[go: up one dir, main page]

WO2001071510A3 - Method and device pertaining to data transfer - Google Patents

Method and device pertaining to data transfer Download PDF

Info

Publication number
WO2001071510A3
WO2001071510A3 PCT/US2001/007199 US0107199W WO0171510A3 WO 2001071510 A3 WO2001071510 A3 WO 2001071510A3 US 0107199 W US0107199 W US 0107199W WO 0171510 A3 WO0171510 A3 WO 0171510A3
Authority
WO
WIPO (PCT)
Prior art keywords
data transfer
arbiter
request
line
special
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/007199
Other languages
French (fr)
Other versions
WO2001071510A2 (en
Inventor
Glen D Stone
Scott D Smyers
Bruce A Fairman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Electronics Inc
Original Assignee
Sony Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Electronics Inc filed Critical Sony Electronics Inc
Priority to JP2001569633A priority Critical patent/JP2003528393A/en
Priority to EP01920223A priority patent/EP1264240A2/en
Priority to AU2001247299A priority patent/AU2001247299A1/en
Publication of WO2001071510A2 publication Critical patent/WO2001071510A2/en
Publication of WO2001071510A3 publication Critical patent/WO2001071510A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

A device and a method for performing data transfer over a bus. In one embodiment the device comprises a request line adapted for initiating a standard data transfer mode. In turn, the request line is used to send a standard data transfer request to an arbiter. The same request line is further adapted for initiating a special data transfer mode. In turn, the same request line is used to send a special data transfer request to the arbiter. The device also includes a grant line adapted for receiving a grant signal from said arbiter. The same grant line is also adapted for receiving a special grant signal from the arbiter. As such, the present invention provides a bus protocol to that provides different levels of bus requestpriority from the device to the arbiter, while not needing any extra pin. The standard data transfer typically indicates asynchronous transfer, whereas the special data transfer typically indicates isochronous data transfer.
PCT/US2001/007199 2000-03-17 2001-03-07 Method and device pertaining to data transfer Ceased WO2001071510A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2001569633A JP2003528393A (en) 2000-03-17 2001-03-07 Data transfer method and data transfer device
EP01920223A EP1264240A2 (en) 2000-03-17 2001-03-07 Method and device pertaining to data transfer
AU2001247299A AU2001247299A1 (en) 2000-03-17 2001-03-07 Method and device pertaining to data transfer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US52790800A 2000-03-17 2000-03-17
US09/527,908 2000-03-17

Publications (2)

Publication Number Publication Date
WO2001071510A2 WO2001071510A2 (en) 2001-09-27
WO2001071510A3 true WO2001071510A3 (en) 2002-01-31

Family

ID=24103435

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/007199 Ceased WO2001071510A2 (en) 2000-03-17 2001-03-07 Method and device pertaining to data transfer

Country Status (4)

Country Link
EP (1) EP1264240A2 (en)
JP (1) JP2003528393A (en)
AU (1) AU2001247299A1 (en)
WO (1) WO2001071510A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101223986B1 (en) * 2006-02-23 2013-01-18 삼성전자주식회사 Smart card and smart card system supporting plurality of interfaces

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5758105A (en) * 1995-12-04 1998-05-26 International Business Machines Corporation Method and apparatus for bus arbitration between isochronous and non-isochronous devices
US6012116A (en) * 1997-12-31 2000-01-04 Sun Microsystems, Inc. Apparatus and method for controlling data, address, and enable buses within a microprocessor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5758105A (en) * 1995-12-04 1998-05-26 International Business Machines Corporation Method and apparatus for bus arbitration between isochronous and non-isochronous devices
US6012116A (en) * 1997-12-31 2000-01-04 Sun Microsystems, Inc. Apparatus and method for controlling data, address, and enable buses within a microprocessor

Also Published As

Publication number Publication date
JP2003528393A (en) 2003-09-24
AU2001247299A1 (en) 2001-10-03
WO2001071510A2 (en) 2001-09-27
EP1264240A2 (en) 2002-12-11

Similar Documents

Publication Publication Date Title
WO2002032101A3 (en) Cable modem system and method for supporting extended protocols
WO2002056154A3 (en) Usb securing device with keypad
MY125638A (en) Interface interlace
EP1213657A3 (en) Dual interface serial bus
WO2003034313A3 (en) Systems and methods for providing digital rights management compatibility
EP0737924A3 (en) Bus arbritation and data transfer
WO2002039648A3 (en) Bluetooth baseband controller
EP0824239A3 (en) Secondary channel for fibre channel system interface bus
WO2002047401A3 (en) Method of receiving specific information at a mobile terminal
WO2005098634A3 (en) Deadlock avoidance in a bus fabric
WO2006010028A3 (en) System and method for managing content between devices in various domains
US7231473B2 (en) Dual channel universal serial bus structure
WO2002041153A3 (en) System and method for implementing a multi-level interrupt scheme in a computer system
EP1193914A3 (en) Data transmission and reception
CN110663229B (en) Method, microcontroller and transceiver assembly for communicating between microcontroller and transceiver assembly
EP1113281A3 (en) A method and apparatus for circuit emulation
ATE425495T1 (en) METHOD AND SYSTEM FOR DATA TRANSFER
EP1094638A3 (en) Method and apparatus for controlling data networks
EP1484870A3 (en) Communication system and communication control method
WO2001057680A3 (en) Data transaction access system and method
CN100369018C (en) Method and device for sharing equipment in multi-central processing unit system
WO2001071510A3 (en) Method and device pertaining to data transfer
FR2766938B1 (en) SERIAL INTERFACE CIRCUIT AND SIGNAL PROCESSING METHOD ASSOCIATED WITH THIS CIRCUIT
WO2002025449A3 (en) Integrated circuit having a programmable address in an i2c environment
ATE533271T1 (en) METHOD FOR ADAPTING BUS SYSTEMS

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

WWE Wipo information: entry into national phase

Ref document number: 2001920223

Country of ref document: EP

ENP Entry into the national phase

Ref country code: JP

Ref document number: 2001 569633

Kind code of ref document: A

Format of ref document f/p: F

WWP Wipo information: published in national office

Ref document number: 2001920223

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 2001920223

Country of ref document: EP