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WO2001047112A2 - Basculeur bistable a haute vitesse - Google Patents

Basculeur bistable a haute vitesse Download PDF

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Publication number
WO2001047112A2
WO2001047112A2 PCT/US2000/042634 US0042634W WO0147112A2 WO 2001047112 A2 WO2001047112 A2 WO 2001047112A2 US 0042634 W US0042634 W US 0042634W WO 0147112 A2 WO0147112 A2 WO 0147112A2
Authority
WO
WIPO (PCT)
Prior art keywords
terminal
input
switch
terminals
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2000/042634
Other languages
English (en)
Other versions
WO2001047112A3 (fr
Inventor
Morteza Cyrus Afghahi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Priority to EP00992658A priority Critical patent/EP1254515A2/fr
Priority to AU45193/01A priority patent/AU4519301A/en
Publication of WO2001047112A2 publication Critical patent/WO2001047112A2/fr
Anticipated expiration legal-status Critical
Publication of WO2001047112A3 publication Critical patent/WO2001047112A3/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356147—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates
    • H03K3/356156—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the primary-secondary type
    • H03K3/35625—Bistable circuits of the primary-secondary type using complementary field-effect transistors

Definitions

  • This invention relates to bistable electronic circuits and, more particularly, to a high speed flip-flop.
  • Flip-flops have many applications in electronic systems. Speed of operation and power efficiency are important characteristics of a flip-flop.
  • a flip-flop can be controlled by a clock to operate upon a data stream as a latch.
  • a dynamic latch generally is capable of operating at a higher speed and with lower power consumption than a static latch.
  • a static latch is generally more stable than a dynamic latch. In short, both dynamic and static latches have favorable and unfavorable characteristics that need to be compromised in circuit design.
  • a bistable device has first and second complementary input terminals and first and second bistable states that are determined by the polarity of the signal applied to one of the input terminals.
  • a source of an uninverted binary input signal preferably an uninverted data stream, has a first value or a second value.
  • a source of an inverted binary input signal, preferably an inverted data stream has a first value or a second value in complementary relationship to the values of the uninverted input signal.
  • a first source of a trigger signal has one polarity.
  • a second source of a trigger signal has the other polarity.
  • the trigger signals could be the bias potential supplies for the transistors of the bistable device.
  • the first trigger signal is applied to the first input terminal and the second trigger signal is applied to the second input terminal to drive the bistable device into the first stable state when the input signal has the first value.
  • the first trigger signal is applied to the second input terminal and the second trigger signal is applied to the first input terminal to drive the bistable device into the second stable state when the input signal has the second value.
  • the bistable device is triggered in push-pull fashion responsive to the binary input signal.
  • a feature of the invention is a latch that can be converted between a dynamic mode and a static mode.
  • Cross-coupled connections are formed between the output of a first bistable stage and the input of a second bistable stage and between the input of the second bistable stage and the output of the first bistable stage so that the first and second stages are alternately cut off or float.
  • cross-coupled connections are also formed between the output of a third bistable stage and the input of a fourth bistable stage and between the output of the fourth bistable stage and the input of the third bistable stage so that the third and fourth stages are alternately cut off or float.
  • the first and second stages are conditionally connected in parallel and the second and fourth stages are conditionally connected in parallel to form a static latch when the connection is in place and a dynamic latch when the connection is not in place.
  • the latch can be converted between a static mode and a dynamic mode.
  • FIG. 1 is a circuit schematic diagram of a dynamic latch incorporating principles of the invention
  • FIG. 2 is a circuit schematic diagram of a static latch incorporating principles of the invention
  • FIG. 3 is a circuit schematic diagram of a convertible latch incorporating principles of the invention.
  • FIG. 4 is a circuit schematic diagram of a master-slave latch incorporating the principles of the invention.
  • FIG. 5 is a circuit schematic diagram of another master-slave latch incorporating the principles of the invention.
  • a dynamic latch has P-type CMOS transistors 10 and 12 connected in a cross-coupled arrangement to form a bistable device.
  • 10 and 12 are each connected to a supply 14 of positive bias potential.
  • the drains of transistors 10 and 12 are connected to complementary output terminals 15 and 16, respectively.
  • the drain of transistor 10 is connected to the gate of transistor 12 and the drain of transistor 12 is connected to the gate of transistor 10.
  • Complementary input terminals 18 and 20 are coupled by invertors 22 and 24, respectively, to the sources of P-type
  • Invertor 22 comprises a P-type CMOS transistor 22a and an N-type CMOS transistor 22b.
  • Input terminal 18 is connected to the gates of transistors 22a and 22b.
  • the drains of transistors 22a and 22b are connected to the source of transistor 26.
  • the source of transistor 22a is connected to bias supply 14.
  • the source of transistor 22b is connected to a supply of negative bias potential 48.
  • invertor 24 comprises a P-type CMOS transistor 24a and an N-type CMOS transistor 24b.
  • Input terminal 20 is connected to the gates of transistors 24a and 24b.
  • the drains of transistors 24a and 24b are connected to the source of transistor 28.
  • the source of transistor 24a is connected to bias supply 14.
  • the source of transistor 24b is connected bias supply 48. Complementary data streams could be fed to input terminals 18 and 20, respectively.
  • a clock terminal 30 is connected to the gates of transistors 26 and 28.
  • the drains of transistors 26 and 28 are connected to the drains of transistors 10 and 12, respectively.
  • Cross coupled transistors 10 and 12 form a bistable circuit that is triggered responsive to the complementary states of input terminals 18 and 20 upon application of each negative clock pulse to terminal 30.
  • the state of the bistable circuit represents the value of the data at input terminals 18 and 20 when the negative clock pulses are applied thereto.
  • output terminals 15 and 16 retain the same state until the next negative clock pulse.
  • the positive and negative potentials of supplies 14 and 48, respectively, which serve as trigger signals, are applied to output terminals 15 and 16 in push-pull fashion: a positive potential is applied to output terminal 15 as a trigger when a negative potential is applied to output terminal 16 as a trigger, and visa-versa.
  • the bistable circuit operates at high speed, i.e., it transitions rapidly from one state to the other, and does not consume much power.
  • the same reference numerals are used to designate the components in common with the dynamic latch of FIG. 1 .
  • Back-to-back invertors 32 and 34 are connected between output terminals 15 and 16 to form a bistable circuit that is triggered by the states of input terminals 18 and 20 upon application of each negative clock pulse to terminal 30.
  • Invertors 32 and 34 each comprise a pair of complementary CMOS transistors having their gates connected together, their drains connected together and their sources connected to a supply of bias potential. One of the complementary transistors is normally saturated, while the other complementary transistor is cut off.
  • the convertible latch of FIG. 3 has N-type CMOS transistors 40. 42, 44 and 46.
  • the drain of transistor 40 is connected to output terminal 15, the gate of transistor 40 is connected to the gate of transistor 10, and the source of transistor 40 is connected through transistor 42 to a supply 48a of negative bias potential.
  • the source of transistor 40 is connected to the drain of transistor 42 and the source of transistor 42 is connected to bias potential 48a.
  • the drain of transistor 44 is connected to output terminal 16, the gate of transistor
  • a test terminal 50 is connected to the gates of transistors 42 and 46.
  • transistors 42 and 46 conduct, i.e., they are turned on, by negative clock pulses applied to terminal 30.
  • transistor 40 is connected to transistor 10 between bias supplies 14a and 48a to form an inverter, i.e, inverter 34 in FIG. 2.
  • transistor 44 is connected to transistor 12 between bias supplies 14b and 48b to form an inverter, i.e., inverter 32 in FIG. 2.
  • These back-to-back inverters function as a static latch.
  • transistors 42 and 46 stop conducting, so transistors 40 and 44 are no longer connected to transistors 10 and 12. respectively, to form back-to-back inverters, i.e. inverters 32 and 34.
  • a binary "1 " i.e., a high voltage level appears at input terminal 18
  • transistor 10 becomes conductive
  • transistor 12 becomes non-conductive
  • a binary "0" appears at output terminal 16.
  • the latch of FIG. 3 is convertible between a dynamic mode when a positive pulse is not present on terminal 50 and a static mode when a positive pulse is present on terminal 50.
  • the latch To enhance the speed of operation of the static latch it is preferable to design the latch so the conductive transistors float, rather than saturate. This can be done by proper selection of the gain of the transistors. As a result, the transistors can switch faster from a conductive state to a non-conductive state in the same manner as a dynamic latch.
  • the same reference numerals are used to designate the components of a master latch 50 in common with the dynamic latch of FIG. 1 , except that clocking transistors 26 and 28 are N-type, instead of P-type and the clock pulses applied to terminal 30 are positive, instead of negative.
  • the same reference numerals plus 100 are used to designate the components of a slave latch 52 in common with the dynamic latch of FIG. 1 , i.e., transistor 1 10 is in common with transistor 10, etc.
  • Output terminals 15 and 16 of master latch 50 are connected to input terminals 120 and 1 18, respectively of slave latch 52.
  • Clock terminal 30 is connected to the gate of each of clocking transistors 26, 28, 126. and 128 without phase inversion.
  • the state of data applied to input terminals 18 and 20 is stored in master latch 50 at the beginning of each clock cycle and is transferred to slave latch 52 at the middle of each clock cycle, so the state of output terminal 1 16 represents the value of the input data and the state of output terminal 1 15 represents the inverse of the state of the input data.
  • output terminals 15 and 16 of master latch 50 are connected to input terminals 1 18 and 120, respectively of slave latch 52, clock terminal 30 is connected to the gate of each of clocking transistors 126 and 128 with a phase inversion caused by an inverter
  • the state of output terminal 1 15 represents the value of the input data
  • the state of output terminal 1 16 represents the inverse of the state of the input data.
  • inverters 22, 24, 122, and 124 could be constructed as in FIG. 1 , namely with complementary types of transistors 22a and 22b and 24a and 24b connected as shown in FIG. 1 to trigger the bistable devices in push-pull fashion.
  • the described embodiments of the invention are only considered to be preferred and illustrative of the inventive concept; the scope of the invention is not to be restricted to such embodiments.
  • Various and numerous other arrangements may be devised by one skilled in the art without departing from the spirit and scope of this invention.
  • the convertible latch could be implemented in other types of transistor architectures.

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  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

Selon l'invention, un dispositif bistable comprend une première et une seconde borne d'entrée complémentaires et un premier et un second état bistables étant déterminés en fonction de la polarité du signal appliqué à une des bornes d'entrée. Une source de signal d'entrée binaire non inversé, de préférence un flux de données non inversé, possède une première ou une seconde valeur. Une source d'un signal d'entrée binaire inversé, de préférence, un flux de données inversé, possède une première ou une seconde valeur complémentaires des valeurs du signal d'entrée non inversé. Une première source de signal déclencheur est dotée d'une polarité. Une seconde source d'un signal déclencheur est dotée de l'autre polarité. Le premier signal déclencheur est appliqué à la première borne d'entrée et le second signal déclencheur est appliqué à la seconde borne d'entrée afin d'entraîner le dispositif bistable dans le premier état stable au moment où le signal d'entrée possède la première valeur. Le premier signal déclencheur est appliqué à la seconde borne d'entrée et le second signal déclencheur est appliqué à la première borne afin d'entraîner le dispositif bistable dans le second état stable au moment où le signal d'entrée possède la seconde valeur.
PCT/US2000/042634 1999-12-13 2000-12-07 Basculeur bistable a haute vitesse Ceased WO2001047112A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP00992658A EP1254515A2 (fr) 1999-12-13 2000-12-07 Basculeur bistable a haute vitesse
AU45193/01A AU4519301A (en) 1999-12-13 2000-12-07 High speed flip-flop

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17059499P 1999-12-13 1999-12-13
US60/170,594 1999-12-13

Publications (2)

Publication Number Publication Date
WO2001047112A2 true WO2001047112A2 (fr) 2001-06-28
WO2001047112A3 WO2001047112A3 (fr) 2002-07-11

Family

ID=22620505

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/042634 Ceased WO2001047112A2 (fr) 1999-12-13 2000-12-07 Basculeur bistable a haute vitesse

Country Status (3)

Country Link
EP (1) EP1254515A2 (fr)
AU (1) AU4519301A (fr)
WO (1) WO2001047112A2 (fr)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57160213A (en) * 1981-03-27 1982-10-02 Toshiba Corp Flip-flop circuit
US4768167A (en) * 1986-09-30 1988-08-30 International Business Machines Corporation High speed CMOS latch with alternate data storage and test functions
JPH07101553B2 (ja) * 1989-02-15 1995-11-01 三菱電機株式会社 バッファ回路およびその動作方法
US5023480A (en) * 1990-01-04 1991-06-11 Digital Equipment Corporation Push-pull cascode logic
US5384493A (en) * 1991-10-03 1995-01-24 Nec Corporation Hi-speed and low-power flip-flop
JPH09232920A (ja) * 1996-02-28 1997-09-05 Nec Ic Microcomput Syst Ltd フリップフロップ回路

Also Published As

Publication number Publication date
WO2001047112A3 (fr) 2002-07-11
EP1254515A2 (fr) 2002-11-06
AU4519301A (en) 2001-07-03

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