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WO2000018118A1 - Dispositif et procede permettant de fusionner les intervalles de suppression verticale - Google Patents

Dispositif et procede permettant de fusionner les intervalles de suppression verticale Download PDF

Info

Publication number
WO2000018118A1
WO2000018118A1 PCT/US1999/021874 US9921874W WO0018118A1 WO 2000018118 A1 WO2000018118 A1 WO 2000018118A1 US 9921874 W US9921874 W US 9921874W WO 0018118 A1 WO0018118 A1 WO 0018118A1
Authority
WO
WIPO (PCT)
Prior art keywords
memories
data
service
memory
multiplexer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1999/021874
Other languages
English (en)
Other versions
WO2000018118A8 (fr
Inventor
Anthony Cucinotta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Arris Technology Inc
Original Assignee
General Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Instrument Corp filed Critical General Instrument Corp
Priority to AU10944/00A priority Critical patent/AU1094400A/en
Priority to US09/787,601 priority patent/US7391471B1/en
Publication of WO2000018118A1 publication Critical patent/WO2000018118A1/fr
Anticipated expiration legal-status Critical
Publication of WO2000018118A8 publication Critical patent/WO2000018118A8/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
    • H04N7/087—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical blanking interval only
    • H04N7/088—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the vertical blanking interval only the inserted signal being digital

Definitions

  • This invention is related to cable television (CATV) and wireless transmission
  • the invention is related to an apparatus for merging
  • VBIs vertical blanking intervals
  • the challenge is offering more channels to subscribers within the spectrum
  • Ancillary information services are typically transmitted using existing
  • the ancillary information is transmitted in the VBI and decoded at a television in order to display the ancillary information along with
  • Ancillary information typically includes text, for example
  • VBI it is desirable to merge several VBIs into the bandwidth allotted for a single
  • VBI in order to nrinimize the overall bandwidth required for the television
  • VBIs are merged by sequentially writing selected
  • VBIs of a field to a first memory, then writing selected VBIs of a second field to a
  • This process is duplicated for a second service such that during the read intervals,
  • Figure 1 is a diagram of the merging system according to the present
  • FIG. 2 is a diagram VBIs from two services merged into a single VBI.
  • the first half 20 is connected to a first service which will be referred to as service A
  • a field programable gate array (FPGA) 40 is connected to a field programable gate array (FPGA) 40 .
  • control circuits having similar functionality may be utilized as a substitute for this
  • the FPGA 40 is preferably controlled by a microprocessor on a Zilog
  • microprocessors serving similar FPGA control functions may be utilized as a
  • the FPGA 40 is connected to an input multiplexer 24 which receives input
  • the input multiplexer 24 has a first output 41 connected to number 1 data bus and a second output 42 connected to number 2 data
  • Memory 26 is connected to number 1 data bus at 46 and is
  • An address bus 45 extends from the memory 26 to a first control
  • the first control multiplexer 28 has a first input 52 connected to the
  • control multiplexers 62, 63 connected to a corresponding input on control multiplexers 62, 63 in the second half
  • output port 54 is also connected to corresponding outputs on control
  • the number 1 data bus also extends to an output multiplexer 34 at port 36.
  • the output multiplexer is connected to the number 2 data bus at port 38.
  • memory 30 is connected to the number 2 data bus at port 50 and to an address bus
  • the address bus 49 extends to a second control multiplexer 32 having
  • an I/O select port 56 being connected to the input 52 of the first control multiplexer
  • An output port 58 is connected to the output port 54 of the first control
  • Both ports 56 and 58 are also connected to the FPGA 40 and to
  • An output data bus 59 extends from the output multiplexer 34 and is coupled to a complimentary output
  • multiplexer 64 of the second half 60 is the multiplexer 64 of the second half 60.
  • Figure 2 shows a
  • VBI could be sized accordingly to receive all the selected lines of service A and all
  • the merged VBI can contain some of the lines from each service as
  • control is achieved by programming the FPGA 40 using a microprocessor (not
  • service A is sampled at a desirable sample rate
  • Service A sample data 22 is fed into the input multiplexer 24.
  • FPGA 40 controls the input multiplexer 22 to send the sample data either to port 41
  • the FPGA 40 controls
  • each memory 26, 30 so that, while memory 26 is receiving data from the input
  • multiplexer 22 along number 1 data bus (write cycle), memory 30 is being read from
  • VBI VBI
  • Each of the memories 26, 30 are controlled through a respective control
  • the FPGA 40 sends input addresses along the input address bus
  • Data is read from the memory 26 according to addresses sent by
  • the memory in a non-sequential order as directed by addresses sent from the FPGA 40 through output port 54 of the control multiplexer 28. For example, as shown in
  • the FPGA 40 could optionally be programmed to send addresses to
  • the memory 26 such that data is read out sequentially.
  • the data in the form of
  • VBIs sampled VBIs is read along number 1 data bus into port 36 of the output multiplexer
  • the number 2 data bus has data flowing from the input multiplexer 24 into the
  • memory 66 when memory 26 is in a read cycle, memory 66 is also in a read cycle. Accordingly,
  • memory 68 when memory 30 is in a read cycle, memory 68 is also in a read cycle. The same
  • data bus 59 therefore receives some line samples from output multiplexer 34 and
  • the FPGA 40 controls the selection of lines from each service. Therefore,
  • An advantage of this invention is that several services VBIs may be

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)

Abstract

L'invention concerne un dispositif et un procédé permettant de fusionner l'information transmise dans les intervalles de suppression verticale correspondant à plusieurs services, de manière à obtenir un seul intervalle de suppression verticale. Le système comprend une paire de mémoires pour les différents services, chaque mémoire étant basculée entre des cycles de lecture et d'écriture. Lorsque la première mémoire est dans un cycle d'écriture, la seconde mémoire est dans un cycle de lecture et vice versa. Un prédiffusé programmable commande les paires de mémoires, de manière à fusionner les intervalles de suppression verticale.
PCT/US1999/021874 1998-09-21 1999-09-21 Dispositif et procede permettant de fusionner les intervalles de suppression verticale Ceased WO2000018118A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU10944/00A AU1094400A (en) 1998-09-21 1999-09-21 Apparatus and method for merging vertical blanking intervals
US09/787,601 US7391471B1 (en) 1999-09-21 1999-09-21 Apparatus and method for merging vertical blanking intervals

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10118198P 1998-09-21 1998-09-21
US60/101,181 1998-09-21

Publications (2)

Publication Number Publication Date
WO2000018118A1 true WO2000018118A1 (fr) 2000-03-30
WO2000018118A8 WO2000018118A8 (fr) 2001-06-21

Family

ID=22283391

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/021874 Ceased WO2000018118A1 (fr) 1998-09-21 1999-09-21 Dispositif et procede permettant de fusionner les intervalles de suppression verticale

Country Status (2)

Country Link
AU (1) AU1094400A (fr)
WO (1) WO2000018118A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1287679A4 (fr) * 2000-04-21 2009-06-17 Goldpocket Interactive Inc Systeme et procede permettant de fusionner des donnees televisuelles interactives et des donnees de sous-titrage codees

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0018783A1 (fr) * 1979-04-25 1980-11-12 Westinghouse Electric Corporation Système de chiffrage et de déchiffrage pour des signaux de son de télévision
GB2286321A (en) * 1994-02-07 1995-08-09 Videotron Groupe Ltee Data transmission to a mass audience

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0018783A1 (fr) * 1979-04-25 1980-11-12 Westinghouse Electric Corporation Système de chiffrage et de déchiffrage pour des signaux de son de télévision
GB2286321A (en) * 1994-02-07 1995-08-09 Videotron Groupe Ltee Data transmission to a mass audience

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1287679A4 (fr) * 2000-04-21 2009-06-17 Goldpocket Interactive Inc Systeme et procede permettant de fusionner des donnees televisuelles interactives et des donnees de sous-titrage codees

Also Published As

Publication number Publication date
WO2000018118A8 (fr) 2001-06-21
AU1094400A (en) 2000-04-10

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