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WO2000005765A1 - Procede de fabrication de substrats d'adaptation de cablage pour boitiers de puces de semi-conducteur - Google Patents

Procede de fabrication de substrats d'adaptation de cablage pour boitiers de puces de semi-conducteur Download PDF

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Publication number
WO2000005765A1
WO2000005765A1 PCT/CH1999/000011 CH9900011W WO0005765A1 WO 2000005765 A1 WO2000005765 A1 WO 2000005765A1 CH 9900011 W CH9900011 W CH 9900011W WO 0005765 A1 WO0005765 A1 WO 0005765A1
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WIPO (PCT)
Prior art keywords
starting materials
electrically conductive
masks
dielectric
plasma ablation
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PCT/CH1999/000011
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German (de)
English (en)
Inventor
Walter Schmidt
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Dyconex Patente AG
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Dyconex Patente AG
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Publication of WO2000005765A1 publication Critical patent/WO2000005765A1/fr
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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0166—Polymeric layer used for special processing, e.g. resist for etching insulating material or photoresist used as a mask during plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0548—Masks
    • H05K2203/0554—Metal used as mask for etching vias, e.g. by laser ablation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1536—Temporarily stacked PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns

Definitions

  • the present invention relates to semiconductor chips and relates in particular to the method for producing rewiring substrates for packages for semiconductor chips (IC packages) in accordance with the definition of the claims.
  • Such rewiring substrates adapt the connection grid of the ICs to the relatively coarse size of the circuit board.
  • Such rewiring substrates can be made from etched or stamped metal "spiders", or can also consist of ceramic or organic substrates.
  • An IC mounted on such a rewiring substrate is also referred to as a packaged IC (IC package) Rewiring substrate with the encapsulation, if applicable, also referred to as an IC package.
  • IC package packaged IC
  • the IC connectors are located on the side of the package. This arrangement allows direct visual inspection of the solder connections when soldering the ICs with a P WB.
  • the IC industry developed smaller and smaller connection grids to allow more and more side IC connections per pack.
  • the connection grid of high-performance ICs is 0.3 - 0.5 mm, which makes processing and soldering of such IC packages difficult and is not economical due to the low yield.
  • IC packs have been developed, the connections of which are not arranged on the side of the periphery, but rather flat.
  • the I / Os are arranged in an x / y grid (array).
  • Such packaging is called ball grid array packages (BGAs) or ⁇ ball grid array packages ( ⁇ BGAs) or chip scale packages (CSPs).
  • BGAs ball grid array packages
  • ⁇ BGAs ⁇ ball grid array packages
  • CSPs chip scale packages
  • Such array packs are currently being launched on the market. While in BGA packs the rewiring substrate is much larger than the bare silicon chip, the rewiring substrate in ⁇ BGAs or CSPs is practically the same size as the bare IC chip.
  • This packaging therefore also enables a very high packing density of such components on the printed circuit board and is therefore considered the next generation of IC packaging.
  • the length of the electrical connection between the IC and the printed circuit board is minimized, which also has a very positive influence on the electrical properties of the electronic systems made therefrom, in particular at higher switching frequencies.
  • the most important advantage, however, is that IC packs with connection surfaces arranged in a grid ensure a significantly higher connection density than is possible with traditional IC packs with connections arranged on the side.
  • the number of connections with a grid arrangement is X times Y compared to a connection number of 2X + 2Y with peripheral arrangement of the connections.
  • the grid of the connections can be significantly enlarged with the same number of connections, which enables a higher yield when soldering these packages to the printed circuit board.
  • connection areas for the IC and grid-shaped connection areas for the printed circuit board connections are structured photochemically on a flexible polyimide film, on the side laminated with a copper film.
  • the polyimide film is then removed locally from its rear side by means of laser ablation in order to form access holes and / or accesses to the connection surfaces of the front side which are arranged in the form of a grid.
  • solder balls are placed in the access holes and soldered.
  • the rewiring substrate prepared in this way is mechanically and the Usually peripheral IC connections are electrically connected to the IC by a bonding process.
  • the IC packaged in this way - with grid-shaped connections opposite the next connection level (printed circuit board) - can be electrically pre-tested and can be processed like a normal component.
  • a disadvantage of this method of manufacturing IC packages is that laser ablation is a sequential process, which increases the cost of manufacturing the rewiring substrates.
  • the method using laser ablation is all the more complex since such IC packs have very small dimensions and highly compressed current path and connection assignments, which results in a very high hole density and accordingly extends the production time of the rewiring substrates.
  • a further disadvantage is that the bottom of the access holes and / or accesses is contaminated during laser ablation and must therefore be cleaned before the solder balls are soldered. This cleaning process represents an additional, time-consuming and cost-intensive work step. In particular, it has been found that when using polyimide films, residues arise which cannot be completely removed even when using plasma.
  • FIG. 1 shows, by way of example, the development of the compression and reduction of IC packs with peripheral connections towards grid surfaces arranged with a grid
  • FIG. 3 shows a first advantageous variant of a production method for rewiring substrates and corresponding IC packs by means of plasma ablation
  • FIG. 5 shows top views of a starting material for the production of rewiring substrates, in accordance with FIG. 4, without and with a mechanical mask lying on it,
  • 6 shows a disadvantageous variant of a production method for rewiring substrates and corresponding IC packs by means of plasma ablation
  • 7 shows a further advantageous variant of a production method for rewiring substrates and corresponding IC packs by means of plasma ablation and differentiated chemical etching
  • FIG. 8 shows a further advantageous variant of a production method for rewiring substrates and corresponding IC packs by means of plasma ablation and differentiated chemical etching
  • FIG. 11 shows a further advantageous variant of a production method for rewiring substrates and corresponding IC packs by means of plasma ablation using mechanical masks
  • 12 shows a first preferred variant of a pressing method for pressing on mechanical masks with permanent magnets for producing rewiring substrates for corresponding IC packages
  • 13 shows a further preferred variant of a pressing method for pressing on mechanical masks for producing rewiring substrates for corresponding IC packs using inert oil films
  • 16 shows a further preferred variant of a pressing process for pressing on mechanical masks made of bimetal for producing rewiring substrates and corresponding IC packs.
  • FIG. 1 shows the development of the compression and reduction of IC packs from peripherally arranged connections with coarse (FIG. 1 a) and fine grid dimensions (FIG. 1 b) to packs with connections arranged in a grid.
  • Fig. Lc shows a pack with a relatively coarse and ld a pack with a fine pitch.
  • FIG. 1c shows a ball grid array package (BGA), while FIG. 1d shows a comparatively very small and highly compressed ⁇ ball grid array package ( ⁇ BGA) or chip-scale package (CSP).
  • BGA ball grid array package
  • ⁇ BGA chip-scale package
  • FIG. 2 shows an example of a known production method for IC packs with connections arranged in a grid by means of laser ablation.
  • Fig. 2a shows one Polyimide foil 1, which is laminated on one side with copper foil 2.
  • the copper foil is photochemically structured in current paths and connection areas 2 'for the IC.
  • the polyimide film is then removed locally from its rear side by means of laser ablation, in order to form access holes and / or accesses 1 ′ to current paths on the front side (FIG. 2c).
  • solder balls 3 are placed in the access holes and soldered to a rewiring substrate CSP.
  • an IC 5 is mounted on this rewiring substrate CSP via an organic intermediate layer 4 (FIG. 2d).
  • the IC is then mechanically and electrically connected to the rewiring substrate CSP, so that the IC is in the form of a package.
  • This now finished IC package can be mounted on printed circuit boards 6, for example (FIG. 2e).
  • Plasma ablation is a known and proven method and is successfully used by the applicant in the DYCOstrate® method for the production of blind holes and through holes in printed circuit boards and foil printed circuit boards.
  • the application of plasma ablation to the production of rewiring substrates for corresponding IC packages is new and has decisive technological and economic advantages.
  • an advantageously organic dielectric for example a thin polyimide foil
  • the starting material which in the present variant is laminated on one side with a layer of electrically conductive material 2, for example a thin copper foil.
  • electrically conductive material for example a thin copper foil.
  • These foils are typically 10 to 100 ⁇ m thick. Of course, thicker and thinner foils can also be used.
  • Other dielectrics that can be processed using plasma can also be used, and other electrically conductive materials that can be processed using chemical processes can also be used.
  • this starting material is covered, for example, on both sides with photoresist 7,7 '. This photoresist is exposed and developed into chemical masks 70, 70 '(FIG. 3c).
  • the chemical masks 70, 70 ' have mask images with structures according to which the underlying electrically conductive material and dielectric are accessible.
  • a first chemical mask 70 on the front of the starting material is used to produce current paths and connection areas in the position of electrically conductive material 2.
  • a second chemical mask 70 'on the back of the starting material is used to produce access holes and / or accesses in the dielectric 1.
  • the layer of electrically conductive material 2 is structured in chemical processes, for example in wet chemical processes such as chemical etching in current paths and connection areas 2 ′ (FIG. 3d).
  • two such photochemically structured starting materials are combined to form a sandwich structure in such a way that they are connected to one another via the current paths and connection areas 2 ′ on the front sides and that the second chemical masks 70 ′ on the rear sides are directed outwards.
  • This sandwich structure is subjected to a plasma ablation process.
  • the dielectric 1 and the developed photoresist of the chemical masks 70 ' are organic in nature and can therefore be processed by plasma. 3f, only exposed areas of chemical masks 70 'and dielectric 1 accessible according to the mask image of these chemical masks 70' are removed.
  • the exposed rear sides of two starting materials are advantageously processed simultaneously, while the front sides of these two starting materials are covered in a protective manner and are not treated. Due to different plasma ablation rates of the dielectric and the developed photoresist, the mask covering is underestimated to a certain extent.
  • the dielectric is usually removed by plasma more slowly than the developed photoresist.
  • Such parameters that control the plasma ablation can be set via the choice of dielectric and photoresist material, as well as via the thickness and fineness of the mask structures and the thickness of the dielectric.
  • solder balls 3 are placed in access holes and / or accesses 1 'on the rear side of the starting material and soldered with current paths and connection areas 2' on the front side of the starting material according to FIG. 3h to a rewiring substrate CSP.
  • an IC 5 is mechanically and electrically connected to the rewiring substrate CSP via an organic intermediate layer 4 to form an IC package.
  • rewiring substrates can be produced which functionally match those in the process 2 by means of laser ablation.
  • IC packs can be processed further and, for example, analogously to FIG. 2e, mounted on printed circuit boards.
  • FIG. 4 shows a further advantageous variant of a production method for rewiring substrates for IC packages by means of plasma ablation.
  • This further variant largely corresponds to that according to FIG. 3, so that reference is made to this description and, above all, the differences in this regard are described below.
  • mechanical masks 80, 80 ' are attached to the front and back of a photochemically structured starting material according to FIG. 4d.
  • Such mechanical masks consist, for example, of metal such as copper, aluminum, brass, beryllium brass, steel, etc. Of course, other materials can also be used for mechanical masks. It is advantageous that these mechanical masks consist of materials that are resistant to plasma ablation.
  • the mechanical masks are provided with mask images, according to the structures of which the starting material is treated by plasma ablation. E.g.
  • a first mechanical mask 80 completely covers the front side of the starting material so that it is not treated, while another, second mechanical mask 80 'on the back side of the starting material has a mask image similar to the underlying second chemical mask 70', so that only a minimum of the developed photoresist is exposed to the plasma. Accordingly, according to FIG. 4f, minimal areas of the second chemical mask 70 ′ and also are exposed only by the mask image of the second mechanical mask 80 ′ regions partially accessible from the dielectric 1 by the mask image of this second chemical mask 70 '. Due to different plasma ablation rates of the developed photoresist and the dielectric, the dielectric is usually removed by plasma more quickly than the developed photoresist. More or less pronounced undercuts occur below the mechanical mask 80 '. According to FIG.
  • access holes and / or accesses 1 ' are thus formed in the dielectric, which have sloping walls and extend to the electrically conductive material.
  • the exposed second chemical mask 70 ' is only minimally exposed to the plasma and is accordingly only slightly removed.
  • solder balls 3 are placed in access holes and / or accesses on the rear side of the starting material according to FIG. 4h and soldered with current paths on the front side of the starting material.
  • the rewiring substrate CSP is now complete. It is not explicitly shown how an IC is mounted on this rewiring substrate CSP and mechanically and electrically connected to it. This takes place, for example, in analogy to the variant according to FIG. 3j.
  • a rewiring substrate CSP can also be formed in the method according to FIG. 4, which is identical to that produced in the method according to FIG. 3.
  • the main difference between these two variants is the use of mechanical masks in the process according to FIG. 4, as a result of which a minimum of photoresist is exposed to the plasma and the plasma is therefore not weakened by the removal of such photoresist, so that the plasma ablation rate is optimal stays high.
  • FIGS. 5 a and 5 b show a plan view of the starting material for the production of rewiring substrates.
  • FIG. 5a corresponds to FIG.
  • FIG. 4d shows the rear side of the starting material without a mechanical mask applied, so that a significant surface of the developed photoresist is exposed to the chemical mask 70 '.
  • FIG. 5b corresponds to FIG. 4e and shows the back of the starting material with a mechanical mask 80 ′ applied.
  • FIG. 6 shows a disadvantageous variant of a production method for rewiring substrates for IC packages by means of plasma ablation. This further variant largely corresponds to that according to FIGS. 3 and 4, so that reference is made to this description and, above all, the differences in this regard are described below.
  • a starting material consists of a dielectric 1 laminated on both sides with conductive material 2.20 (FIG. 6a).
  • conductive materials 2, 20 are, for example, thin copper foils
  • the dielectric 1 is, for example, a thin polyimide foil.
  • a first layer of electrically conductive material 2 is attached to the front of the starting material
  • a further layer of electrically conductive material 20 is attached to the back of the starting material.
  • Both layers of electrically conductive material 2.20 are covered with photoresist 7.7 '(FIG. 6b) and this photoresist 7.7' is advantageously exposed simultaneously and developed into chemical masks 70.70 '(FIG. 6c).
  • a first chemical mask 70 on the front of the starting material is used for Production of access holes and or accesses in the dielectric 1.
  • the electrically conductive material 2 on the front side is structured according to the first chemical mask 70 into a mechanical mask 2 ', while advantageously the electrically conductive material 20 on the rear side according to the second chemical mask 70'. is structured in current paths and connection areas 20 '(FIG. 6d).
  • An advantage of this variant of the production process is the high dimensional stability of the photochemically structured starting material with layers of electrically conductive materials attached on both sides, which have a stiffening effect, which simplifies the further processing of this starting material. It is also advantageous that photochemically structured layers of electrically conductive material can be used as mechanical masks.
  • photoresist material of the chemical masks is removed, for example, by stripping.
  • two such photochemically structured starting materials are combined to form a sandwich structure in such a way that they are connected to one another via their rear sides and that their front sides are directed outwards.
  • the structured layers of electrically conductive material 2 'on the front sides serve as mechanical masks in a plasma ablation process.
  • Dielectric 1 accessible to the plasma is removed in accordance with the mask image of these mechanical masks.
  • the exposed front sides of two starting materials are processed at the same time, while the backs of these two starting materials are protected and are not treated.
  • the plasma ablation causes a certain undercut of the mask covering.
  • the layers of electrically conductive material 2 'attached to these front sides and serving as mechanical masks must be removed. Otherwise you would create short circuits between the solder balls, for example. 6h, these layers of electrically conductive material 2 'are removed. This is done, for example, by wet chemical etching, in which all exposed electrically conductive material is removed. This means that not only the outer layers of electrically conductive material 2 ', but also exposed areas of the inner layers of electrically conductive material 20' of this sandwich structure are removed. The inner layers of electrically conductive material of this sandwich structure modified in this way are designated 20 ".
  • solder balls 3 are placed in access holes and / or accesses to the front of the starting material Previously modified the layer of electrically conductive material, soldering of the solder balls 3 is not possible since the solder balls 3 on the front side of the starting material do not make any electrical contact with the modified layer of electrically conductive material 20 ′′ on the back side of the starting material according to FIG. 6i.
  • a first remedy for such an undesirable modification of a layer of electrically conductive material in the variant of a manufacturing method of rewiring substrates for IC packages by means of plasma ablation according to FIG. 6 is the advantageous variant of a manufacturing method of rewiring substrates using plasma ablation according to FIG. 7.
  • This further variant corresponds largely that according to FIG. 6, so that reference is made to this description and above all the differences in this regard are described.
  • 7 is a starting material for this purpose used with a reinforced layer of electrically conductive material 20 on its back.
  • the layers of electrically conductive materials 2, 20 on the front and the back of the starting material are of different thicknesses.
  • 7a shows schematically and by way of example the use of copper foils 2, 20 of different thicknesses.
  • solder balls 3 are placed in access holes and / or accesses to the front of the starting material and soldered with current paths on the back of the starting material according to FIG. 7g.
  • the rewiring substrate CSP is finished and can then be mechanically and electrically connect with an IC to form an IC package (in analogy to the previously described variants).
  • a further remedy for such an undesirable modification of a layer of electrically conductive material in the variant of a manufacturing method of rewiring substrates by means of plasma ablation according to FIG. 6 creates the advantageous variant of a manufacturing method of rewiring substrates by means of plasma ablation according to FIG. 8.
  • This further variant largely corresponds to that according to Fig. 6, so that reference is made to this description and above all the differences in this regard are described.
  • a differentiated chemical etching takes place. 8a and 8b, such small access holes and / or accesses are formed in the structured dielectric 1 'in the starting material that during subsequent chemical etching processes, accordingly, little etching-reactive medium penetrates into these access holes and / or accesses and accordingly areas exposed to little etching-reactive medium can attack an unreinforced layer of structured electrically conductive material 20 'on the back of the starting material. In this case, a differentiated chemical etching takes place due to the small size of the access holes and / or accesses.
  • FIG. 1 When layers of electrically conductive materials 2, 20 of the same thickness are used, exposed areas of the layers of electrically conductive material 20 ′ are thinned out due to these more or less large access holes and / or accesses. With sufficiently small accesses such as are used for IC packs with connections arranged in a grid and very small grid dimensions, only a thinning and no disadvantageous modification of these layers of electrically conductive material 20 'on the rear sides of the starting materials takes place. In this regard, FIG.
  • FIGS. 7e and 7f show schematically and by way of example the use of copper foils 2, 20 of equal thickness and more or less pronounced thinning and etching through the layer of electrically conductive material 20 'on the back of the starting material as a function of the size of the access openings in the structured dielectric 1'.
  • 8a and 8b thus correspond to parts of FIGS. 7e and 7f;
  • Fig. 8c corresponds to a part of Fig. 7g.
  • the advantageous variant according to FIG. 9 shows a further remedy with regard to such an undesirable modification of a layer of electrically conductive material in the variant of a production method for rewiring substrates by means of plasma ablation according to FIG. 6.
  • This further variant largely corresponds to that according to FIG. 6, so that on this description is referred to and the differences in this regard are described below.
  • a two-stage plasma ablation takes place in the variant according to FIG. 9.
  • a starting material according to FIG. 6a is photochemically structured in identical method steps according to FIGS. 6b-6e and assembled according to FIG. 9a in a manner identical to that according to FIG. 6f to form a sandwich structure.
  • a two-stage plasma ablation is carried out in the variant according to FIGS. 9b and 9d.
  • dielectric 1 is plasma-treated incompletely in accordance with the mask images of the structured layers of electrically conductive material 2 ′ functioning as a mechanical mask.
  • the plasma ablation is interrupted before the inner layers of electrically conductive material 20 'are accessible via access holes and / or accesses to be made in the dielectric 1 *.
  • inner layers of electrically conductive material 20 'of the sandwich structure are replaced by a remaining one thin layer of dielectric 1 * covered.
  • This cover serves as a protective layer during the subsequent removal of the mechanical masks according to FIG. 9c (in analogy to FIG. 6h). Because of this protective layer of dielectric 1 *, the inner layers of electrically conductive material 20 'of the sandwich structure are not attacked when the mechanical masks are removed.
  • access holes and / or accesses 1 ' are completely exposed in the dielectric. Since the mechanical masks are now missing, the dielectric is fully exposed.
  • solder balls 3 are placed in access holes and / or accesses on the front side of the starting material and soldered with current paths on the back side of the starting material.
  • the rewiring substrate CSP is now ready and can then be mechanically and electrically connected to an IC to form an IC package (in analogy to the variants previously shown).
  • FIG. 10 shows a further advantageous variant of a production method for rewiring substrates by means of plasma ablation.
  • This further variant largely corresponds to that according to FIG. 6, so that this description is referred to and the differences in this regard are described below.
  • FIGS. 10f and 10g are identical to those according to FIGS. 6f and 6g.
  • a further photochemical structuring is carried out in the present variant and in accordance with FIG. 10h.
  • the access holes and / or accesses in the dielectric and the remnants of the outer layers of electrically conductive material 2 ′ functioning as mechanical masks are advantageously made with a liquid Photoresist 9.9 'covered.
  • this photoresist 9.9 ' is exposed and, according to FIG. 10J, this photoresist is developed into further chemical masks 90.90'.
  • These chemical masks 90, 90 ' have mask images with structures according to which underlying outer layers of electrically conductive material 2' are accessible.
  • FIG. 10k all of these outer layers of electrically conductive material 2 'are removed in chemical processes, for example in wet-chemical processes. The remaining photoresist material of these chemical masks is then removed, for example by stripping, as shown in FIG. 101.
  • solder balls 3 are placed in access holes and / or accesses on the front side of the starting material and soldered with current paths on the back side of the starting material according to FIG. 101.
  • the rewiring substrate CSP is now ready and can then be started Connect mechanically and electrically with an IC to form an IC package (in analogy to the previously shown variants).
  • FIG. 11 shows a further advantageous variant of a production method for rewiring substrates by means of plasma ablation.
  • This further variant largely corresponds to that according to FIG. 4, so that reference is made to this description and, above all, the differences in this regard are described below.
  • the developed photoresist is removed before the plasma ablation.
  • two such starting materials are combined to form a sandwich structure, in such a way that they are connected to one another via their front sides structured in current paths and connection areas 2 ′ and that their rear sides to the outside are directed.
  • solder balls 3 are placed in access holes and or accesses on the rear side of the starting material and are soldered with current paths on the front side of the starting material according to FIG. 11c.
  • the rewiring substrate CSP is now ready and can then be mechanically and electrically connected to an IC to form an IC package (in analogy to the variants previously shown).
  • FIGS. 12-16 schematically show parts of preferred embodiments of presses and variants of pressing processes.
  • a sandwich structure according to FIG. 11a is pressed together by means of permanent magnets 100, 100 '.
  • the permanent magnets 100,100 ' are preferably fastened in areas of the sandwich structure in which a high and / or uniform contact pressure is desired.
  • Such permanent magnets 100, 100 ' can be connected to the mechanical masks 80, 80' in a separable or inseparable manner.
  • chemically inert oil films 110, 110' are, for example, silicone oils as are used in vacuum pumps.
  • chemically inert oil films are applied between the starting materials, for example in the form of a sandwich structure, and the mechanical masks 80, 80 ', such that no etching-reactive medium can get to the starting materials through gaps which are not provided, and that plasma ablation only occurs along the structures of the mechanical ones Masks 80.80 'is done.
  • FIG 14 shows a further embodiment of a press, in which a starting material is placed around a cylinder 120 and in which a mechanical mask 80 is pressed onto the starting material placed around the cylinder 120 via a pressing device 81, for example via a spring or a clamp becomes. In this case, radial pressure is applied.
  • 15 shows in detail how mechanical masks are pressed radially against starting materials.
  • 15a and 15b show how a starting material to be processed by plasma ablation, for example in the form of a sandwich structure, is stretched between two mechanical masks 80, 80 '.
  • the starting materials lie with their front sides on the inside against one another via photochemically structured electrically conductive materials 2 ′ (in analogy to FIG. 11 a).
  • the mechanical masks 80, 80 ' are against the outer layers of the Dielectric 1 of the starting materials pressed. This is advantageously done by means of registration bolts 82.
  • These registration bolts 82 register the starting materials in relation to the mechanical masks.
  • the starting materials and the mechanical masks advantageously have openings through which the registration bolts 82 are inserted.
  • these registration bolts are rivets, screws, etc.
  • this composite is bent radially in one direction, for example, which creates forces which press the mechanical masks 80, 80 'against the sandwich structure.
  • Fig. 15d shows this radial bending and the resulting forces schematically by means of bending lines and force arrows.
  • 15e shows the composite after plasma ablation from the access holes and / or accesses 1 'in the dielectrics.
  • 15f shows the redissolved plasma-treated starting materials. The further processing of these plasma-treated starting materials has already been described above, so reference is made to this description. Of course, other possibilities of mutual registration of these elements are also available to the person skilled in the art with knowledge of the present invention.
  • the mechanical masks 80, 80 ' are produced from a bimetallic composite.
  • the mechanical masks consist of one or more metal layers with different thermal expansion.
  • 16a shows this arching of the mechanical masks 80, 80 'schematically by means of bending lines.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Procédé de fabrication de substrats d'adaptation de câblage pour boîtiers de puces de semi-conducteur, qui, sur la base de matériaux de départ constitués d'une couche diélectrique (1) et d'une ou deux couches de matière électriquement conductrice (2, 20), consiste à former des pistes conductrices et des plages de connexion (2', 20') par structuration photochimique dans une couche de matière électriquement conductrice (2, 20), ainsi que des trous d'accès et/ou des accès (1') dans le diélectrique (1') par ablation au plasma. Des billes de soudage (3) sont placées dans les trous d'accès et/ou accès et sont soudées avec les pistes conductrices et les plages de connexion (2', 20'). Selon ledit procédé, des boîtiers de puces sont formés par connexion électrique de circuits intégrés (5) avec les pistes conductrices et plages de connexion (2') de ces substrats d'adaptation de câblage ainsi formés.
PCT/CH1999/000011 1998-07-22 1999-01-12 Procede de fabrication de substrats d'adaptation de cablage pour boitiers de puces de semi-conducteur Ceased WO2000005765A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US9370798P 1998-07-22 1998-07-22
US60/093,707 1998-07-22
US9659298P 1998-08-14 1998-08-14
US60/096,592 1998-08-14

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WO2000005765A1 true WO2000005765A1 (fr) 2000-02-03

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0072673A2 (fr) * 1981-08-13 1983-02-23 Minnesota Mining And Manufacturing Company Film support à conducteurs pour l'interconnexion électrique entre des composants électroniques et un circuit externe
EP0452506A1 (fr) * 1989-11-06 1991-10-23 Nippon Mektron, Ltd. Procede de production d'une plaquette a circuits flexible pour le montage de circuits integres
US5091339A (en) * 1990-07-23 1992-02-25 Microelectronics And Computer Technology Corporation Trenching techniques for forming vias and channels in multilayer electrical interconnects
US5227013A (en) * 1991-07-25 1993-07-13 Microelectronics And Computer Technology Corporation Forming via holes in a multilevel substrate in a single step
DE19500655A1 (de) * 1995-01-12 1996-07-18 Fraunhofer Ges Forschung Chipträger-Anordnung sowie Chipträger zur Herstellung einer Chip-Gehäusung
DE19702014A1 (de) * 1996-10-14 1998-04-16 Fraunhofer Ges Forschung Chipmodul sowie Verfahren zur Herstellung eines Chipmoduls
WO1998025303A1 (fr) * 1996-12-02 1998-06-11 Minnesota Mining And Manufacturing Company Reseau a grille de boules a l'echelle de la puce, destine a un boitier de circuit integre

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0072673A2 (fr) * 1981-08-13 1983-02-23 Minnesota Mining And Manufacturing Company Film support à conducteurs pour l'interconnexion électrique entre des composants électroniques et un circuit externe
EP0452506A1 (fr) * 1989-11-06 1991-10-23 Nippon Mektron, Ltd. Procede de production d'une plaquette a circuits flexible pour le montage de circuits integres
US5091339A (en) * 1990-07-23 1992-02-25 Microelectronics And Computer Technology Corporation Trenching techniques for forming vias and channels in multilayer electrical interconnects
US5227013A (en) * 1991-07-25 1993-07-13 Microelectronics And Computer Technology Corporation Forming via holes in a multilevel substrate in a single step
DE19500655A1 (de) * 1995-01-12 1996-07-18 Fraunhofer Ges Forschung Chipträger-Anordnung sowie Chipträger zur Herstellung einer Chip-Gehäusung
DE19702014A1 (de) * 1996-10-14 1998-04-16 Fraunhofer Ges Forschung Chipmodul sowie Verfahren zur Herstellung eines Chipmoduls
WO1998025303A1 (fr) * 1996-12-02 1998-06-11 Minnesota Mining And Manufacturing Company Reseau a grille de boules a l'echelle de la puce, destine a un boitier de circuit integre

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