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WO2000002134A3 - Improved inter-device serial bus protocol - Google Patents

Improved inter-device serial bus protocol Download PDF

Info

Publication number
WO2000002134A3
WO2000002134A3 PCT/US1999/014696 US9914696W WO0002134A3 WO 2000002134 A3 WO2000002134 A3 WO 2000002134A3 US 9914696 W US9914696 W US 9914696W WO 0002134 A3 WO0002134 A3 WO 0002134A3
Authority
WO
WIPO (PCT)
Prior art keywords
serial bus
data
wire
signal level
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1999/014696
Other languages
French (fr)
Other versions
WO2000002134A2 (en
Inventor
Sanjay K Jha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR1020017000012A priority Critical patent/KR20010053365A/en
Priority to JP2000558463A priority patent/JP2003534580A/en
Priority to AU48432/99A priority patent/AU4843299A/en
Priority to EP99932038A priority patent/EP1145132A3/en
Priority to IL14056899A priority patent/IL140568A0/en
Priority to BR9911732-0A priority patent/BR9911732A/en
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Priority to CA002336385A priority patent/CA2336385A1/en
Publication of WO2000002134A2 publication Critical patent/WO2000002134A2/en
Priority to NO20006698A priority patent/NO20006698L/en
Anticipated expiration legal-status Critical
Publication of WO2000002134A3 publication Critical patent/WO2000002134A3/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)

Abstract

An inter-device serial bus protocol facilitates the interconnection and communication among various devices via a serial bus. The bus (48) comprises a clock wire, a data wire, and a start/stop wire. A master serial bus interface couples a master device to the serial bus. A slave serial bus interface couples a slave device to the serial bus. The master serial bus interface (180) may comprise a transaction initiator, a data write mechanism, a data read mechanism, and a clock driver. The transaction initiator initiates a transaction by pulling the signal level of the start/stop wire low. The data write mechanism controls the signal level on the data wire in accordance with the data to be written to the slave device. The data read mechanism reads data by monitoring the signal level on the data wire. The clock driver controls the signal level on the clock wire in accordance with a desired clock signal.
PCT/US1999/014696 1998-07-01 1999-06-30 Improved inter-device serial bus protocol Ceased WO2000002134A2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP2000558463A JP2003534580A (en) 1998-07-01 1999-06-30 Improved device-to-device serial bus protocol
AU48432/99A AU4843299A (en) 1998-07-01 1999-06-30 Improved inter-device serial bus protocol
EP99932038A EP1145132A3 (en) 1998-07-01 1999-06-30 Improved inter-device serial bus protocol
IL14056899A IL140568A0 (en) 1998-07-01 1999-06-30 Improved inter-device serial bus protocol
BR9911732-0A BR9911732A (en) 1998-07-01 1999-06-30 Enhanced protocol for serial bus between devices
KR1020017000012A KR20010053365A (en) 1998-07-01 1999-06-30 Improved inter-device serial bus protocol
CA002336385A CA2336385A1 (en) 1998-07-01 1999-06-30 Improved inter-device serial bus protocol
NO20006698A NO20006698L (en) 1998-07-01 2000-12-29 Serial data bus protocol between devices

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US9138398P 1998-07-01 1998-07-01
US60/091,383 1998-07-01
US24893999A 1999-02-11 1999-02-11
US09/248,939 1999-02-11

Publications (2)

Publication Number Publication Date
WO2000002134A2 WO2000002134A2 (en) 2000-01-13
WO2000002134A3 true WO2000002134A3 (en) 2001-09-27

Family

ID=26783906

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/014696 Ceased WO2000002134A2 (en) 1998-07-01 1999-06-30 Improved inter-device serial bus protocol

Country Status (9)

Country Link
EP (1) EP1145132A3 (en)
JP (1) JP2003534580A (en)
KR (1) KR20010053365A (en)
AU (1) AU4843299A (en)
BR (1) BR9911732A (en)
CA (1) CA2336385A1 (en)
IL (1) IL140568A0 (en)
NO (1) NO20006698L (en)
WO (1) WO2000002134A2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7076225B2 (en) * 2001-02-16 2006-07-11 Qualcomm Incorporated Variable gain selection in direct conversion receiver
FR2828947B1 (en) * 2001-08-27 2003-12-19 Pierre Trazic OUT AND IN FUNCTIONS OF CONNECTION ON A UCE BUS
JP4831899B2 (en) * 2001-08-28 2011-12-07 富士通セミコンダクター株式会社 Semiconductor integrated circuit and clock control method
CN1610896A (en) * 2001-12-28 2005-04-27 皇家飞利浦电子股份有限公司 Communication system
DE102005007333B4 (en) * 2004-05-07 2008-07-03 Avago Technologies General Ip (Singapore) Pte. Ltd. Multi-chip packages with high-speed serial communications between semiconductor dies
US7342310B2 (en) 2004-05-07 2008-03-11 Avago Technologies General Ip Pte Ltd Multi-chip package with high-speed serial communications between semiconductor die
US20060031618A1 (en) * 2004-05-20 2006-02-09 Hansquine David W Single wire and three wire bus interoperability
US20050259609A1 (en) 2004-05-20 2005-11-24 Hansquine David W Single wire bus interface
KR100698303B1 (en) * 2005-03-21 2007-03-22 엘지전자 주식회사 Serial bus direction controller
KR100910446B1 (en) 2007-12-03 2009-08-04 주식회사 동부하이텍 Data Synchronization Implementation Circuit and Method of I2C Time Controller for Display Device
EP2497028B1 (en) 2009-11-05 2014-12-03 Rambus Inc. Interface clock management
US9300129B2 (en) 2013-03-12 2016-03-29 Ascensia Diabetes Care Holding Ag Reverse battery protection for battery-powered devices
EP3103021B1 (en) * 2014-02-07 2020-12-16 Ascensia Diabetes Care Holdings AG Methods and apparatus for a multiple master bus protocol
US10417172B2 (en) 2014-04-28 2019-09-17 Qualcomm Incorporated Sensors global bus
US9734121B2 (en) 2014-04-28 2017-08-15 Qualcomm Incorporated Sensors global bus
IT201800002767A1 (en) 2018-02-16 2019-08-16 St Microelectronics Srl CIRCUIT FOR LED DRIVING, CORRESPONDING DEVICE AND PROCEDURE

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910509A (en) * 1988-03-17 1990-03-20 Zenith Electronics Corporation Bus expander for digital TV receiver
EP0589499A1 (en) * 1992-08-12 1994-03-30 Koninklijke Philips Electronics N.V. A multistation communication bus system, and a master station and a slave station for use in such system
EP0629063A1 (en) * 1993-05-21 1994-12-14 Nortel Networks Corporation Serial bus system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910509A (en) * 1988-03-17 1990-03-20 Zenith Electronics Corporation Bus expander for digital TV receiver
EP0589499A1 (en) * 1992-08-12 1994-03-30 Koninklijke Philips Electronics N.V. A multistation communication bus system, and a master station and a slave station for use in such system
EP0629063A1 (en) * 1993-05-21 1994-12-14 Nortel Networks Corporation Serial bus system

Also Published As

Publication number Publication date
EP1145132A2 (en) 2001-10-17
IL140568A0 (en) 2002-02-10
JP2003534580A (en) 2003-11-18
EP1145132A3 (en) 2002-08-21
NO20006698D0 (en) 2000-12-29
NO20006698L (en) 2001-02-20
KR20010053365A (en) 2001-06-25
BR9911732A (en) 2002-01-29
AU4843299A (en) 2000-01-24
CA2336385A1 (en) 2000-01-13
WO2000002134A2 (en) 2000-01-13

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