WO2000074222A1 - H-type bridge circuit and integrated circuit - Google Patents

Abstract

An H-type bridge circuit for the drive of a position control actuator, which is capable of controlling minute current. The H-type bridge circuit includes a load connected between the outputs of first and second output circuits that produce first voltage (POUT) and second voltage (NOUT) complementarily in response to input signals (PWM1, PWM2). The output current flowing through the load is controlled to be zero by eliminating the differences in phase and pulse-width duty between the input signals (PWM1, PWM2) to the two output circuits. With reference to this condition, a difference in pulse-width duty is created between the input signals (PWM1, PWM2) so that the load can be supplied with a positive or negative output current the magnitude of which corresponds to the difference in the pulse-width duty.

Description

 Specification

H-type bridge circuit and semiconductor integrated circuit device

 The present invention relates to an H-type bridge circuit controlled by PWM (Pulse Width Modulation) and a semiconductor integrated circuit device equipped with the H-type bridge circuit. The present invention relates to a technology that is effective for generating positive and negative output currents.

Fig. 15 shows a conceptual diagram of a conventional PWM-controlled H-shaped bridge circuit, and Fig. 16 shows its operation explanatory diagram.A conventional H-type bridge circuit using a PWM is: Control signal DIR that determines the direction of the current flowing to the load and control that controls the magnitude of the current with the duty ratio (Hals duty) of the Hals signal. ), At the time of DIRL (low level), the transistors Q 2 and Q 3 of the Η-type bridge circuit shown in FIG. 15 are turned off, and the transistor Q 1 is turned on. When Q 4 is turned on by the PWM signal, which is controlled by the PWM signal, the transistor Q 1 loads the current I に through the load through the transistor Q 4. When the transistor Q4 is turned off, the inductance of the load The stored energy causes the body diode of the transistor Q3, and the regenerative current to flow in the path of the transistor Q1 and the load in the on-state, so that the load has a positive-phase (hositive) output point POUT Negative phase (negative) The current Io flows in the direction of the output point NOUT, and the magnitude of the current is controlled by the Hals duty of the control signal PWM, as shown in FIG. 16 (B). When DIR goes high (H), transistor Q3 in FIG. 15 is turned on, and transistors Q1 and Q4 are turned off. Transistor Q2 is controlled by control signal PWM. Therefore, contrary to the above case, the load flows a current Io from the output point N 0 UT to the P 0 UT.

 The inventor of the present application has studied the use of the H-type bridge circuit of the PWM control as described above for position control. In this position control, the problem is that the output current becomes zero. Focus on the optical disk (recording medium) such as a CD-ROM, DVD, MO, etc., for example, the focus and track of an optical disk device (disk drive) that reproduces information or self-records. Driver's, hard disk drive (HDD) actuator-the output current is controlled around zero.When the PWM control of these drivers is performed by the conventional circuit as described above, a very small current is controlled. When trying to do so, it must be near zero and control must be performed with Hanoles duty

 However, the switching of the M◦ SFET (absolute gate field effect transistor) and the bilateral transistor is less than the delay. Therefore, the duty ratio of the Hals width is shorter than the turn-on delay of the above transistor. When the transistor is turned on, the transistor cannot be turned on, and when the transistor is turned on, it is shorter than the turn-off delay, and the time cannot be controlled. Will not be able to follow

In the case of the bi-transistor transistor, the delay time is usually about 1 microsecond. If you want to control the current to 1 / 100th of full scale (duty 100%), the PWM carrier cycle must be set to 100 microseconds: 2 milliseconds. In this case, the output transistor cannot follow the current change at a frequency of 1 kilohertz or more.The delay time of the output transistor of the M 0 SFET is about 1/10 of that of the biplane, but it is still 10 KH z becomes the limit As described above, in the conventional circuit, it is impossible to perform high-precision control with high responsiveness centering on zero output current. Therefore, the focus of the optical desk device such as CDROM, DVD, and MO as described above. It cannot be applied to position control that requires high-speed response, such as track drivers and HDD actuator drivers. For this reason, conventional position control uses exclusively a log circuit. But analog times On the road, not only is the current consumption large, but also the power and the heat generated by the large current consumption are efficiently dissipated from the viewpoint of element protection. ; Measures are indispensable

 Note that there is Japanese Patent Application Laid-Open No. 8322949 as a focus drive used in an optical word self-recording / reproducing apparatus that uses a PWM circuit as a drive circuit. At the time of microcurrent control, a drive microscale is not output every PWM frame, but an output microscale according to the input data is generated only once every few times to allow a desired microcurrent to flow to the load. Yes Therefore, it is necessary to move between tracks at high speed and run in a high speed. C It is not applicable to drivers such as DROM and truck drivers such as truck driver.

Accordingly, an object of the present invention is to provide a PWM control H-type bridge circuit which enables high response and high-precision output control. The PWM control H-type bridge circuit is provided on one semiconductor substrate. Another object of the present invention is to provide a structured semiconductor integrated circuit device. Further objects and novel features will be apparent from the description of this specification and the accompanying drawings.

 The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a second one which outputs the first voltage and the second ff in response to an input signal in an additive manner. For a so-called H-type bridge circuit in which a load is connected between the output terminals of the first and second output circuits, a PWM-controlled control signal (hereinafter also referred to as a PWM signal) input to the two output circuits ) As an in-phase signal and the output current flowing through the load means to be zero, and based on such a state, the relative Hals width duty difference of the PWMi word applied manually to the first and second output circuits. And an output current having a current value corresponding to the difference is caused to flow in the positive or negative direction to the load means.

 FIG. 1 is a basic circuit diagram showing one embodiment of an H-type bridge circuit under PWM control according to the present invention,

 FIG. 2 is a waveform diagram for explaining the operation of the P-M-controlled H-type bridge circuit of FIG. 1;

 FIG. 3 is a circuit diagram showing one embodiment of an H-type bridge circuit controlled by PWM according to the present invention;

 FIG. 4 is a circuit diagram showing another embodiment of the H-type bridge circuit under PWM control according to the present invention,

 FIG. 5 is a circuit diagram showing another embodiment of the H-type bridge circuit under PWM control according to the present invention,

FIG. 6 shows another example of the PWM controlled Η-bridge circuit according to the present invention. FIG. 2 is a circuit diagram showing one embodiment,

 FIG. 7 is a block diagram showing another embodiment of the H-type bridge circuit under PWM control according to the present invention,

 FIG. 8 is a waveform diagram for explaining the operation of the H-type bridge circuit of FIG. 7;

 FIG. 9 is a circuit diagram showing one embodiment of a booster circuit used in the H-type bridge circuit of FIG.

 FIG. 10 is a waveform diagram for explaining the operation of the booster circuit of FIG. 9;

 FIG. 11 is a waveform diagram for explaining the operation of the PWM-controlled H-type bridge circuit according to the present invention.

 FIG. 12 is a block diagram showing an embodiment of a semiconductor integrated circuit device constituting an H-bridge circuit of PWM control to which the present invention is applied. FIG. 13 is a block diagram showing the embodiment shown in FIG. FIG. 1 is an overall block diagram of a control system using a semiconductor integrated circuit device.

 FIG. 14 is a schematic configuration diagram of a CD player on which the semiconductor integrated circuit device of FIG. 12 is mounted,

 FIG. 15 is a block diagram showing an example of a conventional H-type bridge circuit controlled by PWM.

 FIG. 16 is a waveform diagram for explaining the operation of the H-type bridge circuit shown in FIG. 15 in the best mode for carrying out the invention

 BRIEF DESCRIPTION OF THE DRAWINGS The invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 shows an H-type bridge circuit under PWM control according to the present invention. A circuit diagram for explaining the basic concept is shown. A first CMOS output circuit consisting of a P-channel MOSFET Q1 and an N-channel MOSFET Q2 (between the power supply voltage VC C and the circuit ground potential GND) The first CMOS output circuit is provided with the first input signal PMW1 supplied to the gates of the P-channel MOSFET Q1 and the N-channel MOSFET Q2. The first CM0S output circuit generates a high-level output signal such as the power supply voltage VCC and a low-level output signal such as the circuit ground potential GND from the output terminal P0UT in response to the input signal PWM1. Similarly, between the power supply voltage V and the circuit ground potential GND, a second CMOS output circuit (a second inverter circuit) comprising a P-channel type MOS FET TQ 3 and an N-channel type MOS FET Q 4 is provided. ) Is provided, and the output terminal responds to the manual signal PWM2. Form a high-level output signal such as power supply voltage VC C and a low-level output signal such as circuit ground potential GND from N OUT

 In the above circuit, the two impeller circuits should be two vertical lines, and the load should be likened to the letter H in the alphabet with a horizontal line connecting the respective midpoints (the output terminals POUT and NOUT). In the present application, such a configuration is referred to as an H-type bridge circuit.

According to the present invention, the H-type bridge circuit is controlled using a PWM input signal, and the turn-on / turn-off of the switch element of each output circuit is controlled even in a minute current region where the current Io flowing through the load is close to zero. In order to avoid the influence of the delay time, the following measures have been taken. In this invention, the two output circuits constituting the す る -type bridge circuit, in other words, the half-bridge circuit (MOS FETQ 1 and Q 2 and Q 3 and Q 4) are completely different from the conventional PWM control, that is, the input signal PWM supplied to each input terminal of the above two output circuits 1 and PWM2 are not the same PWM signal as in the past, but are two signals that change independently. The meaning of the independently changing means that two human power signals PWM 1 Or, in one of the PWM 2, it means that the pulse width duty may be fixed. That is, the current I o corresponding to the difference between the relative Hals width duty of the two human power signals PWM1 and PWM2. There is a major feature of the PWM control according to the present invention in that

 FIG. 2 shows a timing diagram of one embodiment for explaining the PWM control according to the present invention. In this embodiment, the H-type pre-circuit shown in FIG. Fig. 2 (A) shows the case where the current I o flowing through the load is zero (I o 0), and Fig. 2 (B) shows the case where the current I 流 れ る flowing through the load is positive (I υ · 0) In Fig. 2 (C), the current Iυ flowing through the load is shown as a negative field (I o-.0) force <respectively. The positive or negative direction of the current depends on the output terminal. In correspondence with the symbols POUT (positive output) and N 0 UT (negative output), the direction from output terminal P 0 UT to N OUT is assumed to be positive, and the opposite is assumed to be negative. In the rotation control of the motor, the positive direction corresponds to the forward rotation and the negative direction corresponds to the reverse rotation.

As shown in Fig. 2 (A), the input signals PWM 1 and PWM 2 supplied to the two half-bridge circuits have a Hanoleth width duty of 50 (¾ and in-phase, and the output terminal POUT Since N OUT also changes in phase and both are always at the same potential in time, no current Io flows through the load.At this time, the switch MOSFETs Q 1 and Q 2 and Q 3 and Q 4 corresponds to the signal change of the input signals PWM 1 and 2 and the output terminal including these delay times, even if there is a turn-on / turn-off delay time. POUT and NO UT Since the voltage force << changes and both ends of the load are set to the same potential as described above, it is possible to easily and accurately create a state where the current I0 flowing through the load is zero.

 As shown in Fig. 2 (B), when a small current flows from the output P OUT to the output NO OUT, the Hals width duty of the output P 0 UT should be slightly larger than 50%, and the output NO UT This can be achieved by making the Hals width duty slightly smaller than 50% .In other words, if the Hals width duty of the output P OUT is slightly larger than 50%, the average of the output P〇 UT is correspondingly increased. If the output voltage rises slightly above the midpoint voltage (VCCZ 2) and the Hals width duty of the self-output NOUT is slightly smaller than 50 5, the average output NOUT Ε drops slightly from the midpoint voltage (VCC / 2), and a minute current (Iυ0) corresponding to the minute voltage difference flows.

As shown in Fig. 2 (C), when a small current flows from the output N OUT in the direction of the output P OUT, contrary to the above (Β), the Hals width duty of the output P OUT is slightly reduced. 5 0 ⁰⁾ than smaller, thereby to be achieved by larger than Hals width du tee just! This 5 0 ° b of output NOUT, in the direction opposite to the above case (B), the two output NOUT A small current (I o 0) corresponding to the average small voltage difference between POUT and POUT

Since the delay time of the output transient is already included in the Halse width duty of the PWM signal corresponding to zero load current as described above, the pulse width duty is controlled based on 50%. That is, the switching delay due to the PWMi signal is so strong that it appears near full scale where one duty is 100% and the other is 0%, and at full scale output maximum condition. However, since the output current itself is large, No problem.

In FIG. 1, for example, the Hals width duty of the input signal PWM2 is fixed at 50%, and the Hals width duty of the input signal PWM1 is 50% to 100% centering on 50 ° 6. In this case, the load may be varied up to 50% to 0%. In this case, the load is applied at the maximum: VC CZ 2 Since the voltage is not applied, the load drive current I υ is as described above. In the case where the range of the drive current of the load is small L, when the Hals width duty of the input signal PWM 2 is fixed to 50 ⁽ ¾), the circuit can be simplified and the power consumption can be reduced.

 In FIG. 1, for example, the human power (the Hals width duty of the signal PWM2 is fixed at 250 ′, and the input Hals width duty of the PWM 1 is 25 ° 25 −η −1 100 % And 25% to 0 '¾. In this case, the load in the forward direction has a drive current I し た corresponding to the maximum voltage of VC C 3 4 4. In the negative direction, the drive current I ο corresponding to the voltage of VCC / 4 can also be applied. The width can be set variously according to the direction of the drive current

 FIG. 3 shows a circuit diagram of an embodiment of a Η-shaped pre-soji circuit that is PWM controlled according to the present invention. In this embodiment, a human-powered terminal of the Η-shaped bridge circuit is provided. The basic circuit diagram of the PWMi symbol generation circuit that forms the supplied PWMi symbol is shown.

The PWM signal generating circuit of this embodiment corresponds to the timing diagram shown in FIG. 2. That is, when the input signal is zero, the human-power signal PWM 1 supplied to the two half bridges (output circuits) And PWM2 power, 50% loss width duty, and change the voltage of the output terminals POUT and NOUT in the same phase to make the current flowing to the load zero as the same phase. The direction of the current flowing to the load in response to the positive or negative change of the input signal, and the current value are used to supply the power supply voltage VCC to the load at full scale (::-VCC). The Hals width duty of the input signals PWM1 and PWM2 is changed complementarily

 Inputs as above ί Words PWM 1 and PWM 2 are formed by two operational amplifiers (computing width circuits) 〇Ρ 1 and 〇Ρ 2 and two concentrators (voltage comparison circuits) VC 1 and VC 2 The signal V in and the reference voltage V ref are supplied to the obeamp OP 1 to operate as an inverting amplifier circuit to form an output voltage V 1 having a negative phase. And set the resistance values of the human resistance R 3 and the feedback resistance R 4 to be equal, and operate as an inverting amplifier circuit with a voltage gain of 1 to output the output voltage V 2 in the opposite phase to the output voltage V 1. Form

 The ohmic amplifier OP1 amplifies the input signal Vin with a voltage gain corresponding to a resistance ratio between the input resistor R1 and the feedback resistor R2, if necessary, by increasing the resistance values of the resistors R1 and R2. The circuit may be operated as a buffer circuit (Voltage-follower circuit) with the voltage gain being equal to 1. Therefore, when the output impedance of the circuit forming the human-power signal Vin is sufficiently small, the above-mentioned ohmic amplifier may be used. OP 1 can be omitted

 In Fig. 3, when driving the H-type bridge circuit, in order to prevent shoot-through current of the two half bridge circuits, that is, to ground the circuit from power supply voltage VCC through MOS FETs Q1 and Q2 and Q3 and Q4. In order to prevent the current from flowing to the potential GD, it is desirable to provide a delay circuit that switches the M0 SFET in the off state to the on state after the MOSFET in the on state turns off. (Omitted in the figure)

The output voltage V 1 of the above-mentioned operational amplifier 0 P 1 is supplied to the inverting input of the circuit VC 1. The voltage V2 is supplied to the inverting input (-) of the con- verter VC2. The PWM carrier signal (triangular wave) is applied to the in-phase input (-) of these con- verters VC1 and VC2. The DC level of the carrier ί symbol is equal to the reference voltage V ref.,

 Therefore, when the input voltage Vin is equal to the reference voltage V ref, in other words, when the input signal Vin is zero, the output voltage V 1 of the oveamplifier P 1 and the output voltage OP 2 The output voltage V2 is equal to the reference voltage Vref, and the output of the con- troller VC1 and VC2 has a duty 50 Since the H-type bridge circuit is driven by PWM2, the complementary VC1 output PWM1 appears at the positive complementary output POUT of the H-type pre- and rectifier circuits, and the complementary output NOUT output Overnight VC 2 output PWM 2 appears inverted In this way, when the input signal (manual voltage) Vin and the reference voltage Vref are equal, the positive-phase output POUT and the negative-phase output NOUT have a duty of about 50同 In-phase PWM shows waveform and current does not flow to load

In the case of V in ■ V ref, Oheanfu 0 P 1, OP 2 output voltage V 1, V is, V 1 V ref, respectively, become a relationship of V 2 V ref, Hals width duty of the positive phase output ^POUT, 50 α 6, The negative phase output N OUT has a duty cycle of 50'.Therefore, current flows from the negative phase output NOUT to the positive phase output P 0 UT to the load

Conversely, when V in V ref, the operational amplifiers 0 P 1 and 0 P 2 output voltages V 1 and V 2 are in the relationship of V 1 V ref and V 2 V ref, respectively. Hals width duty '50%, Hals width duty of negative phase output N OUT becomes 50¾.Therefore, current flows from the positive phase output P 0 UT to the negative phase output N OUT to the load. FIG. 4 is a circuit diagram of another embodiment of the PWM-controlled H-shaped bridge circuit according to the present invention. In this embodiment, the variation of the operating voltage VCC in the H-shaped bridge circuit is described. In other words, in the embodiment shown in Fig. 3, the PWM control is performed independently of the power supply voltage VCC of the H-type bridge circuit. The average output voltage of the PWM-controlled output POUT and NOT is the average output voltage if the VCC expressed by the product of the power supply voltage VCC and the Hals width duty fluctuates, and the current flowing to the load fluctuates.

 Therefore, in this embodiment, a current sense resistor R s is connected in series with the load, the voltage between both ends of R s is level-shifted by the output amplifier P 3, and the output is fed back to the output pin 0 P 1. Is sufficiently smaller than the DC resistance of the load.The current flowing through the current sense resistor R s is sufficiently smoothed by the self-inductance LL and DC resistance RL of the load. The voltage R s, I R across R s is amplified (amplification rate R 6, 'R 5) by the amplifier 0 Ρ 3 and at the same time, the reference voltage V ref is the reference U o 0 and the output OP 3 output The voltage of the output OP 3 is level-shifted to the voltage V ref), and the output of the OP 3 is fed back to the inverting input of the OP 1 via the feedback resistor R 2. The following relational expression (1) between υ Stand for That

 I ο (V i η V r e f) (R 2 R 1) (R δ, R 6 R s

 (1), and the current can flow to the load regardless of the load impedance.

In the embodiment of FIG. 3 described above, if the amplitude of the PWM carrier signal ίVC is proportional to the power supply voltage VCC, the power supply voltage VCC fluctuates. Also, the current I o flowing through the load can be kept constant. For example, in the case of V 1 V 2 VC, the pulse width duty of the positive-phase output POUT is 25ό, and the Halse width duty of the negative-phase output N0UT is 15%. The difference is 50 0 (that is, the average voltage applied to the load is 0.5 V CC. If the power supply voltage VCC fluctuates by -'- 10 VC, it becomes VC-10%. HOUT width duty of POUT (25 / 1.150) 逆, Negative phase output NOUT Hals width duty (-25 / 1.150) (, the difference is 501.1% The average pressure applied to the load is the product of the above-mentioned Hals width duty difference and the power supply voltage.Therefore, even after the power supply voltage VCC changes as described above, 50 no 1.1 (%)>, 1.1: VCC 0.5 VCC Is constant

 In the embodiment of FIG. 4, current feedback is applied. Therefore, even if the amplitude of the PWM carrier signal is constant VC, the fluctuation of the power supply voltage VC C is attenuated even if not as large as the embodiment of FIG. To avoid this, it is necessary to make VC proportional to VCC as in the above.

 FIG. 5 is a circuit diagram of another embodiment of the PWM-controlled H-type bridge circuit according to the present invention. In this embodiment, the operating voltage VC of the H-type bridge circuit is shown. C-power <H-bridge circuit that level-shifts the output voltage POUT and NOUT of the H-bridge circuit that is fed back using an ohmic amplifier OP3, and returns negatively to the input amplifier P1. Assuming that the average voltages of the positive phase outputs P 0 UT and NOUT are VP and VN, the following relational expressions (.2) and (3) are established.

 -(VinR2) R1-(VP VN) R7, (R5R6)

 (2) ... G V (VP VN) ,, V in

R 2 (R 5 R 6), R 1R 7 (3) The voltage gain between human outputs is determined by the above equation (3). Capacitances C1 and C2 act as filters for removing the PWM carrier signal from the feedback loop.

 FIG. 6 shows a circuit diagram of another embodiment of the PWM-controlled H-type bridge circuit according to the present invention. Also in this embodiment, the operating voltage VCC of the H-type bridge circuit is fed back. In this embodiment, only the voltage of the positive-phase output POUT is level-shifted by the ohmic amplifier P3 and negatively fed back. The negative-phase output NOUT changes in the negative phase with respect to the positive-phase output POUT. R8 and R10 form the midpoint voltage of VCC and 2 so that the purpose of the negative feedback can be achieved only by the voltage of the positive-phase output POUT.In the case of a semiconductor integrated circuit of a PWM control system as described later, The filter for removing the PWM carrier signal from the feedback roof is only the capacitor C1, and the corresponding external terminal for connecting the capacitor C1 is only P1. External end compared to a circuit integrated into a semiconductor integrated circuit FIG. 7 shows a block diagram of another embodiment of the PWM-controlled H-type bridge circuit according to the present invention, in which one capacitor can be eliminated and one carrier can be reduced. In this embodiment, the H-type bridge circuit is constituted by an N-channel MOS FET. That is, the switch element on the power supply voltage VCC side is replaced with the P-channel M0 SFET as described above, A type MOS SFET is used. By constructing such an output circuit with a single-channel M 0 SFET, the layout on a semiconductor integrated circuit can be simplified.

 When the output transistor of the H-type bridge circuit is an N-channel MOS FET for both the upper and lower arms (switch elements) as in this embodiment, the N-channel MOS FET TQ 1 on the upper arm side is used. And Q3 drive requires booster circuits CP1 and CP2.

1 i When Q3 is turned on, the drive voltage applied to that gate is set to a boosted voltage VBST that is equal to or higher than VCC-Vth (Vth is the threshold voltage of MOS FET Q1, Q3). The booster circuits CP 1 and CP 2 are provided for this purpose, and the delay circuits DL 1 and DL 2 are provided to avoid shoot-through current due to simultaneous turning on of the MOSFETs Q 1 and Q 2 and Q 3 and Q 4 on the upper and lower arms. Is a waveform diagram for explaining the operation of the H-type bridge circuit controlled by PWM shown in FIG. 7 above. In FIG. 7, the turn-on delay T d is used to avoid simultaneous upper and lower arm turning on of the half-bridge circuit. For example, MOS FETs Q1 and Q2, where 1 is longer than the off-delay Td2, will be described as an example.Driving signal When PWM1 changes from L to high level H, such a change In contrast, in the delay circuit DL1, the voltage VGSQ1 applied between the gate and source of the MOS FETQ1 rises. The rise is set to the delay time corresponding to the turn-on delay Td1, and the fall of the voltage VGSQ2 applied between the gate and the source of the MOS FETQ2 is set to the delay time corresponding to the above-mentioned turn-off delay Td2. Is set.

 By setting the delay times Td1 and Td2 as described above, when the drive signal PWM1 changes to a low level L and then to a high level H, the MOSFET Q2 changes to the self-delay time Td2. Correspondingly, the MOSFET is turned off at an earlier timing, and thereafter, the MOSFET Q1 is turned on with a delay corresponding to the above-mentioned delay time Td1, so that the through current through the MOSFETs Q1 and Q2 is obtained. Conversely, when the drive signal PWM 1 changes from high level H to low level, the MOSFET Q 1 turns off at an earlier timing corresponding to the delay time Td 1, and then the MOSFET Q 2 Since the transistor is turned on with a delay corresponding to the delay time Td1, the through current does not occur through the MOSFETs Q1 and Q2.

 The above MO S F E T Q 1 and Q 2 provide a large output current to be supplied to the load.

1) It is formed in a large size so that it can be obtained. Therefore, the input gate capacitance is set to a relatively large capacitance value.

In order to change the gate voltage of MOSFET at high speed in accordance with the above-mentioned PWMi language, pre-drivers PD1 and PD2 composed of CMOS inverter circuits are provided, although not particularly limited. The free driver PD 1, which forms the input signal supplied to the gate of the MOS FET TQ 1 on the power supply voltage VCC, has its operating voltage set to the boosted voltage VB ST formed by the boosting circuit CP 1. The high level supplied to the gate of the MOSFETQ 1 is set to a high level corresponding to the boosted voltage VBST.

 Circuits for driving the MOSFETQ3 and Q4 of the upper and lower arms of the other half bridge circuit of the H-type bridge circuit also include the same delay circuit DL2, free drivers PD3, PD4, and booster circuit CP as described above. 2 power << established

 FIG. 9 is a circuit diagram of one embodiment of a booster circuit used in the PWM-controlled H-shaped bridge circuit of FIG. 7 in this embodiment.In this embodiment, a boosted voltage is formed by a charge-hoff circuit. In the charge-hung circuit, the capacitor C3 is precharged with the power supply voltage VCC, and the boosted voltage is formed by adding the power supply voltage VSS of the opening and closing circuit to the charged voltage.

 In this embodiment, a P-channel type M〇SF ETQ 13 which uses the power supply voltage VCC for the above-mentioned cache C 3 is used as a gate of the MOS FE TQ 13. A resistor R 10 is provided between the gate of the MOS FET Q 13, which is turned on by the low-level output signal formed in 12, and the boosted node of the capacitor C 3. When the MO SF ETQ 12 is turned off and the boosted node of the capacitor C3 rises above VCC, the gate voltage is raised through the resistor R10 to correspond to the boosted voltage and the MOSFET Q13

IG Turn off,

 Such a switch control method of the precharge MO SFE TQ 13 is also used for the switch control of the output switch MOSFET Q 14 for transmitting the boosted voltage to the output capacitor C 4. The gate of TQ15 is set to the low level, the switch MOSFETQ15 is turned on, and the boosted voltage V12 (VCC: VSS) is transmitted to the output capacitor C4. The MOSFE TQ14 is turned off. When the boosted node of the capacitor C3 drops to VCC due to the brittle operation, the gate voltage of the MOS FETQ14 increases through the resistor R11 in response to the boosted voltage VBST. 0 Turn off SFETQ 1 5

 FIG. 10 shows a waveform diagram for explaining the operation of the booster circuit of FIG. 9 above. Clock No. Signal When the CLK is at a low level, an inverter circuit IV 1 which operates as a driver The output voltage V 10 is set to the high level (VSS). Therefore, the MOSFETQ 11 is turned on, the output voltage V 11 is set to the low level (GND), and the Μ0 SFETQ 12 is turned on. As a result, the gate voltage V 13 of the MOSFETQ 13 is pulled to a low level.This causes the MOS FETQ 13 to be turned on, and the boosted node V 12 of the capacitor C 3 is connected to the power supply voltage VCC. Due to the low level of the above-mentioned cut-off signal CL MO, the MOS SFE TQ 14 is turned off and the Μ0 gate voltage V 14 of the SFETQ 15 is boosted by the resistor R 1. Conveyed through 1 and turned off

Next, when the clock signal CLK becomes high level, the output voltage V 10 of the input circuit IV 1 which operates as a driver is set to low level (GND). Therefore, the MOSFETQ 10 is turned on, Output ¾iiV 11 is set to high level (VCC) and MOS FETQ 12 is turned off. In response to the ON state of the MOSFET Q10, the voltage V12 on the boost side of the capacitor C3 is set to a boosted voltage such as VCCVSS. At this time, the low level of the output voltage V1 2 is turned off, and the gate voltage of MOSFET Q13 also rises in response to the voltage rise of V12 in response to the above-described boosting operation, and the MOSFET Q13 is turned off. The boosted voltage VCCVSS formed by the bootstrap action of the power supply voltage does not leak to the power supply voltage VCC side. Since the gate voltage V14 of the MOSFET Q15 is set to low level (GND), the MOSFET Q14 is turned on, and the boosted voltage VCC-VSS is converted to the output capacitance C4. Tell

 In this embodiment, the constant current sources I 1 and I 2 are provided on the source side of the MOSFETs Q 12 and Q 14. Therefore, when the MOSFETs Q 12 and Q 14 are turned on, the P-channel type Set the gate voltage and source voltage of MOS FETs Q13 and Q15 to R10x11 and R11x12, and set the gate-source voltage to the minimum required voltage difference. It is used to make the switching to the off-state by the resistors R10 and R11 faster.The above operation is repeated according to the change of the clock signal CLK. As a result, the boosted voltage VBST is set to a boosted voltage such as VCCVSS.In the embodiment of FIG. 7, the boosting circuits CP 1 and CP 2 are provided in each half-bridge circuit. To form the operating voltage supplied to both drivers PD 1 and PD 3

FIG. 11 shows a waveform diagram for explaining the operation of the H-type bridge circuit controlled by PWM according to the present invention. In the circuit of the embodiment as shown in FIG. When a sine wave is applied to in At the output voltage VI of the output PI (ie, the inverted input (-) of VC1), the phase-inverted waveform is applied to the output voltage V2 of the operational amplifier OP2 (that is, the inverted input (-) of the VC2). Since the same PWM carrier is applied to the in-phase inputs () of the converters VC 1 and VC 2, an independent PWM waveform, that is, the input is the same for the converters VC 1 and VC 2 The control signals P WM1 and P MW 2 are complementarily changed in response to the signal Vin, and the control signals P WM1 and P MW 2 are inverted by the output circuit to output the positive-phase output PUUT and the negative-phase output NOUT The following four modes exist in the correlation between the positive-phase output POUT and the negative-phase output NOUT

 (1) Positive phase output POUT force; 'High level and negative phase output When NOUT is at the mouth level,

 () Positive phase output POUT force

 (3) Positive phase output POUT is low level and negative phase output NOUT

 (4) When positive-phase output POUT is low and negative-phase output NOUT is

 In the above period (1), a current flows through the current path in which the MOSFETs Q1 and Q4 are turned on, and in the period (2), the MOSFETs Q1 and Q3 and the parasitic diode between the upper arms. In the period (3), current flows through the current path where the MOSFETs Q3 and Q2 are turned on. In the period (4), the MOSFETs Q2 and Q4 As a result, the current Io flows through the load in response to the input signal Vin as shown in the figure.

Fig. 12 shows the PWM control H-type bridge circuit to which the present invention is applied. A process diagram of one embodiment of a semiconductor integrated circuit device equipped with a semiconductor device is shown. The semiconductor integrated circuit device of this embodiment is directed to a CDR OM DVD. , Sindle SPN, Focus FC S, Track TRK, Thread SLD, Tray TRY are integrated into one chip. Of these, the target point is set to zero as in position control. The focus FC S, the track TRK, the thread S LD and the tray TRY requiring the position control or the rotation control should be the PWM controlled actuator according to the present invention as described above. The booster circuit forms the operating voltage VBST of the upper-arm driver in the half-bridge circuit composed of the N-channel MOS FETs constituting each of the above-mentioned actuator drivers.

 The clock carrier circuit generates the PWM carrier signal consisting of a triangular wave using the clock signal CLK formed by the clock generator CL KO SC. This triangular wave (PWM carrier signal) is composed of all five signals including the above-mentioned sinedle. The circuit can be simplified by sharing such a circuit shared by the PWM control circuit.

 In this embodiment, since the load is driven by PWM, the power consumption is small, and the heat generation is small with the power and the low power consumption. As a result, the main drivers necessary for driving the CDR0M and DVD can be formed by one semiconductor integrated circuit device, and the mounting restrictions can be eliminated. Further, such a device can be further miniaturized. Further, since the power consumption is low, the battery life can be prolonged when the device is mounted on a portable electronic device driven by a battery.

FIG. 13 shows a control using the semiconductor integrated circuit device shown in FIG. FIG. 2 is a block diagram showing the entire control system. The mechanism of the CD-ROMZ DVD includes the above-mentioned Shindle, Focus, Track, Thread, Tray Motor, Combo, Microprocessor MPU that controls the entire system, and Servo It is composed of a digital signal processor DSP that performs control. There is no particular limitation, but the power supply voltage VSS for the logic circuit is 5, and the power supply voltage VCC for the drive is 5 V and 1 2 L or shift of V is used

 FIG. 14 is a schematic configuration diagram of a slide feed mechanism of a CD player on which the above-described semiconductor integrated circuit device under PWM control according to the present invention is mounted.

 The slide feed mechanism shown in the figure is of a linear motor type and is suitable for a CDROM in which access performance is important. Although not particularly limited, the structure is supported by one shaft. The optical pickup is mounted on the moving body. The drive coil is mounted on the moving body, and the two magnets are mounted on the side yoke. The polarities of the two magnets are the same. The magnetic flux exits the magnet and forms the roof of the center yoke side yoke, and a gear is formed between the magnet and the center yoke.

 The drive coil is located at the position of the gear, and the current sensor generates a force according to Fleming's law when a current is applied to make the moving body move holly. A speed sensor is located on the opposite side of the drive coil. The linear motor is provided to monitor the moving speed of the linear motor. The linear motor is driven to set a certain speed profile to a target track, and a feedback or moving mechanism for moving the motor is operated as it is. The above speed sensor is used to rake

The outline of the access method is as follows. The number of tracks is calculated from the time of de-Q, the number of tracks to be jumped is calculated by comparing the number of tracks to be jumped, and the number of tracks to be jumped is calculated by comparing the numbers of tracks. Off, the focus servo is on, the optical system is moved quickly by the linear motor,

 On the other hand, by extracting the envelope from the RF signal and counting it, the number of tracks moved is counted, and this is sequentially compared with the number of tracks to be jumped. At this time, each servo is turned on to apply a brake to the optical system. Here, the subcode data Q is read, and the difference from the target track is calculated. (Within 0 tracks), and if out of the range, return to the first sequence again and move the entire optical system with the linear motor. The lens mechanism is a two-axis device with two degrees of freedom in the focus direction and the tracking direction. Upper word yourself track set Bok is performed by controlling the tools de S L D

 The operational effects obtained from the above embodiment are as follows.

 (1) For a so-called H-type bridge circuit in which a load is connected between the output terminals of the first and second output circuits that output the first voltage and the second voltage complementarily in response to an input signal Then, the output current flowing through the load means is set to zero as a PWM signal input to the two output circuits as an in-phase signal, and based on such a state, the output current is input to the first and second output circuits. By giving a relative Hals width duty difference of the PWM signal to the output means having a current value corresponding to the difference in the positive or negative direction to the load means, a zero value corresponding to the target position is obtained. High responsiveness and high-accuracy output control with a focus on the state

• L 2 In addition, the low power consumption by the PWM control makes it easier to form multiple devices on one semiconductor substrate.

 2) By using the first voltage as a positive power supply voltage and setting the first voltage to the ground potential of the circuit, the power supply voltage can be used effectively while realizing the high responsiveness and high-precision output control. Is obtained

 (3) An input signal having a constant Hals width duty is supplied to the second input terminal of the second output circuit, and the input signal is supplied to the second input terminal to the first input terminal of the first output circuit. By supplying a PWM signal in which the Hals width duty is changed in the positive or negative direction based on the Hals width duty, the PWM with a simple configuration centered on the zero state corresponding to the target position is provided. The effect that the current by the control can flow to the load is obtained.

 (4) By using the above-mentioned load means as a drive coil of a motor that performs position control, it is possible to achieve an effect that high responsiveness and high-accuracy position control can be realized centering on a zero state corresponding to a target position.

 (5) The first and second output circuits are composed of a CMOS circuit composed of a Ρchannel type MOS FET and a Νchannel type MOSF Ε る こ と, thereby simplifying a circuit for forming an input signal. The effect that can be obtained

 (6) The first and second output circuits are composed of MOchannel type MO SF 、, and the power supply voltage (the Ν0 SF ゲ ー ト入 力 The first and third switch elements are configured as described above.Ν The threshold L of the channel type MOS FET, the input of the signal amplitude raised to the value voltage or more. The effect is that the layout can be simplified.

(7) The first and second and the third and fourth switches are provided between the first and second input terminals and the {0 SF} gates constituting the respective switch elements. A delay circuit for preventing DC current from flowing through the switching element; and first to fourth pre-drivers for driving the MOSFET in response to a delay signal of the delay circuit. The third driver uses the boosted voltage, which is higher than the first voltage by the threshold voltage or more, as the operating voltage, thereby preventing the generation of DC current and increasing the power supply voltage. The effect of realizing effective PWM control can be obtained.

 (8) The first input that receives the human power signal and is current amplified (the first inverting amplifier circuit that forms the signal, the current is amplified by receiving the output signal, and the phase of the first input is reversed. A second inverting amplifier circuit for forming a second input signal is provided, the first input signal and the second input signal are received at one input terminal, and the other input terminal receives a PWM carrier signal. By providing the first and second voltage ratio circuits and making the input signals visible to the first and second output circuits, the power supply voltage can be used at full scale. Is possible

 (9) A current detecting resistor element is provided between the load means and the second output terminal of the second output circuit, and a detection voltage formed by the current detecting resistor element is received, and the first inversion is performed. By providing a feedback circuit for negative feedback to the amplifier circuit, the load current can be controlled without being affected by the load inductance.

 (10) The load is smoothed by applying a feedback circuit that forms a return signal corresponding to the voltage difference and negatively feeds back to the first inverting input circuit. The current flowing through the power supply can be controlled without being affected by the power supply voltage.

 (11) The voltage at one end of the self-load means is smoothed, and a feedback signal corresponding to a difference voltage between the first voltage and the midpoint voltage between the first voltage and the second voltage is formed to form the first inverting input. By providing a feedback circuit that negatively feeds back to the circuit,

I 4 The effect of this is that while controlling the current that is not affected by the power supply voltage, it is possible to reduce the number of capacitors provided for removing the PWM carrier signal provided on the feedback roof and the number of external terminals for connecting it to one. (12) A so-called H-type bridge circuit in which a load is connected between the output terminals of the first and second output circuits that output the first voltage and the second voltage complementarily in response to the input signal On the other hand, the output current flowing through the load means is set to zero by using the PWM signals input to the two output circuits as in-phase signals, and the first and second output circuits are manually operated based on such a state. A plurality of circuits for providing a relative Hals width duty difference of the PWM signal and flowing an output current having a current value corresponding to the difference in the positive or negative direction to the load means, and a spindle motor drive control circuit. And the above-mentioned PWM control circuit By forming the PWM carrier that supplies the PWM carrier in common to the symbol generation circuit on one semiconductor integrated circuit (semiconductor substrate), the circuit can be simplified by sharing the circuit. CDROM and DVD mounted can be downsized.

 Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. For example, MOSFETs flow current along the main surface of the semiconductor substrate, L, so-called horizontal M 0 SFETs, as well as flow current perpendicular to the main surface of the semiconductor substrate, and The switch element constituting the H-type bridge circuit, which may be a MOSFET, is not limited to the above-mentioned M 0 SFET, but can be replaced with another switch element such as a bayora type transistor.

 The circuit that forms the PWM signal supplied to the H-type bridge circuit includes a driving circuit (H-type bridge circuit) that can adopt various embodiments and a PWM circuit that includes a PWM control circuit that drives the driving circuit. The control system is the first

I 5 In addition to those formed in one semiconductor integrated circuit device as shown in Fig. 3, those in which an H-type bridge circuit and a circuit that forms a PWM signal to be manually operated are formed in various semiconductor integrated circuit devices. May be industrial availability

 The present invention is widely applied to an H-type bridge circuit using a PWM control circuit that forms positive and negative output currents centering around zero corresponding to a target position, such as positioning control, and a semiconductor integrated circuit device mounted thereon. Can be used

2 0

Claims

The scope of the claims  1. a first output circuit corresponding to an input signal supplied to the first input terminal and outputting the first voltage and the second voltage complementarily from the first output terminal;  A second output circuit that outputs the first voltage and the second voltage complementarily from the second output terminal in response to a human signal supplied to the second human terminal; and the first and second outputs. A load means provided between the first and second output terminals of the circuit,  The first and second PWM terminals are supplied to the first and second input terminals, respectively, and the output current flowing to the load means is substantially converted to the first and second PWM signals as in-phase signals. To zero,  A first output from the first output terminal to the second output terminal through the self-loading means in response to a relative difference in Hals width duty between the first and second PWMi symbols. An H-type bridge circuit for forming a current and a second output current flowing from the second output terminal to the first output terminal through the load means.  2 · In Claim 1,  The first voltage is a positive power supply voltage,  An H-type bridge circuit, wherein the second voltage is a circuit ground potential.  3. In Claim 1,  The first input terminal of the second output circuit is supplied with a human signal having a constant Hals width of D テ. A PWM signal in which the pulse width duty is changed in the positive or negative direction based on the Hals width duty supplied to the second input terminal is supplied to the first human input terminal of the first output circuit.プ -type bridge circuit characterized in that 4. In Claim 2,  The load means is a motor drive coil for performing position control.  5. In Claim 4,  Each of the first and second output circuits is  First and third switch elements provided between the first voltage and the first and second output terminals, respectively;  An H-type bridge circuit comprising second and fourth switch elements provided between the second voltage and the first and second output terminals, respectively.  6. In Claim 5,  The first and third switch elements are P-channel type MOS FETs,  The second and fourth switch elements are N-channel M〇S F E T H-bridge circuits,  7. In Claim 5,  The first to fourth switch elements are composed of N-channel type M 0 S F E T,  The gates of the N-channel M 0 SFETs corresponding to the first and third switch elements include the N-channel MOSFETs constituting the first and third switch elements with respect to the first voltage. An H-type bridge circuit to which an input signal having a signal amplitude higher than a threshold voltage is supplied.  8. In Claim 7,  The first human terminal and the M configuring the first and second switch elements The first and second switch elements are passed between the OSFET gate and And a first and second bridge for driving the MOSFETs constituting the first and second switch elements in response to the delay signal of the delay circuit. Driver '  DC current flows between the second input terminal and the gate of the M0 SFET constituting the third and fourth switch elements through the third and fourth switch elements. And a third and fourth free driver for receiving the delay signal of the delay circuit and separating the MOSFETs constituting the third and fourth switch elements. ,  The first and third free-driving circuits are characterized in that an operating voltage is a boosted voltage higher than the first voltage by the threshold voltage or more.  9. In Claim 8,  A first inverting amplifier circuit for receiving a human input signal and forming a first input signal having a current width;  Receiving the output signal of the first inverting amplifier circuit, amplifying the current, and 1 input 第 a second inverting amplifier circuit for forming a second human-power signal in phase opposite to the word signal,  A first voltage comparison circuit receiving the first human input signal at one of the human input terminals and receiving the PW {carrier} signal at the other input terminal;  The second input signal is received at one input terminal and the other input signal is received at the other input terminal. A second voltage comparison circuit for receiving the PWM carrier signal;  The output signal of the first voltage comparison circuit is a human input signal transmitted to the first input terminal of the first output circuit,  A PWM control test, wherein the output signal of the second voltage comparison circuit is used as a human-powered signal transmitted to a second input terminal of the second output circuit. 2 ί) 10. In Claim 9,  A current detecting resistance element provided between the load means and a second output terminal of the second output circuit;  An H-type pre-circuit, further comprising a feedback circuit that receives a detection voltage formed by the current detection resistance element and negatively feeds back to the first inverting amplifier circuit.  11. In claim 9,  An H-type circuit, further comprising a feedback circuit for smoothing a voltage between both ends of the load means, forming a feedback signal corresponding to the voltage difference, and performing a negative feedback to the first inverting input circuit. Bridge circuit  12. In claim 9,  Smoothing the voltage at one end of the load means, forming a feedback signal corresponding to a difference voltage between the first voltage and the midpoint voltage between the first voltage and the second voltage, and performing negative feedback to the first inverting input circuit; H-type bridge circuit characterized by further comprising a feedback circuit  13. a first output circuit corresponding to an input signal supplied to the first human input terminal and outputting the first voltage and the second voltage complementarily from the first output terminal;  A second output circuit corresponding to an input signal supplied to a second input terminal and outputting the first voltage and the second voltage complementarily from a second output terminal; and Loading means provided between the first and second output terminals of the output circuit,  The first and second PWM signals are supplied to the first and second input terminals, respectively, and the first and second PWM signals are output as a common-mode signal to the load terminal {¾. Is substantially zero, The first output terminal is connected to the second output terminal through the self-loading means in accordance with the relative difference between the duty widths of the first and second PWM signals. A plurality of sets of PWM control circuits each forming a first output current toward the first output terminal and a second output current from the second output terminal to the first output terminal through the load means;  A sindle motor drive control circuit;  For the above PWM control circuit and Shindlemo overnight drive control circuit, 14. A semiconductor integrated circuit device comprising a PWM carrier signal generating circuit for supplying a WM carrier signal and a PWM carrier signal generating circuit formed on one semiconductor substrate.  The first voltage is a positive power supply voltage,  The second voltage is the ground potential of the circuit,  Each of the first and second output circuits is  First and third N-channel type MOS FETs respectively provided between the first voltage and the first and second output terminals;  A second and fourth N-channel type MOS FETs respectively provided between the second voltage and the first and second output terminals,  Between the first human input terminal and the gates of the first and second N-channel MOSFETs, a DC current is prevented from flowing through the first and second N-channel MOSFETs. A delay circuit; first and second drivers for driving the first and second N-channel MOSFETs in response to a delay signal of the delay circuit;  A DC current is prevented from flowing between the second human terminal and the third and fourth N-channel MOSFETs through the third and fourth N-channel MOSFETs. And a third and fourth driver for receiving the delay signal of the delay circuit and driving the third and fourth N-channel MOS FETs, Using the clock signal generated by the above PWM carrier signal generation circuit The charge pump circuit further includes a booster circuit that supplies the first and third drivers with a threshold voltage 1 <, which is higher than the value voltage by the value of the first voltage, as an operating voltage. Semiconductor integration characterized by comprising Ί 2