WO2000072433A1 - Switching circuit - Google Patents

Abstract

A low-power-loss switching circuit for use as a high-power switching circuit, such as an inverter circuit (1), which converts DC power from a solar battery or fuel cell system into domestic AC power. The switching circuit comprises a series circuit (23) of a silicon transistor (21) and a non-silicon transistor (22), or a parallel circuit (26) of a silicon transistor (24) and a non-silicon transistor (25), or a series/parallel circuit (27) of the series circuit (23) and the non-silicon transistor (25). The conversion capability of the silicon transistors (21) and (24) is 0.1kVA-200kVA, and the non-silicon transistors (22) and (25) is composed of a SiC-base or GaN-base semiconductor.

Description

 Description Switching circuit Technical field

 The present invention relates to a switching circuit with low power loss. Background art

 Conventionally, switching circuits for large power control of inverters that convert DC power from solar cells or fuel cell power generation systems into AC power for home use generally use Si semiconductor devices, and transistors with the same characteristics, Combining multiple diodes to form one switching circuit. Also, as such a transistor,

Structures such as IGBT (insulated gate bipolar transistor) and MOSFET (metal oxide semiconductor field effect transistor) are used.

 Here, in order to improve the conversion efficiency of the inverter described above, it is necessary to increase the efficiency of a transistor used as a switching device for high power control of a switching circuit. In general, when increasing the efficiency of a device, it is necessary to reduce the ON resistance of the device in order to reduce the conduction loss, and to increase the switching characteristics of the device in order to reduce the switching loss. Processing dimensions are scaled down.

 However, when it is assumed that the switching device is used as a switching device for high power control, it is necessary to improve the efficiency of the device while maintaining the device withstand voltage. In this case, the device withstand voltage decreases. As a result, the current technology for improving the efficiency of Si semiconductor devices is close to its theoretical limit, and it is difficult to significantly improve efficiency.

The present invention has been made in view of the above circumstances, and has as its object to provide a switching circuit with low power loss. Disclosure of the invention The characteristic configuration of the switching circuit according to the present invention for achieving the above object is as follows.

 The first characteristic configuration is provided with a series circuit in which a Si transistor and a non-Si transistor are connected in series, and the conversion capacity of the Si transistor is 0.1 kVA to 200 kVA. The non-Si transistor is made of a SiC or GaN-based semiconductor.

 Further, a second characteristic configuration is that a parallel circuit formed by connecting the Si transistor and the non-Si transistor of the first characteristic configuration in parallel is provided. The present invention is characterized in that a series-parallel circuit in which the non-Si transistor is connected in parallel to the series circuit having the first characteristic configuration is provided.

 The fact that the non-Si transistor is made of a SiC or GaN-based semiconductor means that in the case of an FET (field effect transistor) or the like, the breakdown electric field strength is about 10 times (3 MV_cm ), The channel length can be scaled down (short channel) while maintaining the required device breakdown voltage, and the carrier concentration can be increased up to 100 times Si. This means that the resistance can be reduced by increasing the carrier concentration. As a result, a non-Si transistor having a lower ON resistance and a higher switching speed than the Si transistor can be obtained, and the conduction loss and the switching loss can be reduced at the same time. Here, the GaN-based semiconductor is GaN, AIGAN, InGAN, or INAlGAN, or a combination thereof.

Therefore, according to the first characteristic configuration, since the non-Si transistor of the series circuit can be turned off at high speed when the switching circuit is cut off, the turn-off time of the entire series circuit can be reduced, and the operating frequency can be improved. Switching loss can be reduced. In addition, both the S i transistor and the non-S i transistor can reduce the voltage applied to both ends of the transistor compared to when they are used alone and can afford a withstand voltage. The voltage increases and the conversion capacity increases. In addition, compared to the case where a switching circuit is formed by a single non-Si transistor, it is not necessary to use an expensive non-Si transistor with a high withstand voltage and a high speed. Can be reduced. According to the second characteristic configuration, the switching current to be turned on or off by the switching circuit is shared by the S i transistor and the non-S i transistor, so that the entire circuit is formed by the expensive non-S i transistor. Even without this, it is possible to reduce the conduction loss and the switching loss. That is, since the non-Si transistors of the parallel circuit can be turned on at high speed, the turn-on time of the entire parallel circuit can be reduced, the operating frequency can be improved, and the switching loss and the conduction loss can be reduced at the same time.

 Further, according to the third special configuration, both the turn-on time and the turn-off time of the switching circuit can be shortened, and the power loss can be reduced at both the turn-on and the turn-off.

 By the way, in the above first to third characteristic configurations, the fact that the conversion capacity (rated voltage X rated current or rated voltage X average current) of the Si transistor is 0.1 kVA to 200 kVA means that: This means that the switching circuit itself is for high power control in the first place. In general, as shown in FIG. 7, a device with a large conversion capacity has a low maximum operating frequency, and a device with a small conversion capacity has a high maximum operating frequency. Therefore, irrespective of the conversion capacity of the Si transistor in the above range, according to the first to third features, the maximum operating frequency and / or the conversion capacity of the Si transistor can be effectively improved. This is equivalent to

Further, a fourth characteristic configuration is that, in addition to the first, second or third characteristic configuration, the Si transistor is an IGBT (insulated gate bipolar transistor). According to the fourth characteristic configuration, a Si transistor having a larger conversion capacity than a MOSFET and a transistor having an operation frequency higher than that of a normal bipolar transistor can be obtained, so that the performance of the entire switching circuit can be improved. . A fifth characteristic configuration is that, in addition to the first, second, or third characteristic configuration, the non-Si transistor is a field-effect transistor. According to the fifth characteristic configuration, a transistor having a high switching speed and a low ΔN resistance can be obtained. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a circuit diagram showing a basic structure of an inverter circuit, and FIG. 2 is a circuit diagram of a switching circuit according to the present invention comprising a series circuit in which a Si transistor and a non-Si transistor are connected in series. FIG. 3 is a circuit diagram showing an example.

 FIG. 4 is a circuit diagram showing an example of a switching circuit according to the present invention including a parallel circuit formed by connecting an Si transistor and a non-Si transistor in parallel. FIG. 4 is a waveform diagram showing switching characteristics at the time of turn-on of each of a non-S i transistor and a parallel circuit;

 FIG. 6 is an example of a switching circuit according to the present invention, comprising a series circuit in which a Si transistor and a non-Si transistor are connected in series and a series-parallel circuit in which the non-Si transistor is connected in parallel; FIG.

 FIG. 7 is an explanatory diagram showing the conversion capacity and operating frequency of the high power control device. BEST MODE FOR CARRYING OUT THE INVENTION

 An embodiment in which the switching circuit of the present invention is applied to, for example, an inverter circuit 1 shown in FIG. 1 will be described with reference to the drawings.

 First, the basic structure of the inverter circuit 1 is shown in FIG. The inverter circuit 1 is composed of a converter section 10, a smoothing circuit 11, and an inverter section 12, and a high-frequency three-phase AC input (for example, 10 kHz to 20 kHz) is commercially available. It is a three-phase AC output with a frequency (50 Hz or 60 Hz). The high-frequency three-phase AC input is obtained by orthogonally converting DC power from a solar cell, a fuel cell, or the like using a transistor circuit, and boosting the DC power using a high-frequency transformer.

 The inverter unit 12 is provided with switching circuit units 13 at six locations between two internal nodes N 1 and N 2 and three output nodes Q 1, Q 2 and Q 3. Each switching circuit unit 13 is composed of a switching device 14 and a return diode 15. Conventionally, the switching device 14 and the freewheeling diode 15 generally use a Si transistor and a Si diode.

[First embodiment] In the first embodiment of the switching circuit of the present invention, as shown in FIG. 2, each of the switching circuit units 13 is replaced with a Si transistor 21 and a non-S i It is composed of a series circuit 23 formed by connecting the transistor 22 in series. Further, the freewheel diode 15 is provided in parallel with each of the Si transistor 21 and the non-Si transistor 22.

 The S i transistor 21 is S i —I G B T, and its electrical characteristics are withstand voltage.

(Collector-emitter voltage) is 300 V, current capacity (collector current) is 75 A, turn-off delay time is 175 ns, and fall time is 245 ns. The non-Si transistor 22 is a GaN-FET, and its electrical characteristics are as follows: withstand voltage (drain-source voltage) of 300 V, current capacity (drain current) of 75 A, The one-off delay time is 150 ns and the fall time is 40 ns. Note that both the turn-off delay time and the fall time are for a 200 V, 20 A resistive load.

 As shown in FIG. 3, the turn-off time from when the gate voltage changes until the switching circuit turns off is the sum of the turn-off delay time and the fall time. 420 ns, 190 ns for the non-Si transistor 22 alone, and about 320 ns for the series circuit 23 as a whole.

 In this case, the gate voltages of the S i transistor 21 and the non-S i transistor 22 are controlled by independent control circuits to control the switching speed between the S i transistor 21 and the non-S i transistor 22. In addition, each gate voltage is controlled to match the on-resistance. The gate voltage shown in FIG. 3 is that of the S i transistor 21 with respect to the series circuit 23. In the present embodiment, the gate voltage of the non-S i transistor 22 is It is delayed by 25 ns from the gate voltage of the Si transistor 21.

By the way, the switching loss can be considered as power consumed by a current that temporarily passes through both switching circuit units 13 when one of the pair of switching circuit units 13 is turned off and the other is turned on. it can. Accordingly, the maximum switching loss L off in the switching circuit unit 13 that is turned off is approximately expressed by Equation 1. Loff = \ V (t / r) I (1 -t / rJd t X f = VX IX r X f / 6 (1)

Here, V, I, and f are the voltage, current, switching time (turn-off time), and switching frequency, respectively.

 According to Equation 1, in the case where the switching circuit unit 13 is configured by a single Si transistor having the same switching characteristics as the Si transistor 21, and in the case of the series circuit 23, the maximum switching loss Loff is determined by the turn-off time. Improve proportionately. In the case of this embodiment, it is improved by about 24%. When the switching frequency f is 20 kHz and the load is 200 V and 20 A resistive, the maximum switching loss Loff per unit 13 of the switching circuit is reduced by about 1.3 W.

 [Second embodiment]

 In the second embodiment of the switching circuit of the present invention, as shown in FIG. 4, each of the switching circuit units 13 is replaced with the switching device 14 instead of the switching device 14.

It comprises a parallel circuit 26 formed by connecting the Si transistor 24 and the non-Si transistor 25 in parallel. The reflux diode 15 is provided in parallel with each of the Si transistor 24 and the non-Si transistor 25.

 The Si transistor 24 is a Si—IGBT, and its electrical characteristics are a withstand voltage (collector-emitter voltage) of 600 V, a current capacity (collector current) of 50 A, and a turn-on delay time. 40 ns, and the rise time is 26.5 ns. The non-Si transistor 25 is a GaN-FET and has electrical characteristics such as a withstand voltage (drain-source voltage) of 600 V, a current capacity (drain current) of 30 A, and a turn-on delay. The time is 40 ns and the rise time is 40 ns. Note that both the turn-on delay time and the rise time are for a 200 V, 20 A resistive load.

As shown in FIG. 5, the turn-on time from the change of the gate voltage until the switching circuit is turned on is the sum of the turn-on delay time and the rise time. 5 ns, 80 ns for the non-Si transistor 25 alone, and about 200 ns for the parallel circuit 26 as a whole. In this case, the gate voltage of the Si transistor 24 of the parallel circuit 26 and the gate voltage of the non-Si transistor 25 are designed to rise simultaneously.

 By the way, the switching loss can be considered as the power consumed by the through current of the pair of switching circuit units 13 as described above. Therefore, the maximum switching loss L on in the switching circuit unit 13 on the side that is turned on is approximately represented by the above-described formula 1 as in the case of the maximum switching loss L off. In this case, the switching time is the turn-on time.

 According to Equation 1, in the case where the switching circuit unit 13 is constituted by a single Si transistor having the same switching characteristics as the Si transistor 24, and in the case of the parallel circuit 26, the maximum switching loss Lon is the turn-on time. It is improved in proportion to In the case of the present embodiment, it is improved by about 34%. When the switching frequency f is 20 kHz and the load is 200 V and 20 A resistive, the maximum switching loss L on per unit of the switching circuit unit 13 is reduced by about 1.3 W. Is done.

 [Third embodiment]

 In the third embodiment of the switching circuit of the present invention, as shown in FIG. 6, each of the switching circuit units 13 is replaced with the above-described series circuit 23 instead of the switching device 14, It comprises a series-parallel circuit 27 in which non-Si transistors 25 are connected in parallel. The reflux diode 15 is provided in parallel with each of the Si transistor 21 and the non-Si transistors 22 and 25.

In the case of the present embodiment, the turn-off time and the turn-on time of the series-parallel circuit 27 are shortened as in the case of the first embodiment and the second embodiment, respectively. The switching loss is reduced by about 2.6 W, and the inverter section 12 is provided with the six switching circuit units 13, so that the power loss of about 15 W is improved in the entire inverter circuit 1. Is done. In the case of an inverter of 4 kW, the efficiency increases by about 0.4%. In general, the efficiency of an inverter is about 93%, and further improvement is extremely difficult. Therefore, an efficiency improvement of about 0.4% is sufficiently large as an effect. The control of the gate transistors 21 and the non-Si transistors 22 and 25 at the time of turning off and turning on each gate voltage is in accordance with the first and second embodiments. . Further, according to the switching circuit of the present invention, since the switching speed is improved as described above, the switching frequency of the switching circuit can be increased in addition to the effect of reducing the switching loss. High frequency AC input frequency can be set higher. As a result, the high-frequency transformer used in the preceding stage of the inverter circuit 1 can be reduced in size and efficiency.

 [Another embodiment]

 <1) In each of the above embodiments, the Si transistors 21 and 24 may be transistors other than IGBT. Further, the non-Si transistors 22 and 25 may be transistors other than FET.

 The S i transistors 21 and 24 and the non-S i transistors 22 and

The electrical characteristics of 25 are not limited to those of the above embodiments.

 <2> In addition to the GaN transistor, each of the non-Si transistors 22 and 25 may be other GaN such as AIGaN, InGAn, or InA1GaN. It may be a system transistor or a SiC transistor.

 (3) In the above embodiments, the switching circuit of the present invention is applied to the inverter circuit 1, but may be applied to circuits other than the inverter circuit 1. Industrial applicability

 The switching circuit of the present invention can be used in, for example, a switching circuit such as an inverter that converts DC power from a solar cell or a fuel cell power generation system into AC power for home use, and improves the conversion efficiency of the inverter. be able to.

Claims

The scope of the claims 1. It has a series circuit consisting of a S i transistor and a non-S i transistor connected in series,  A switching circuit, wherein the conversion capacity of the Si transistor is 0.1 kVA to 200 kVA, and the non-Si transistor is made of a SiC or GaN-based semiconductor.  2. It has a parallel circuit consisting of S i transistors and non-S i transistors connected in parallel,  A switching circuit, wherein the conversion capacity of the Si transistor is 0.1 kVA to 200 kVA, and the non-Si transistor is made of a SiC or GaN-based semiconductor.  3. A series circuit formed by connecting the non-Si transistor in parallel to a series circuit formed by connecting the Si transistor and the non-Si transistor in series,  A switching circuit, wherein the conversion capacity of the Si transistor is 0.1 kVA to 2OOKVA, and the non-Si transistor is made of a SiC or GaN-based semiconductor.  4. The switching circuit according to claim 1, wherein the Si transistor is an insulated gate bipolar transistor.  5. The switching circuit according to claim 1, wherein the non-Si transistor is a field effect transistor.