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WO2000061372A1 - Drive circuit for a thermal ink jet printhead - Google Patents

Drive circuit for a thermal ink jet printhead Download PDF

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Publication number
WO2000061372A1
WO2000061372A1 PCT/IT2000/000122 IT0000122W WO0061372A1 WO 2000061372 A1 WO2000061372 A1 WO 2000061372A1 IT 0000122 W IT0000122 W IT 0000122W WO 0061372 A1 WO0061372 A1 WO 0061372A1
Authority
WO
WIPO (PCT)
Prior art keywords
power transistor
transistor
drive circuit
circuit
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IT2000/000122
Other languages
French (fr)
Inventor
Angelo Menegatti
Renato Conta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olivetti Tecnost SpA
Original Assignee
Olivetti Lexikon SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olivetti Lexikon SpA filed Critical Olivetti Lexikon SpA
Publication of WO2000061372A1 publication Critical patent/WO2000061372A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/015Ink jet characterised by the jet generation process
    • B41J2/04Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04541Specific driving circuit
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/015Ink jet characterised by the jet generation process
    • B41J2/04Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/0455Details of switching sections of circuit, e.g. transistors
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/015Ink jet characterised by the jet generation process
    • B41J2/04Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/0458Control methods or devices therefor, e.g. driver circuits, control circuits controlling heads based on heating elements forming bubbles
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2202/00Embodiments of or processes related to ink-jet or thermal heads
    • B41J2202/01Embodiments of or processes related to ink-jet heads
    • B41J2202/13Heads having an integrated circuit
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65Lateral DMOS [LDMOS] FETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers

Definitions

  • This invention relates to a drive circuit for a thermal ink jet printhead, comprising a thermal resistor suitable for generating a jet of ink in the presence of a predetermined current, a power transistor connected to the thermal resistor and suitable for assuming an ON state for activating the predetermined current, and a logic circuit connected to the power transistor for selectively controlling the power transistor to assume the ON state.
  • This known circuit comprises a thermal resistor for generating a bubble of steam and ejecting a droplet of ink, a power transistor having the “drain” connected to the thermal resistor and the “source” to earth, a logic drive circuit for selectively controlling the power transistor and a voltage booster circuit placed between the logic drive circuit and the power transistor for elevating the level of the voltage output by the logic drive circuit and applying this converted level as the "gate” voltage (V G ) to the "gate” of the power transistor to bring it into the ON state and accordingly activate the heating of the thermal resistor.
  • the voltage booster circuit is necessary for commanding the power transistor in a region of the characteristics RON — V G in which total resistance of the transistor in the ON state (RON or total ON Resistance) , namely the sum of the Resistance due to the physical characteristics of the transistor alone (RONC or channel ON Resistance) and of the parasitic resistance due to the interconnections (R P ) , is low, in substance in the region of 3.5 ⁇ 4.5 ⁇ .
  • the object of this invention is the production of a MOS technology integrated circuit that does not require the insertion of voltage booster circuits for driving the transistors that supply energy to the thermal resistors of the printhead.
  • This technical problem is solved by the drive circuit for a thermal ink jet printhead characterised in that the power transistor is produced using the MOS technology and is suitable for assuming the ON state with a gate voltage V G of between 4.5 and 5.5 Volt.
  • Fig. 1 represents a block diagram of a printhead
  • Fig. 2 represents a section of the power transistor of Fig.l
  • Fig.3 represents curves Ro N —> V G typical of power transistors in accordance with the known art and according to this invention.
  • a drive circuit 10 for a printhead comprises a predefined number of thermal resistors 11, corresponding to the number of nozzles in the printhead, an equivalent number of power transistors 12, an equivalent number of logic control circuits 14 and one or more shift registers 15 of width measured as a number of bits at least equal to the number of the resistors 11.
  • Each resistor 11 has its first terminal connected to a reference voltage (voltage V C c) , of between 6.5 and 12.5 Volt for example, and its second terminal connected to a corresponding transistor, in particular to the drain 12b of the transistor 12 and is suitable for generating the thermal energy necessary for the activation of a jet of ink by a corresponding nozzle associated therewith in the printhead, when the transistor 12 is active (ON) .
  • V C c reference voltage
  • Each logic circuit 14 with two inputs and one output, has the first input connected to a timing circuit (strobe) , not depicted in the figure, by means of a connection 18, the second input to an output of the register 15, and the output to the corresponding transistor 12, in particular to its controlling electrode (gate) 12a.
  • strobe timing circuit
  • Each logic circuit 14 is suitable for activating the conduction of the transistor 12 subject to the presence of a bit with value 1 output by the register 15 and for a time determined by the timing circuit by means of a strobe signal on the connection 18.
  • the register 15, of known type, is suitable for storing a temporary map of bits with value 0 or 1 representative of the nozzles to be activated through the respective resistors 11 and for simultaneously commanding the selective activation of the resistors 11, by means of the corresponding logic circuits 14 and transistors 12.
  • Each transistor 12 has the source 12c connected to ground and, as already described, the gate 12a to the output of the respective logic circuit 14, and the drain 12b to the second terminal of the respective resistor 11 and is suitable for switching from an OFF state (non-conduction) to the ON state in relation to the voltage V G applied to the gate 12a.
  • Each transistor 12, a distinguishing element of this invention, is produced according to MOS technology, as is all of the drive circuit 10.
  • the drive logic is CMOS type and the transistor 12 is LDMOS type (Lateral Double-diffusion Metal Oxide Semiconductor) and comprises, in accordance with a section thereof, a P type substrate 21 (Fig. 2) , known in itself, an N- doped region (Nwell) 22, known in itself, which extends to the entire area of the electrodes.
  • LDMOS type Layer Double-diffusion Metal Oxide Semiconductor
  • the transistor 12 comprises, in correspondence with the source 12c, a P+ doped region 23 adjacent to an N+ doped region, of known type, and, set between the Nwell region 22 and the P+ and N+ regions, 23 and 24 respectively, a P- doped region, of known type, which extends by diffusion underneath the area of the electrode of the gate 12a and determines the value of L reported in the formula (1), as will be described in detail later.
  • the transistor 12 comprises, in correspondence with the drain 12b, an N+ doped region, of known type.
  • the transistor 12 finally also comprises, in correspondence with the gate 12a, a layer of oxide 27 having a thickness T 0 ⁇ the value of which, as is known, is inversely proportional to the value of the capacitance Cox shown in the formula (1) .
  • the transistor 12 an LDMOS type transistor, the advantage is obtained of being able to control the value of L irrespective of the width of the gate electrode 12a.
  • the advantage is also obtained of limiting the threshold voltage V TH to values of between 0.6 and 1.0 V and accordingly of obtaining a further lowering of the RONC of the transistor 12. If, in fact, we refer again to the formula (1) :
  • the drive circuit 10 does not differ from that of the known drive circuits, but it is advantageous in that the power transistor 12, of the LDMOS type for example, can be driven with the same voltage as that generally used in the logic circuit 14, of the CMOS type for example, and in the shift register 15, namely 5 Volt.
  • the drive circuit 10 in accordance with this invention, presents the further advantages of not requiring a voltage booster circuit for each power transistor and of being technologically feasible without any special expedients .
  • the transistor 12 may be produced using other types of MOS technology that enable the value of L to be controlled and in particular the thickness T 0 ⁇ of the layer of oxide 27 for obtaining the desired values of the gate voltage V G and of the total RON, without departing from the spirit of the invention.
  • the transistor 12 may be of the NMOS or NDDD- NMOS (Double Diffusion Drain NMOS) type.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Particle Formation And Scattering Control In Inkjet Printers (AREA)

Abstract

This invention relates to an integrated circuit for the driving of ink jet printheads. The circuit (10) comprises a thermal resistor (11) for generating a bubble of steam and ejecting a droplet of ink, a logic drive circuit (14, 15) and a power transistor (12) connected to the thermal resistor (11) and controlled directly by the logic circuit (14, 15). The transistor (12) is made from the same technology as the logic circuit (14, 15) and is driven with a gate voltage VG of between 4.5 and 5.5 Volts. The circuit (10) does not require the insertion of voltage boost devices between the logic circuit (14, 15) and the power transistor (12) while guaranteeing a low total resistance RON of the transistor, in practice in the region of 3.5 4.5 Φ.

Description

DRIVE CIRCUIT FOR A THERMAL INK JET PRINTHEAD
Technical Field
This invention relates to a drive circuit for a thermal ink jet printhead, comprising a thermal resistor suitable for generating a jet of ink in the presence of a predetermined current, a power transistor connected to the thermal resistor and suitable for assuming an ON state for activating the predetermined current, and a logic circuit connected to the power transistor for selectively controlling the power transistor to assume the ON state. Background Art
An integrated drive circuit for a thermal ink jet printhead made from MOS (Metal Oxide Semiconductor) technology is known from the European Patent application No. 97110413.8.
This known circuit comprises a thermal resistor for generating a bubble of steam and ejecting a droplet of ink, a power transistor having the "drain" connected to the thermal resistor and the "source" to earth, a logic drive circuit for selectively controlling the power transistor and a voltage booster circuit placed between the logic drive circuit and the power transistor for elevating the level of the voltage output by the logic drive circuit and applying this converted level as the "gate" voltage (VG) to the "gate" of the power transistor to bring it into the ON state and accordingly activate the heating of the thermal resistor.
In accordance with the known art, the voltage booster circuit is necessary for commanding the power transistor in a region of the characteristics RON — VG in which total resistance of the transistor in the ON state (RON or total ON Resistance) , namely the sum of the Resistance due to the physical characteristics of the transistor alone (RONC or channel ON Resistance) and of the parasitic resistance due to the interconnections (RP) , is low, in substance in the region of 3.5÷4.5 Ω.
In fact with a low total RON. given a certain drain current of the transistor (IDS) necessary to supply energy to the thermal resistor, the average power leaked in the circuit is low (IDS 2*RON) with obvious advantages in controlling the temperature of the printhead during operation. In particular, in accordance with the following simplified formula : RON ≡ (L/W) * (1/ (μn* C0χ* (VG-VTH) ) (1) wherein W: width of the transistor; L: length of the transistor channel; μn: surface channel mobility of the electrons; C0χ: gate capacitance of the transistor which is inversely proportional to the thickness T0χ of the layer of oxide of the transistor gate; VTH: threshold voltage of the transistor and VG: signal voltage applied to the gate. If we assume: a L/W=1.5μm/4000μm; a μn ≡ 400 cm2 / (Volt* sec) ; a Tox ≡ 500 A (angstrom) ; and a VTH ≡ 1.5 V a signal VG ≡ 10 Volt is needed to obtain a R0NC ≡ 2 Ω, which corresponds to the RON of 3.5÷4.5 Ω (Fig. 3, curve a). As a result, if we want to produce the circuit for driving of the printhead with the parameters quoted above, in the known art, for each thermal resistor, a voltage booster circuit must be inserted between the logic drive circuit which, as is known, normally "works" at ≡ 5 V for design simplicity' s sake, and the power transistor which, in accordance with the formula (1) must instead "work" with a VG of ≡ 10 V in order to have a total RON between 3.5 and 4.5 Ω.
Remembering that the current trend in printheads is to have an ever greater number of high density nozzles and accordingly of corresponding thermal resistors associated with power transistors, it is obvious that the present day solutions imply a high degree of wasted circuitry on account of the need to include voltage booster circuits which generally consist of at least two transistors powered with a voltage of 10 Volt and therefore with a more complex technology than the 5 Volt logic circuitry.
In short, the need to insert voltage booster circuits in the integrated circuits that comprise printheads today augments the surface area of the integrated circuit to be built, increases the risk of defects and failures and, in the final analysis, the cost of producing the integrated circuit itself. Disclosure of the Invention The object of this invention is the production of a MOS technology integrated circuit that does not require the insertion of voltage booster circuits for driving the transistors that supply energy to the thermal resistors of the printhead. This technical problem is solved by the drive circuit for a thermal ink jet printhead characterised in that the power transistor is produced using the MOS technology and is suitable for assuming the ON state with a gate voltage VG of between 4.5 and 5.5 Volt. Brief Description of Drawings
This and other characteristics of the present invention will become clear from the description that follows of a preferred embodiment, provided by way of a non-restricting example, and with reference to the accompanying drawings, where :
Fig. 1 represents a block diagram of a printhead; Fig. 2 represents a section of the power transistor of Fig.l; and Fig.3 represents curves RoN —> VG typical of power transistors in accordance with the known art and according to this invention. Best mode for Carrying Out the Invention With reference to Fig. 1 a drive circuit 10 for a printhead, according to this invention, comprises a predefined number of thermal resistors 11, corresponding to the number of nozzles in the printhead, an equivalent number of power transistors 12, an equivalent number of logic control circuits 14 and one or more shift registers 15 of width measured as a number of bits at least equal to the number of the resistors 11.
Each resistor 11, of known type, has its first terminal connected to a reference voltage (voltage VCc) , of between 6.5 and 12.5 Volt for example, and its second terminal connected to a corresponding transistor, in particular to the drain 12b of the transistor 12 and is suitable for generating the thermal energy necessary for the activation of a jet of ink by a corresponding nozzle associated therewith in the printhead, when the transistor 12 is active (ON) .
Each logic circuit 14, with two inputs and one output, has the first input connected to a timing circuit (strobe) , not depicted in the figure, by means of a connection 18, the second input to an output of the register 15, and the output to the corresponding transistor 12, in particular to its controlling electrode (gate) 12a.
Each logic circuit 14 is suitable for activating the conduction of the transistor 12 subject to the presence of a bit with value 1 output by the register 15 and for a time determined by the timing circuit by means of a strobe signal on the connection 18.
The register 15, of known type, is suitable for storing a temporary map of bits with value 0 or 1 representative of the nozzles to be activated through the respective resistors 11 and for simultaneously commanding the selective activation of the resistors 11, by means of the corresponding logic circuits 14 and transistors 12. Each transistor 12 has the source 12c connected to ground and, as already described, the gate 12a to the output of the respective logic circuit 14, and the drain 12b to the second terminal of the respective resistor 11 and is suitable for switching from an OFF state (non-conduction) to the ON state in relation to the voltage VG applied to the gate 12a. Each transistor 12, a distinguishing element of this invention, is produced according to MOS technology, as is all of the drive circuit 10.
In accordance with a preferred embodiment, the drive logic is CMOS type and the transistor 12 is LDMOS type (Lateral Double-diffusion Metal Oxide Semiconductor) and comprises, in accordance with a section thereof, a P type substrate 21 (Fig. 2) , known in itself, an N- doped region (Nwell) 22, known in itself, which extends to the entire area of the electrodes. The transistor 12 comprises, in correspondence with the source 12c, a P+ doped region 23 adjacent to an N+ doped region, of known type, and, set between the Nwell region 22 and the P+ and N+ regions, 23 and 24 respectively, a P- doped region, of known type, which extends by diffusion underneath the area of the electrode of the gate 12a and determines the value of L reported in the formula (1), as will be described in detail later.
The transistor 12 comprises, in correspondence with the drain 12b, an N+ doped region, of known type. The transistor 12 finally also comprises, in correspondence with the gate 12a, a layer of oxide 27 having a thickness T0χ the value of which, as is known, is inversely proportional to the value of the capacitance Cox shown in the formula (1) . In accordance with this invention, in the context of driving ink jet thermal heads, it was found that by using as the transistor 12 an LDMOS type transistor, the advantage is obtained of being able to control the value of L irrespective of the width of the gate electrode 12a.
It was also found that, by reducing the thickness T0χ of the layer of oxide 27 from the thickness of -≡ 500÷600 A (angstrom) , used in the known drive circuits for printheads, to a thickness of between --- 150 and 350 A, the result is obtained of being able to command the switching of the transistor 12 from the OFF state to the ON state with a voltage VG of -≡ 5 Volt and of having at the same time a low RONC (≡ 2 Ω) and a total RO of between 3.5 and 4.5 Ω (Fig. 3, curve b) which corresponds with the object of this invention. By reducing the thickness T0χ of the layer of oxide 27 to a thickness of between -= 150 and 350 A, the advantage is also obtained of limiting the threshold voltage VTH to values of between 0.6 and 1.0 V and accordingly of obtaining a further lowering of the RONC of the transistor 12. If, in fact, we refer again to the formula (1) :
RON ≡ (L/W)* (1/ (μn* Cox* (VG-VTH) ) (1) all the other parameters being equal, with: Tox = 250 A, VTH = 0.8 Volt e VG = 5 Volt an ROC ≡ 2 Ω is obtained and therefore of the same value as obtained in the known art with T0χ = 500 A, VTH = 1.5 Volt and VG = 10 Volt.
Therefore, for a like current in the thermal resistor 11 (180÷300 mA) , we will have the same voltage drop on power transistor 12 and the same dispersion of power (IDS2*RON) • The operation of the drive circuit 10 does not differ from that of the known drive circuits, but it is advantageous in that the power transistor 12, of the LDMOS type for example, can be driven with the same voltage as that generally used in the logic circuit 14, of the CMOS type for example, and in the shift register 15, namely 5 Volt.
Furthermore the drive circuit 10, in accordance with this invention, presents the further advantages of not requiring a voltage booster circuit for each power transistor and of being technologically feasible without any special expedients .
Naturally the transistor 12 may be produced using other types of MOS technology that enable the value of L to be controlled and in particular the thickness T0χ of the layer of oxide 27 for obtaining the desired values of the gate voltage VG and of the total RON, without departing from the spirit of the invention. For example, the transistor 12 may be of the NMOS or NDDD- NMOS (Double Diffusion Drain NMOS) type.
Changes may be made to the dimensions, shapes, materials, components, circuit elements, connections and contacts, as also to the circuitry and construction details illustrated and to the method of operation without departing from the spirit of this invention..

Claims

1. Drive circuit for a thermal ink jet printhead, comprising
- a thermal resistor (11) suitable for generating a jet of ink in the presence of a predetermined current; - a power transistor (12) connected to said thermal resistor
(11) and suitable for assuming an ON state for activating said predetermined current;
- a logic circuit (14, 15) connected to said power transistor
(12) for selectively controlling said power transistor (12) to assume the ON state; characterised in that
- said power transistor (12) is produced using the MOS technology and is suitable for assuming the ON state with a gate voltage VG of between 4.5 and 5.5 Volt.
2. Drive circuit according to claim 1, characterised in that said power transistor is LDMOS (12) type.
3. Drive circuit according to claim 1, characterised in that said power transistor (12) is NMOS or NDDD-NMOS type.
4. Drive circuit according to claim 1, 2 or 3 characterised in that the gate (12a) of said power transistor (12) has a corresponding gate oxide (27) of thickness between 150 and 350 A (angstrom) .
5. Drive circuit according to claim 1, 2 or 3 characterised in that said power transistor (12) in the ON state has a total resistance RON of between 3.5 and 4.5 Ω (ohm) .
6. Drive circuit according to claim 1, 2 or 3 characterised in that said power transistor (12) in the ON state controls a current IDs of between 180 and 300 A (milliampere) .
7. Circuit according to claim 1, 2 or 3 characterised in that said power transistor (12) has a threshold voltage VTH of between 0.6 and 1.0 V (volt).
PCT/IT2000/000122 1999-04-12 2000-04-05 Drive circuit for a thermal ink jet printhead Ceased WO2000061372A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ITTO99A000280 1999-04-12
IT1999TO000280A IT1307033B1 (en) 1999-04-12 1999-04-12 DRIVING CIRCUIT FOR INK JET THERMAL PRINT HEAD.

Publications (1)

Publication Number Publication Date
WO2000061372A1 true WO2000061372A1 (en) 2000-10-19

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IT (1) IT1307033B1 (en)
WO (1) WO2000061372A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1221720A2 (en) 2000-12-28 2002-07-10 Canon Kabushiki Kaisha Semiconductor device, method for manufacturing the same, and ink jet apparatus
US7018012B2 (en) 2003-11-14 2006-03-28 Lexmark International, Inc. Microfluid ejection device having efficient logic and driver circuitry
WO2018156171A1 (en) * 2017-02-27 2018-08-30 Hewlett-Packard Development Company, L.P. Nozzle sensor evaluation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0816082A2 (en) 1996-06-26 1998-01-07 Canon Kabushiki Kaisha Recording head and recording apparatus using the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0816082A2 (en) 1996-06-26 1998-01-07 Canon Kabushiki Kaisha Recording head and recording apparatus using the same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MANZINI S ET AL: "HOT-ELECTRON INJECTION AND TRAPPING IN THE GATE OXIDE OF SUBMICRON DMOS TRANSISTORS", INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & IC'S,US,NEW YORK, NY: IEEE, 1998, pages 415 - 418, XP000801105, ISBN: 0-7803-4752-8 *
VESTLING L ET AL: "A NOVEL HIGH-FREQUENCY HIGH-VOLTAGE LDMOS TRANSISTOR USING AN EXTENDED GATE RESURF TECHNOLOGY", IEEE INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS,US,NEW YORK, NY: IEEE, vol. CONF. 9, 1997, pages 45 - 48, XP000800154, ISBN: 0-7803-3994-0 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1221720A2 (en) 2000-12-28 2002-07-10 Canon Kabushiki Kaisha Semiconductor device, method for manufacturing the same, and ink jet apparatus
EP1221720A3 (en) * 2000-12-28 2007-08-01 Canon Kabushiki Kaisha Semiconductor device, method for manufacturing the same, and ink jet apparatus
EP2302677A1 (en) * 2000-12-28 2011-03-30 Canon Kabushiki Kaisha Method for manufacturing a semiconductor device
US7018012B2 (en) 2003-11-14 2006-03-28 Lexmark International, Inc. Microfluid ejection device having efficient logic and driver circuitry
WO2018156171A1 (en) * 2017-02-27 2018-08-30 Hewlett-Packard Development Company, L.P. Nozzle sensor evaluation
US10632742B2 (en) 2017-02-27 2020-04-28 Hewlett-Packard Development Company, L.P. Nozzle sensor evaluation

Also Published As

Publication number Publication date
ITTO990280A1 (en) 2000-10-12
IT1307033B1 (en) 2001-10-23

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