WO2000049648A1 - Ceramic multilayered thin-layer capacitor - Google Patents
Ceramic multilayered thin-layer capacitor Download PDFInfo
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- WO2000049648A1 WO2000049648A1 PCT/DE1999/000441 DE9900441W WO0049648A1 WO 2000049648 A1 WO2000049648 A1 WO 2000049648A1 DE 9900441 W DE9900441 W DE 9900441W WO 0049648 A1 WO0049648 A1 WO 0049648A1
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- oxide
- thin layer
- ceramic
- ceramic thin
- multilayer capacitor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
Definitions
- the present invention relates to a ceramic multilayer capacitor with a plurality of plate capacitors and a method for producing a ceramic multilayer capacitor with a plurality of plate capacitors.
- Such multilayer ceramic capacitors have been generally known as discrete components for many years. These capacitors have a ceramic composite produced by lamination. The metallic inner electrode layers are alternately connected to head contacts in such a way that with n inner electrode layers n-1 plate capacitors are formed which are connected in parallel. In this way, extraordinarily high capacitance densities are achieved due to a large number of individual capacitors, a small electrode spacing (the so-called dielectric layer thickness, standard today: 10 ⁇ m) and dielectric ceramics with large dielectric constants, which, depending on the type of capacitor and with poor temperature characteristics 10,000 can lie.
- dielectric layer thickness standard today: 10 ⁇ m
- Such multilayer capacitors are manufactured using powdered dispersions, which are drawn out to form green foils, and by screen printing techniques for the metal electrodes.
- the manufacturing temperatures for the standard types are above 1000 ° C.
- the smallest dimensions for multilayer capacitors are approximately 0.5 x 1.0 x 0.5 mm 3 (type: 0402).
- capacitors are integrated in thick-film or thin-film technology on substrates or (exclusively) in thin-film technology on semiconductor circuits.
- the known discrete ceramic multilayer capacitors have the following disadvantages:
- the dielectric layer thickness cannot easily be reduced to less than 1 ⁇ m with the aid of powder-based ceramic techniques.
- an MMgO single crystal is used as the substrate.
- this material is not used as a substrate in semiconductor technology and is therefore unsuitable for the integration of the capacitors.
- the object of the present invention is therefore to create discrete ceramic multilayer capacitors or a method for their production, which can be produced using thin-layer methods of semiconductor technology and can be used for integrated circuits.
- inventive features according to claims 1 and 11 make it possible to create ceramic multilayer capacitors, the minimum size of which is limited only by the resolution of the technology used. Are there Arrangements possible that allow optimal integration.
- La shows a schematic representation of a first production step for a ceramic multilayer capacitor according to the invention
- Fig. Lb is a schematic representation of a second manufacturing step subsequent to Fig. La;
- FIG. 1 c shows a schematic illustration of a third production step following FIG. 1 b;
- FIG. 1d shows a schematic representation of a fourth production step following FIG. 1c;
- Fig. Le is a schematic representation of a ceramic two-layer capacitor.
- the ceramic multilayer capacitor 1 comprises a plurality, two in the present embodiment, of plate capacitors 3, 5, which are connected to different connection contacts (not shown).
- Each plate capacitor 3, 5 comprises an oxide ceramic thin layer 7.
- This thin layer is made using various technologies, such as, for. B. CSD, MOCVD, PVD, etc., deposited on a bottom electrode 9 (bottom electrode).
- the bottom electrode in turn is applied to a platinized silicon wafer 11.
- a second electrically conductive layer or later electrode 13 is formed over a predetermined area of the first oxide ceramic thin layer 7.
- a second oxide ceramic thin layer 15 is applied over the predetermined area of the second electrode 13 and over the first oxide ceramic thin layer 7.
- a continuous contact hole 17 is formed through the first and second oxide ceramic thin layers 7, 15.
- a third electrode 19 is formed in the contact hole 17 and makes contact with the bottom electrode 9.
- the contact hole 17 is formed by an etching process, whereby both wet and dry etching processes can be used.
- the thin layers 7, 15 and the electrically conductive layers 9, 13, 19 could be obtained by wet chemical deposition with photosensitive precursors and by means of photolithography. This has the advantage that a ceramic layer is only formed where the gel layer remains after development.
- the Si wafer serving as the substrate can be etched away from the rear. Discrete multilayer capacitors are then obtained, the dielectric layer thicknesses of which are far below that of conventional types.
- Each oxide ceramic thin layer 7, 15 consists of a material selected from the group consisting of titanate, zirconate, niobate and tantalate.
- the temperature response of the capacitance can be controlled by using different compositions for the dielectric thin films 7, 15 within a multilayer thin film capacitor 1.
- Each electrode and / or base electrode 9, 13, 19 consists of a material selected from the group of metals and metallic-conductive non-metals, such as. B. oxides, nitrides, silicides, carbides, etc.
- Electrodes 9, 13, 19 are preferably made using shadow masks or liftoff technology.
- the electrically conductive layers are deposited using an electrode mask B or D.
- the contact hole is etched using an etching mask A.
- FIG. 2 shows a top view of a structured multilayer thin-film capacitor.
- etching holes are etched through the ceramic layers, the ceramic layers outside the capacitor surfaces remain as dead dimensions left. This can be useful for sealing purposes.
- FIG. 3 shows a laminated ceramic multilayer capacitor of the prior art as an example.
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Abstract
Description
Keramischer Mehrlagen-DünnschichtkondensatorCeramic multilayer thin film capacitor
Die vorliegende Erfindung betrifft einen keramischen Viel- schichtkondensator mit einer Mehrzahl von Plattenkondensatoren sowie ein Verfahren zur Herstellung eines keramischen Vielschichtkondensators mit einer Mehrzahl von Plattenkondensatoren.The present invention relates to a ceramic multilayer capacitor with a plurality of plate capacitors and a method for producing a ceramic multilayer capacitor with a plurality of plate capacitors.
Solche keramischen Mehrlagen-Dünnschichtkondensatoren sind als diskrete Bauelemente seit vielen Jahren allgemein bekannt. Diese Kondensatoren weisen einen durch Laminierung erzeugten Keramik-Verbund auf. Die metallischen Innenelektrodenlagen sind abwechselnd mit Kopfkontakten verbunden, derart, daß sich bei n Innenelektrodenlagen n-1 Plattenkondensatoren bilden, die parallel geschaltet sind. Auf diesem Wege werden außerordentlich hohe Kapazitätsdichten erreicht und zwar aufgrund einer großen Anzahl von Einzelkondensatoren, eines geringen Elektrodenabstands (der sog. Dielektri- sehen Schichtdicke, Standard heute: lOμm) und dielektrischer Keramiken mit großen Dielektrizitätszahlen, die je nach Kondensatortyp und mit schlechter Temperaturcharakteristik über 10.000 liegen können.Such multilayer ceramic capacitors have been generally known as discrete components for many years. These capacitors have a ceramic composite produced by lamination. The metallic inner electrode layers are alternately connected to head contacts in such a way that with n inner electrode layers n-1 plate capacitors are formed which are connected in parallel. In this way, extraordinarily high capacitance densities are achieved due to a large number of individual capacitors, a small electrode spacing (the so-called dielectric layer thickness, standard today: 10 μm) and dielectric ceramics with large dielectric constants, which, depending on the type of capacitor and with poor temperature characteristics 10,000 can lie.
Solche Vielschichtkondensatoren werden über pulverisierte Dispersionen, die zu grünen Folien ausgezogen werden, und durch Siebdrucktechniken für die Metallelektroden gefertigt. Die Herstellungstemperaturen für die Standardtypen liegen über 1000 °C.Such multilayer capacitors are manufactured using powdered dispersions, which are drawn out to form green foils, and by screen printing techniques for the metal electrodes. The manufacturing temperatures for the standard types are above 1000 ° C.
Die kleinsten Abmessungen für Vielschichtkondensatoren liegen bei etwa 0,5 x 1,0 x 0,5 mm3 (Typ: 0402).The smallest dimensions for multilayer capacitors are approximately 0.5 x 1.0 x 0.5 mm 3 (type: 0402).
Neben Kondensatoren als diskreten Bauelementen werden Kon- densatorfunktionen in Dickschicht- oder Dünnschichttechnik auf Substraten bzw. (ausschließlich) in Dünnschichttechnik auf Halbleiterschaltungen integriert. Die bekannten diskreten keramischen Vielschichtkondensatoren haben folgende Nachteile:In addition to capacitors as discrete components, capacitor functions are integrated in thick-film or thin-film technology on substrates or (exclusively) in thin-film technology on semiconductor circuits. The known discrete ceramic multilayer capacitors have the following disadvantages:
l. Die dielektrische Schichtdicke läßt sich mit Hilfe der pulverbasierten Keramiktechniken nicht leicht unter lμm reduzieren.l. The dielectric layer thickness cannot easily be reduced to less than 1 μm with the aid of powder-based ceramic techniques.
2. Die Bauelemente lassen sich nicht mit den üblichen Tech- niken der Halbleiterfertigung auf Halbleiterchips integrieren, da die Folien. Und Siebdrucktechnik in keiner Weise kompatibel zu den Halbleitertechnologien ist.2. The components cannot be integrated with the usual techniques of semiconductor production on semiconductor chips, since the foils. And screen printing technology is in no way compatible with the semiconductor technologies.
3. Die Abmessungen lassen sich mit den heute eingesetzten Fertigungstechniken nicht wesentlich unter die o. g. kleinste Abmessung verringern.3. With the manufacturing techniques used today, the dimensions can not be significantly below the above. reduce the smallest dimension.
4. Beim Aufbau der Vielschichtkondensatoren in Dünnschichtform wird als Substrat ein MMgO-Einkristall verwendet. Die- ses Material wird in der Halbleitertechnologie jedoch nicht als Substrat verwendet und ist daher für die Integration der Kondensatoren ungeeignet.4. When building up the multilayer capacitors in thin-film form, an MMgO single crystal is used as the substrate. However, this material is not used as a substrate in semiconductor technology and is therefore unsuitable for the integration of the capacitors.
Die Aufgabe der vorliegenden Erfindung ist daher, diskrete keramische Vielschichtkondensatoren bzw. ein Verfahren zu deren Herstellung zu schaffen, welche über Dünnschichtverfahren der Halbleitertechnologie herstellbar und für integrierte Schaltkreise verwendbar sind.The object of the present invention is therefore to create discrete ceramic multilayer capacitors or a method for their production, which can be produced using thin-layer methods of semiconductor technology and can be used for integrated circuits.
Die Aufgabe wird erfindungsgemäß durch die kennzeichnenden Merkmale der Ansprüche 1 und 11 gelöst.The object is achieved by the characterizing features of claims 1 and 11.
Durch die erfindungsgemäßen Merkmale gemäß Anspruch 1 und 11 ist es möglich, keramische Vielschichtkondensatoren zu schaffen, deren minimale Größe lediglich durch die Auflösung der verwendeten Technologie begrenzt ist. Dabei sind Anordnungen möglich, die eine optimale Integration zulassen.The inventive features according to claims 1 and 11 make it possible to create ceramic multilayer capacitors, the minimum size of which is limited only by the resolution of the technology used. Are there Arrangements possible that allow optimal integration.
Weitere Vorteile der vorliegenden Erfindung ergeben sich aus den Merkmalen der Unteransprüche 2-10 und 12-23.Further advantages of the present invention result from the features of subclaims 2-10 and 12-23.
Eine Ausführungsform der vorliegenden Errfindung wird im folgenden anhand der Zeichnung näher beschrieben. Es zeigen:An embodiment of the present invention is described below with reference to the drawing. Show it:
Fig. la eine schematische Darstellung eines ersten Herstellungsschrittes für einen erfindungsgemäßen keramischen Vielschichtkondensator;La shows a schematic representation of a first production step for a ceramic multilayer capacitor according to the invention;
Fig. lb eine schematische Darstellung eines auf Fig. la nachfolgenden zweiten Herstellungsschrittes;Fig. Lb is a schematic representation of a second manufacturing step subsequent to Fig. La;
Fig. lc eine schematische Darstellung eines auf Fig. lb nachfolgenden dritten Herstellungsschrittes;FIG. 1 c shows a schematic illustration of a third production step following FIG. 1 b;
Fig. ld eine schematische Darstellung eines auf Fig. lc nachfolgenden vierten Herstellungsschritteε;FIG. 1d shows a schematic representation of a fourth production step following FIG. 1c;
Fig. le eine schematische Darstellung eines keramischen Zweischichtkondensators .Fig. Le is a schematic representation of a ceramic two-layer capacitor.
Fig. 2 Draufsicht eines erfindungsgemäßen, strukturierten keramischen Vielschichtkondensators;2 top view of a structured ceramic multilayer capacitor according to the invention;
Fig. 3 perspektivischhe Seitenansicht eines keramischen Vielschichtkondensators des Standes der Technik.3 perspective side view of a ceramic multilayer capacitor of the prior art.
In Fig. la-d ist ein Herstellungsverfahren eines erfin- dungsgemäßen keramischen Vielschichtkondensators 1 dargestellt. Der keramische Vielschichtkondensator 1 umfaßt eine Mehrzahl, zwei in der vorliegenden Ausführungsform, von Plattenkondensatoren 3, 5, die zu unterunterschiedlichen Anschlußkontakten (nicht dargestellt) verbunden sind.A manufacturing method of a ceramic multilayer capacitor 1 according to the invention is shown in FIGS. The ceramic multilayer capacitor 1 comprises a plurality, two in the present embodiment, of plate capacitors 3, 5, which are connected to different connection contacts (not shown).
Jeder Plattenkondensator 3 , 5 umfaßt eine oxidkeramische Dünnschicht 7. Diese Dünnschicht wird über verschiedene Technologien, wie z. B. CSD, MOCVD, PVD, etc., auf einer Bodenelektrode 9 (bottom electrode) abgeschieden. Die Bo- denelektrode wiederum ist auf einem platinierten Silizium- wafer 11 aufgebracht.Each plate capacitor 3, 5 comprises an oxide ceramic thin layer 7. This thin layer is made using various technologies, such as, for. B. CSD, MOCVD, PVD, etc., deposited on a bottom electrode 9 (bottom electrode). The bottom electrode in turn is applied to a platinized silicon wafer 11.
Eine zweite elektrisch leitende Schicht bzw. spätere Elektrode 13 über einem vorbestimmten Bereich der ersten oxid- keramischen Dünnschicht 7 ausgebildet. Über dem vorbestimmten Bereich der zweiten Elektrode 13 und über der ersten oxidkeramischen Dünnschicht 7 ist eine zweite oxidkeramische Dünnschicht 15 aufgebracht. Durch die erste und zweite oxidkeramischen Dünnschicht 7, 15 hindurch ist ein durchge- hendes Kontaktloch 17 ausgebildet. In dem Kontaktloch 17 ist eine dritte Elekktrode 19 ausgebildet und stellt einen Kontakt mit der Bodenelektrode 9 her.A second electrically conductive layer or later electrode 13 is formed over a predetermined area of the first oxide ceramic thin layer 7. A second oxide ceramic thin layer 15 is applied over the predetermined area of the second electrode 13 and over the first oxide ceramic thin layer 7. A continuous contact hole 17 is formed through the first and second oxide ceramic thin layers 7, 15. A third electrode 19 is formed in the contact hole 17 and makes contact with the bottom electrode 9.
Das Kontaktloch 17 wird durch ein Ätzverfahren ausgebildet, wobei sowohl nasse als auch trockene Ätzverfahren verwendet werden können. Alternativ könnten die Dünnschhichten 7, 15 und die elektrisch leitenden Schichten 9 , 13 , 19 durch naßchemische Abscheidung mit photosensitiven Precursoren und mittels Photolithographie erhalten werden. Dies hat den Vorteil, daß eine keraraischhe Schichht nur dort gebildet wird, wo die Gelschicht nach der Entwicklung übriggeblieben ist.The contact hole 17 is formed by an etching process, whereby both wet and dry etching processes can be used. Alternatively, the thin layers 7, 15 and the electrically conductive layers 9, 13, 19 could be obtained by wet chemical deposition with photosensitive precursors and by means of photolithography. This has the advantage that a ceramic layer is only formed where the gel layer remains after development.
In anderen Ausführungsformen ist es denkbar, zunächst alle oxidkeramischen und elektrisch leitenden Schichten 7, 15, 9, 13, 19 abzuscheiden und erst am Ende z. B. mittels ion milling oder focussed ion beam (FIB) Löcher an der Elektro- denposition durch alle Schichten hindurch zu ätzen. Dies hat den Vorteil, daß nicht während des Kondensatoraufbaus Ätzschäden eingebaut werden können.In other embodiments, it is conceivable to first deposit all oxide-ceramic and electrically conductive layers 7, 15, 9, 13, 19 and only at the end, for. B. using ion milling or focused ion beam (FIB) holes on the electrical to etch the position through all layers. This has the advantage that etching damage cannot be installed during the capacitor construction.
Sind hinreichend viele Einzelkondesatoren 3 , 5 aufeinander- geschichtet, um eine selbsttragende Konstruktion zu erhalten, so läßt sich der als Substrat dienende Si-Wafer von der Rückseite wegätzen. Es werden dann diskrete Vielschichtkondensatoren erhalten, deren dielektrische Schicht- dicken weit unterhalb derjenigen konventioneller Typen liegen.If a sufficient number of individual capacitors 3, 5 are stacked on top of one another in order to obtain a self-supporting construction, the Si wafer serving as the substrate can be etched away from the rear. Discrete multilayer capacitors are then obtained, the dielectric layer thicknesses of which are far below that of conventional types.
Jede oxidkeramische Dünnschicht 7, 15 besteht aus einem Material ausgewählt aus der Gruppe Titanat, Zirkonat, Niobat und Tantalat. Durch Verwendung unterschiedlicher Zusammensetzungen für die dielektrischen Dünnschichten 7, 15 innerhalb eines Mehrlagen-Dünnschichtkondensators 1 kann der Temperaturgang der Kapazität kontrolliert werden.Each oxide ceramic thin layer 7, 15 consists of a material selected from the group consisting of titanate, zirconate, niobate and tantalate. The temperature response of the capacitance can be controlled by using different compositions for the dielectric thin films 7, 15 within a multilayer thin film capacitor 1.
Jede Elektrode und/oder Bodenelektrode 9, 13, 19 besteht aus einem Material ausgewähllt aus der Gruppe Metalle und metallisch-leitende Nichtmetalle, wie z. B. Oxide, Nitride, Silicide, Carbide, etc.Each electrode and / or base electrode 9, 13, 19 consists of a material selected from the group of metals and metallic-conductive non-metals, such as. B. oxides, nitrides, silicides, carbides, etc.
Die Abscheidung der elektrischh leitenden Schichten bzw.The deposition of the electrically conductive layers or
Elektroden 9, 13, 19 erfolgt vorzugsweise mittels Schattenmasken oder Liftoff-Technik.Electrodes 9, 13, 19 are preferably made using shadow masks or liftoff technology.
Die Abscheidung der elektrisch leitenden Schichten erfolgt mittels einer Elektrodenmaske B oder D. Das Ätzen des Kontaktlocheε erfolgt mittels Ätzmaske A.The electrically conductive layers are deposited using an electrode mask B or D. The contact hole is etched using an etching mask A.
In Fig. 2 ist eine Draufsicht eines strukturierten Mehrlagen-Dünnschichtkondensators dargestellt. In der bisher be- schriebenen Ausführungsform werden lediglich Ätzlöcher durch die Keramikschichhten geätzt, die Keramikschichten außerhalb der Kondensatorflächen bleiben als tote Masssen übrig. Dies kann für Versiegelungszwecke sinnvoll sein. Alternativ kann man jedoch auchh die Keramik dtrukturieren, um die Kondensatoren auf den Chips zu separieren. Dies wird bei nahe benachbarten Kondensatoren unumgänglich sein, um ein Übersprechen der Signale zu verhindern.2 shows a top view of a structured multilayer thin-film capacitor. In the previously described embodiment, only etching holes are etched through the ceramic layers, the ceramic layers outside the capacitor surfaces remain as dead dimensions left. This can be useful for sealing purposes. Alternatively, however, one can also structure the ceramic to separate the capacitors on the chips. This will be indispensable for capacitors that are close together in order to prevent crosstalk of the signals.
In Fig. 3 ist beispielhaft ein laminierter keramischer Vielschichtkondensator des Standes der Technik dargestellt. 3 shows a laminated ceramic multilayer capacitor of the prior art as an example.
Claims
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/DE1999/000441 WO2000049648A1 (en) | 1999-02-17 | 1999-02-17 | Ceramic multilayered thin-layer capacitor |
| EP99915481A EP1161766A1 (en) | 1999-02-17 | 1999-02-17 | Ceramic multilayered thin-layer capacitor |
| JP2000600298A JP2003533007A (en) | 1999-02-17 | 1999-02-17 | Ceramic multilayer thin layer capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/DE1999/000441 WO2000049648A1 (en) | 1999-02-17 | 1999-02-17 | Ceramic multilayered thin-layer capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2000049648A1 true WO2000049648A1 (en) | 2000-08-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/DE1999/000441 Ceased WO2000049648A1 (en) | 1999-02-17 | 1999-02-17 | Ceramic multilayered thin-layer capacitor |
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| Country | Link |
|---|---|
| EP (1) | EP1161766A1 (en) |
| JP (1) | JP2003533007A (en) |
| WO (1) | WO2000049648A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7224280B2 (en) | 2002-12-31 | 2007-05-29 | Avery Dennison Corporation | RFID device and method of forming |
| US7307527B2 (en) | 2004-07-01 | 2007-12-11 | Avery Dennison Corporation | RFID device preparation system and method |
| US7842152B2 (en) | 2005-08-22 | 2010-11-30 | Avery Dennison Corporation | Method of making RFID devices |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4857642B2 (en) * | 2005-07-29 | 2012-01-18 | Ｔｄｋ株式会社 | Method for manufacturing thin-film electronic components |
| JP4957835B2 (en) * | 2010-05-31 | 2012-06-20 | Ｔｄｋ株式会社 | Thin film electronic component and method for manufacturing thin film electronic component |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5135883A (en) * | 1990-06-29 | 1992-08-04 | Samsung Electronics Co., Ltd. | Process for producing a stacked capacitor of a dram cell |
| US5206788A (en) * | 1991-12-12 | 1993-04-27 | Ramtron Corporation | Series ferroelectric capacitor structure for monolithic integrated circuits and method |
-
1999
- 1999-02-17 WO PCT/DE1999/000441 patent/WO2000049648A1/en not_active Ceased
- 1999-02-17 EP EP99915481A patent/EP1161766A1/en not_active Withdrawn
- 1999-02-17 JP JP2000600298A patent/JP2003533007A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5135883A (en) * | 1990-06-29 | 1992-08-04 | Samsung Electronics Co., Ltd. | Process for producing a stacked capacitor of a dram cell |
| US5206788A (en) * | 1991-12-12 | 1993-04-27 | Ramtron Corporation | Series ferroelectric capacitor structure for monolithic integrated circuits and method |
Non-Patent Citations (2)
| Title |
|---|
| GROSSMANN M ET AL: "A novel integrated thin film capacitor realized by a multilayer ceramic-electrode sandwich structure", ELECTROCERAMICS VI '98, MONTREUX, SWITZERLAND, 24-27 AUG. 1998, vol. 19, no. 6-7, Journal of the European Ceramic Society, 1999, Elsevier, UK, pages 1413 - 1415, XP004166104, ISSN: 0955-2219 * |
| HENNINGS D ET AL: "ADVANCED DIELECTRICS: BULK CERAMICS AND THIN FILMS**", ADVANCED MATERIALS, vol. 3, no. 7/08, 1 July 1991 (1991-07-01), pages 334 - 340, XP000329352, ISSN: 0935-9648 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7224280B2 (en) | 2002-12-31 | 2007-05-29 | Avery Dennison Corporation | RFID device and method of forming |
| US8072333B2 (en) | 2002-12-31 | 2011-12-06 | Avery Dennison Corporation | RFID device and method of forming |
| US7307527B2 (en) | 2004-07-01 | 2007-12-11 | Avery Dennison Corporation | RFID device preparation system and method |
| US7842152B2 (en) | 2005-08-22 | 2010-11-30 | Avery Dennison Corporation | Method of making RFID devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2003533007A (en) | 2003-11-05 |
| EP1161766A1 (en) | 2001-12-12 |
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