WO1999038332A9 - Method and device for converting image data blocks into image lines - Google Patents

Abstract

The invention provides a special read- and write-addressing technique which halves the size of the memory required for the conversion by eliminating the need for the memory to 'double up'. Normally this is made necessary by simultaneous write- and read accesses.

Description

description

Method and device for converting image data blocks into image lines.

The invention relates to a method and a device in which image data blocks which follow one another in time in the line direction and contain, for example, brightness and color information for pixels, are converted into image lines in such a way that between the writing of the

Image data blocks Information for pixels of an image line is output from a memory in the correct sequence in time.

Such a method or such an arrangement is known from US Pat. No. 5,563,623 in connection with a control of an actively addressable display unit.

In the upcoming object-based video standard MPEG-4, additional memories for the objects of a previous picture are required for the prediction, since the picture to be displayed arises from the composition of different picture objects and no longer represents them completely and unchanged. Two separate memories are therefore necessary, namely a so-called frame buffer for holding image data blocks and a memory for image objects, which means a higher hardware expenditure in comparison to earlier video standards.

The object on which the invention is based is now a device or an arrangement for converting

Specify image data blocks in image lines in which the total memory requirement is as small as possible.

This object is achieved with regard to the method by the features of patent claim 1 and with regard to the arrangement by the features of patent claim 2. The further claims relate to advantageous configurations of the device according to the invention.

The invention is explained in more detail below with reference to an exemplary embodiment shown in the drawings. It shows

FIG. 1 shows an illustration to explain the data structures and memory addressing,

FIG. 2 shows a flow chart to explain the method,

FIG. 3 shows a block diagram of a device for carrying out the method,

Figure 4 is a block diagram for explaining the function of an input address generator of Figures 3 and

FIG. 5 shows a block diagram for explaining the output address generator from FIG. 3.

The underlying object is achieved according to the invention in that image block data are written into a memory and image lines are read from the memory in such a way that the memory only has to be dimensioned so large that it can accommodate a line of image blocks. A so-called doubling of the memory due to the simultaneous write and read operations is not necessary.

In the first part of FIG. 1, an image B consisting of image block lines 1 ... 36 is shown, each image block line having 44 image blocks. The picture blocks of picture block row 1 are labeled 1.1, ..., 1.44, the picture blocks of picture block row 2 are labeled 2.1, ..., 2.44 and the last block of picture block row 36 is labeled 36.44. Each image block has, as indicated by way of example in image block 1.1, M = 16 words W _] _ ... W _] _g on. In the example described here, the CCIR-601 standard with 704 x 576 pixels per field (frame) and a 4: 2: 2 format for brightness and color information is assumed. In the lower part of FIG. 1 this is exemplified by a word W _n in which the image information for 16 pixels is divided into 8 columns SP1 ... SP8, with column SP1 two brightness information Y0 and Yl and two color difference values U0 and V0 and column SP8 has two brightness values Y14 and Y15 and two color difference values U7 and V7. Each line of a word in an image block thus has the data of 16 pixels, two pixels sharing a common color described by two color difference values.

In addition, triples T21, T22, T31 and T32 are indicated as examples in the upper first part of FIG. 1 in the picture block lines 2 and 3, the triplet T21 consisting of the picture blocks 2.1, 2.2 and 2.3, the triplet T22 consisting of the picture blocks 2.4, 2.5 and 2.6, the triple T31 consist of blocks 3.1, 3.2 and 3.3 and the triple T32 consist of image data blocks 3.4, 3.5 and 3.6.

In a second part of FIG. 1, a memory M is shown with memory blocks M_ ... M 8 and three memory blocks M] _, M2 and M3 up to M45, M47 and M48 to memory triple TM1 to memory block triple TM16 are summarized. A third part of FIG. 1 shows a video image V with image lines L]... 576, the image line Li having a pixel P1 at the beginning and a pixel 704 at the end of the line.

A memory block represents a memory area that can hold 16 x 16 pixels, for example. Memory blocks can advantageously correspond exactly to one image block, but in principle a different size of a memory block is also possible. A flow chart is shown in FIG. 2 to explain the exemplary method. It is clear from this that first, in a first step, all image blocks 1.1 ... 1.44 of the first block line 1 of image B are calculated and stored in the memory M. Thereupon, in a second step, the first image line L] _ is output as the first line of the memory M up to the memory block M44. As soon as the first line L] _ has been output, the first three lines of the memory blocks can already be written with the first three image blocks 2.1, 2.2 and 2.3 of the next block line 2 of the image B. These are stored nested, which means that in the first memory block triple TM1, as entered in the second part of FIG. 1, the first words W _] _ (2.1) ..., W] _ (2.3) of the first trip ice T21 and in the memory cherblocktripel TM2 the second words W (2.1) ... W (2.3) of the first trip to the sixteenth words W] _g (2.1), ..., W _] _g (2.3) of the first triplet stored in the memory block triplet TM16 become. As soon as the second line L _{2 has been} output, the respective second lines of the memory blocks can be written with the next triple T22 of the next block line 2. These are also nested in a corresponding manner. At the same time, the third image line L _{3 is} output. If all m = 16 image lines have been output or all k = m triples of the second image line have been written in, the entire memory, the memory blocks M_ ... M48, has already been filled with the data for the next m = 16 lines. However, these picture lines are now stored "block by block". The first line of the second picture block line 2 thus contains the words W] _ (2.1) ... W] _ (2.44) in the first memory block triplet TM1. Accordingly, the picture line 17 can be read out line by line The memory block triple TM2 is then read out and at the same time the triple T31 of the third block line is written into the memory block triple TM1 read out and described with the new image blocks, the process can start again and convert block lines 3 and 4 into image lines 33 to 64 etc. With z = 576 image lines, the above-mentioned sub-procedure must be carried out z / 2 * m = 18 times from the second step, whereby, of course, no further block line is saved during the last run.

FIG. 3 shows a block circuit for carrying out the method specified above, which has the memory M, an input address generator EAG, a write switch SFW, an output address generator AAG and a read switch LSW in addition to a clock supply CLK. The clock supply CLK is connected to the input address generator EAG, the switching mechanism SSW, the reading switching mechanism LSW and the output address generator AG. The input address generator is controlled by an output signal MODI of the write switch and generates a write address SADR for the memory M. In addition, the write switch SSW generates a write activation signal SEN for the memory M. The write switch reports to the read switch LSW with the aid of a signal BZS that a Block line was written and the read switch LSW reports to the write switch using a signal ZL that a picture line has been read. The output address generator is driven by an output signal MOD2 of the read switching mechanism and generates a read address LADR in the memory M. Data DI is written into the memory M and data DO is read out.

An input memory MI and / or a FIFO memory FIFO are optionally additionally provided, indicated by dashed lines. If there is an input memory MI for storing the data DI, it can advantageously also be controlled by the input address generator. In the event that a FIFO memory is available for receiving the output data DO, this can advantageously be controlled by a signal FIN generated in the read switching mechanism. FIG. 4 shows one possibility for realizing the input address generator based on four counters A, B, C and D. The write address SADR consists of a part for addressing the 48 blocks, a part for addressing the 16 lines and a part for addressing the 8 columns. The 8 columns are formed, for example, by the counter D, the rows depending on the signal MODI either only from the counter C or depending on the counters B and C. Depending on the MODI signal, block addressing is performed either by counters A and B or by counters A, B and C. Because of the triples, the counter readings of B or B and C are multiplied by the number 3 and become the counter reading of A added.

A read address LADR_MI also contains, like the write address SADR, a part for addressing the blocks, a part for addressing the rows and a part for addressing the columns. The column addresses are formed from the counter D, the row addresses from the counter C and the block addresses from the counter readings of the counters A and B, the counter reading from B being multiplied by 3 and added to the counter reading from A.

FIG. 5 shows one possibility for realizing the output address generator. In this case, the read address LADR is formed from four counters A ', B', C and D ', the most significant bits of the address for addressing the blocks also serving the next lower bits for addressing the rows and the lowest bits for addressing the columns. The column addressing is formed from the counter D 'and the row addressing either from the counter C' or from the counter B 'and the counter C, with a switchover being effected by the signal MOD2. Depending on the signal MOD2, the block addressing occurs either as a function of the two counters A 'and B' or from the counters A ', B' and C, wherein the counter reading of counter D 'is multiplied by 3 and added to the counter reading of counter A'.

Due to the CCIR-601 standard mentioned at the beginning with 704 x 576 points per frame and the selected size of m = 16 words per image block, it is advantageous to use triples of image data blocks and triples of memory blocks, however, in particular for other image formats, they are also in principle other n-tuples of image data blocks and memory blocks are conceivable in connection with this method.

Claims

claims 1. Method for converting image data blocks into image lines, a respective image data block having m words with data for m pixels each, in which, in a first step, all image data blocks (1.1 .. 1.44) of a first block line (1) of an image (B) are first stored in a memory (M) consisting of 3 m memory blocks (M] _ .. M4 ₈ ), in a second step, for all triples (T21, T22, ..) of image data blocks of a respective first further block line (2, 4, ...), one line (Z ^ tM)) of a line of the first or a second further block line (1, 3, ..) is output as an image line (L - (- * _{m + n} ) and words of a respective triple of image data blocks of the first further block line (2, 4, ...) are written block by block into every third memory block, with a first word (W ] _ (2.1), W _] _ (2.4), ...) of a first image data block of a respective triplet (T21, T22, ...) in the first memory block (M _] _), the first word (W ^ (2.2 ), Wι (2.5), ..) of the second image data block of the respective triplet in the second memory block (M ₂ ) and the first word ( ₁ (2.3) _/ W ₁ (2.6), ..) of the third image data block of the respective triplet in the third memory block (M3) is written, - in which in a third step a respective triple (TM21, TM22, ...) of memory blocks are read together line by line as the respective image line (L ₍ t + 1 _{) *} m + n 'and at the same time a respective triple (T31, T32, ...) of image data blocks of a respective second one another block line (3, 5, ..47) are written into memory blocks with image data blocks of the respective first further block line that have already been read out, until all memory blocks of the respective first further block line (2, 4, ..48) are read out and no respective second further ones Block line are more, and - in which steps two and three are repeated until all block lines (1, ..., 36) of an image are read in and output as image lines (L ^ .. L57g). 2. Device for performing the method according to claim 1, - In which there is an input address generator (EA6) with a plurality of synchronous counters (Zi) which, depending on a first changeover signal (MODI) of a write switch (SSW), forms write addresses (SADR) for the memory (M) from the counter readings , - In which there is an output address generator (AAG) with a further plurality of synchronous counters (Zo) which, depending on a second changeover signal (MOD2) of a read switching mechanism (LSW), read addresses (LADR) for the memory (M) from the counter readings educates - In which the write switch a read activation signal (SEN) forms for the memory and uses a first end signal (BZS) to inform the read circuit that a block line has been completely written into the memory, and - In which the read switching mechanism in turn uses a second end signal (ZL) to inform the write switching mechanism that an image line has been read. 3. Apparatus according to claim 2, wherein the input address generator also forms read addresses (LADR_MI) for an input memory (MI), from which the image data blocks for the memory (M) can be called up. 4. Device according to one of claims 2 or 3, wherein the read switching mechanism (LSW) additionally delivers a control signal (FIN) for a FIFO memory (FIFO), in which the image lines can be read out from the memory (M).