WO1999038212A1

WO1999038212A1 - Static random access memory cell utilizing drive transistors with low threshold voltages

Info

Publication number: WO1999038212A1
Application number: PCT/US1998/000998
Authority: WO
Inventors: Richard K. Klein; John C. Holst; Asim A. Selcuk
Original assignee: Advanced Micro Devices Inc
Current assignee: Advanced Micro Devices Inc
Priority date: 1998-01-21
Filing date: 1998-01-21
Publication date: 1999-07-29
Anticipated expiration: 2000-07-21

Abstract

An SRAM or static random access memory cell for use in a microprocessor includes drive transistors configured as natural transistors which have low threshold voltages. A control circuit modulates a substrate or well bias signal to a well which contains the transistors to increase the threshold voltage during storage. The natural drive transistors have a greater drive strength than the pass gate transistors due to the doping characteristics associated with the low threshold voltage. The pass gate transistors and pull down transistors of the memory cell are disposed in the same well.

Description

STATIC RANDOM ACCESS MEMORY CELL UTILIZING DRIVE TRANSISTORS WITH LOW THRESHOLD VOLTAGES

Cross Reference To Related Cases

The present application is related to U.S. Application Serial No. entitled, "A Static Random Access Memory Cell Utilizing A Triple Well Back Bias To Optimize Speed And Leakage Characteristics," filed by Hoist on an even date herewith (Attorney Docket No. 60048/173).

Technical Field

The present invention relates generally to semiconductor memory. More particularly, the present invention relates to a memory cell having optimal speed and leakage characteristics.

Background Art

Semiconductor memory devices, such as, random access memory (RAM) devices, typically include a number of memory cells coupled to at least one bit line. The memory cells often include at least one storage device, storage node, and pass gate transistor. Generally, in semiconductor memory cells, such as, static random access memory (SRAM) cells, two storage transistors are coupled between pass gate transistors, and a bit line is coupled to each of the pass gate transistors. Thus, each memory cell is often located between two bit lines. The pass gate transistors (e.g., transfer gates) have gate electrodes which are coupled to word lines. A signal, such as, an address or select signal is provided on the word line associated with the memory cell to select or to access a particular memory cell. Once the memory cell is selected via the word line, the memory cell can be read or written via the pass gate transistors coupled to the bit lines. The memory cell of the SRAM often contains two inverters connectedin anti-parallel.

Basically, each cell is a flip-flop which has two stable states (e.g., a logic 1 or a logic 0). The memory cell is generally made of four or six transistors. In a four transistor SRAM cell, a first resistor is coupled in series with a first pull down (e.g., storage or drive) transistor at a first storage node, and a second resistor is coupled in series with a second pull down transistor at a second storage node. A first pass gate is coupled between a first bit line and the first storage node, and a second pass gate is coupled between a second bit line and a second storage node.

In a six-transistor memory cell, the first and second resistors are replaced by first and second load transistors. The load transistors can be P-channel transistors or depletion mode N-channel transistors. The pull down transistors and pass gate transistors for both 4-transistor cells and for 6- transistor cells are usually N-channel enhancement mode transistors. Due to power, stability and speed considerations associated with modern memory devices, it is desirable to construct memory cells with pull down transistors that have a greater drive strength than the pass gate transistors, and, yet also have a relatively small width. When the threshold voltage of the pull down transistors is much lower than that of the pass gate transistors, the drive strength of the pull down transistors is substantially greater relative to the pass gate transistors. The lower the threshold voltages of the transistor also minimizes transistor width, thereby conserving memory cell area. Furthermore, transistors with lower threshold voltages tend to turn on and off more quickly.

However, if the threshold voltage is too low, the transistor can be susceptible to being improperly turned on and off. Furthermore, transistors which have small threshold voltages tend to have larger leakage current characteristics. The leakage current contributes to the amount of power which is consumed by the memory cell. As a result, this leakage current adds to the constant power drain associated with the memory cell.

Thus, there is a need for a memory cell which is optimized for high speed, small size and lower leakage current characteristics. Further, there is a need for a memory cell which utilizes pull down transistors with a substantially greater drive strength than the pass gate transistors. Further still, there is a need for a stable, yet fast, memory cell which consumes minimal power

Disclosure Of Invention

The present invention relates to a semiconductor memory device. The semiconductor memory device includes a semiconductor substrate, a memory cell, and a control circuit. The semiconductor substrate has a well that is coupled to a well contact. The memory cell includes at least one pass gate transistor formed within the well of the semiconductor substrate and at least one pull down transistor formed within the well of the semiconductor substrate. The pull down transistor is doped so as to have a threshold voltage less than a threshold voltage of the pass gate transistor. The control circuit has an output coupled to the well contact. The control circuit provides a first substrate bias signal at the output when the memory cell is being accessed and provides a second substrate bias signal at the output when the memory cell is in a storage mode. The threshold voltage of the pass gate transistor and the pull down transistor is greater when the second substrate bias signal is provided than when the first substrate bias signal is provided.

The present invention further relates to a SRAM memory. The SRAM memory includes a semiconductor substrate, a memory cell, and a substrate bias generator. The semiconductor substrate has a first well and a second well. The first well is doped with first dopants, and the second well is doped with second dopants. The first dopants have an opposite conductivity type to the second dopants. The first well is disposed in the second well and coupled to a well contact. The memory cell

-2- includes a plurality of natural MOS pull down transistors and a plurality of enhancement MOS pass gate transistors. The natural MOS pull down transistors are formed within the first well. The substrate bias generator has an output coupled to the well contact. The substrate bias generator provides a first substrate bias signal at the output when the memory cell is being accessed and provides a second substrate bias signal at the output when the memory cell is not being accessed. The threshold voltage of the natural MOS pull down transistors is greater when the second substrate bias signal is provided than when the first substrate bias signal is provided.

The present invention still further relates to a method of accessing a memory cell in a semiconductor memory. The memory cell includes at least one natural MOS transistor. The MOS transistor is formed in a semiconductor substrate. The semiconductor substrate has a first well and a second well. The first well is doped with first dopants, and the second well is doped with second dopants. The first dopants have an opposite conductivity type to the second dopants. The first well is disposed in the second well and is coupled to a well contact. The method includes addressing the memory cell, providing a first substrate signal to the well contact, performing a read operation or a write operation on the memory cell, and providing a second substrate signal to the well contact. The threshold voltage of the natural MOS transistor is greater when the second substrate signal is provide than when the first substrate signal is provided.

In one aspect of the present invention, a SRAM memory cell includes N-channel pass gate (access) transistors and N-channel pull down (drive) transistors. The N-channel pass gate transistors and the N-channel pull down transistors are disposed in a triple well structure within the semiconductor substrate. The transistors are provided in a P-well which is surrounded by a N-well that is provided in a P-substrate.

The triple wall structure advantageously provides the additional effect of preventing soft errors caused by radiation. The third well (the P-well surrounded by the N-well) provides a barrier between the substrate and the transistors associated with the memory cells. The N/P junction or boundary between the N-well and the P-substrate prevents charges developed in the P-substrate from advancing to the P-well in which the pass gate transistors and the pull down transistors are disposed.

According to another aspect of the present invention, the P-well in which the pass gate and the pull down transistors are disposed is coupled to a control circuit which modulates the voltage to the P-well. Preferably, the control circuit responds to a microprocessor signal, a read or write signal, a word line decode signal, an address signal, or other selection signal and brings the P-well to a more negative voltage when the memory cell is not being accessed. Preferably the control circuit modulates the well bias signal to the N-well from 0 to -3 volts (V). The control circuit effectively controls or reuses the leakage current associated with the transistors of the cell when the cell is not being accessed.

-3- According to yet another aspect of the present invention, the control circuit provides a ground signal to the P-well when the memory cell is being accessed and a -3V signal to the P-well when the memory cell is not being accessed. The -3V signal raises the threshold associated with the pass gate and the pull down transistors so that the pass gate and the pull down transistors have lower leakage currents despite their low threshold voltages when accessed. Thus, the control circuit effectively controls the threshold voltages associated with the pass gate and the drive transistors.

In yet another aspect of the present invention, the pull down transistors are natural transistors, and the pass gate are regular enhancement mode transistors. Whereas the natural pull down transistors have a threshold voltage of 0.3 V or less when the first substrate bias signal (0V) is provided, the regular enhancement pass gate transistors have a threshold voltage of 0.5V or more when the first substrate bias signal is provided. Both transistors have approximately the same gate width, and yet the natural pull down transistors have a greater drive strength than the enhancement pass gate transistors. The semiconductor substrate area is advantageously saved because the natural transistors occupy less space than regular transistors of the same drive strength. In still a further aspect of the present invention, an array of memory cells is provided on a single substrate with a processor unit. The array of memory cells includes pass gate and pull down transistors provided in a triple well structure. The triple well structure is provided a substrate bias signal by a control circuit that responds to an on-chip processor signal. The on-chip processor signal provides an indication that the memory cell is about to be accessed. The control circuit changes the substrate bias signal to the triple well so that the pass gate and the pull down transistors have a lower threshold voltage during the access of the memory cells.

Brief Description Of Drawings

The invention will hereafter be described with reference to the accompanying drawings wherein like numerals denote like elements and:

Figure 1 is an electrical schematic drawing of a memory system, including a memory cell in accordance with an exemplary embodiment of the present invention;

Figure 2 is a general schematic block diagram of the memory cell, including a triple wall structure in accordance with an exemplary embodiment of the present invention; and

Figure 3 is a cross-sectional view of a semiconductor substrate, including a portion of the memory cell schematically illustrated in Figure 1.

Mode for Carrying Out the Invention

With reference to Figure 1, a memory system 5 is comprised of control circuit 100 and an array (not shown) of cells, such as, a memory cell 10. Memory cell 10 is coupled between complementary bit lines 12 and 14 and is coupled to a word line 16. Memory cell 10 is preferably a static random access memory cell (SRAM), including a load transistor 18, a load transistor 20, a drive or pull down transistor 22, and a drive or pull down transistor 24. Transistors 18 and 20 are contained within an N-well 106, whereas transistors 22 and 24 are contained within a P-well 104. Transistors 18, 20, 22 and 24 are coupled together to form cross-coupled inverters having a storage node 26 and a storage node 28.

Transistors 18 and 20 are preferably P-channel transistors, but may be replaced by polysilicon or other resistors, by N-channel depletion mode transistors, or by other electrical devices for dropping the voltage at storage nodes 26 and 28 when pull down transistors 22 and 24 are turned on, respectively. Pull down transistors 22 and 24 are preferably N-channel transistors, although other types of transistors, such as, bipolar transistors or other devices may be utilized. Transistors 22 and 24 are preferably natural N-channel transistors having a gate threshold voltage of approximately 0.3 volts (V) when well 104 is normally biased. Generally, natural transistors have threshold voltages of .2 to .3 V. Regular enhancement mode transistors have threshold voltages from .5 to ,7V. Depletion mode transistors have threshold voltages below 0V.

Storage node 26 is coupled to a pass gate transistor 30 which is controlled by word line 16. Storage node 28 is coupled to a pass gate transistor 32 which is also controlled by word line 16. Pass gate transistors 30 and 32 are preferably regular N-channel enhancement mode transistors having a gate threshold voltage between 0.5 and 0.6 V when well 104 is normally biased, although other types of transistors may be utilized and lower threshold voltages can be utilized. Transistors 30 and 32 are located in P-well 104.

Transistors 18 and 22 form a first inverter having an input at a conductive line 23, and transistors 20 and 24 form a second inverter having an input at conductive line 21. Conductive line 23 is coupled to the output of the second inverter formed by transistors 20 and 24 (e.g., storage node 28). Similarly, conductive line 21 is coupled to the output of the first inverter formed by transistors 18 and 22 (e.g., storage node 26). Thus, transistors 18, 20, 22 and 24 form cross-coupled inverters having outputs at storage nodes 26 and 28.

In operation, cell 10 stores a logic signal, data, or other information, such as, a logic 1 or logic 0 in node 26 and its complement in node 28. When transistor 22 is turned on (a voltage greater than the threshold voltage is applied on line 23), transistor 18 is turned off, and node 26 is coupled to ground. When transistor 24 is turned off, transistor 20 is turned on and node 28 is coupled to VCC or power. Conversely, when transistor 22 is turned off, transistor 18 is turned on, and node 26 is coupled to VCC. When transistor 24 is turned on, transistor 20 is turned off and node 28 is coupled to ground. Generally, the logic level stored on node 26 is opposite to the logic level stored in node 28.

-5- Cell 10 is accessed for reading from and for writing to nodes 26 and 28 when a select signal, such as, a logic 1 or VCC, is provide on word line 16. The signal VCC can be 5V, 3.3V, or other power voltages. Memory cell 10 is accessed as pass gate transistors 30 and 32 couple bit lines 12 and 14 to nodes 26 and 28, respectively, in response to the select signal on word line 16. The select signal is greater than the threshold voltage of transistors 30 and 32, respectively when cell 10 is accessed.

During a read or write operation, transistors 22 and 24 should have greater drive strength than transistors 30 and 32 to appropriately provide and receive signals to and from bit lines 12 and 14. Although transistors 22 and 24 can have the same width as transistors 30 and 32, transistors 22 and 24 have a greater drive strength due to doping characteristics which give transistors 22 and 24 such a low threshold voltage. Alternatively, the width of transistors 22 and 24 can be reduced to save substrate area at the expense of drive strength.

In a read operation, cell 10 is accessed by providing the select signal on line 16. During the read operation, the signal at storage node 26 is provided to bit line 12, while the signal at storage node 28 is provided to bit line 14. The signals on lines 12 and 14 have been read by a sense amplifier (not shown). The signals on lines 12 and 14 are complementary.

In a write operation, cell 10 is accessed by providing a select signal on line 16. During the write operation, the signal on bit line 12 is driven to node 26, while the signal on bit line 14 is driven to node 28. After the select signal on line 16 is removed, cell 10 stores the signals driven on lines 12 and 14 on nodes 26 and 28, respectively.

Alternatively, cell 10 can be a different type of memory cell, such as, a shift register DRAM cell or other device. The principles of the present invention can be applied to all types of memory cells which utilize transistors.

With reference to Figure 2, control circuit 100 of memory system 5 is coupled to a terminal 101, a terminal 102, and a terminal 103. A substrate 70 preferably contains control circuit 100 as well as the array of memory cells (not shown), including cell 10 (Figure 1). Substrate 70 includes a triple well structure comprised of well 104 and well 106. A terminal 101 is preferably a contact or an electrode coupled to well 104. Well 104 is a P-well that preferably contains N-channel transistors 22, 24, 30, and 32 (Figure 1). A terminal 102 is preferably a contact or an electrode coupled to well 106. Well 106 is a N-well which surrounds well 104 and contains transistors 18 and 20. Terminal 103 is preferably a contact or an electrode coupled to substrate 70.

Well 104 is surrounded by well 106 to prevent soft errors due to radiation by providing a protective barrier between substrate 70 and transistors 22, 24, 30 and 32. Well 104 is a

P-type well and well 106 is an N-type well. Well 104 has a doping concentration of 10¹⁶ to 10¹⁸ (e.g., 10¹⁷) of P-type dopants per centimeter cubed. Well 106 has a depth of .1 to 2 microns or more and a doping concentration of 10¹⁶ to 10¹⁸ (e.g., 10") of N-type dopants per centimeter cubed.

-6- Additionally, the threshold voltages associated with transistors 22, 24, 30 and 32 can be controlled by providing a substrate bias or well bias signal from control circuit 100 to terminal 101 which is coupled to well 104. For example, by providing a well bias signal at a first voltage, such as, ground, the threshold voltage of natural transistors 22 and 24 is approximately 0.2V, whereas the threshold voltage of regular enhancement transistors 30 and 32 is approximately 0.5 to 0.6v. When control circuit 100 provides a voltage of approximately -3V, the threshold voltage of natural transistors 22 and 24 is preferably raised to approximately 0.5 to 0.6V. The threshold voltage of regular enhancement transistors 30 and 32 is also raised. Substrate 70 is preferably biased at 0V. Well 106 is also preferably biased at VCC. When the signal at terminal 101 is more negative, the threshold voltage of transistors

22, 24, 30 and 32 is higher. When the threshold voltage of transistors 22, 24, 30 and 32 is higher, less leakage current occurs in cell 10. Thus, control circuit 100 via terminal 101 can modulate or control the threshold voltage of 1 or more of transistors 22, 24, 30 and 32.

Alternatively, the signal to terminal to 101 can be at various different voltage levels and of different signal types. For example, positive voltages, pulsing signals, or other types of bias signals can be utilized. Also, control circuit 100 can respond to various types of signals to produce the bias signal.

Control circuit 100 preferably responds to a read or write signal, word line decode, address signal, microprocessor control signal, or other signal which indicates that cell 10 is about to be accessed. Preferably, preparatory to the accessing of cell 10, control circuit 100 raises the voltage at terminal 101 so that the threshold voltage of natural transistors 22 and 24 is lowered to approximately 0.2V. After cell 10 is accessed, control circuit 100 responds to the read or write signal, word line decode, address signal, microprocessor control signal, or other signal and then lowers the voltage at terminal 101 so that the threshold voltage of natural transistors 22 and 24 is raised. Alternatively, just transistors 24 and 22, or just transistors 30 and 32, can be provided in P-well 104.

Control circuit 100 ensures that a high threshold voltage for transistors 22, 24, 30 and

32, can be provided when cell 10 is simply storing data. Thus, transistors 22, 24, 30 and 32 have minimum leakage current characteristics during storing because of a high threshold voltage during storing. Yet, transistors 22, 24, 30, and 32 are quickly accessible (e.g., readable and writable) because of a low threshold voltage during access.

With reference to Figure 3, a more detailed drawing of substrate 70, including wells

104 and 106 is shown. Well 104 includes transistors, such as, transistors 22, 24, 30 and 32 (Figure 1).

Well 106 includes transistors such as transistors 18 and 20. As an example, in Figure 3, transistor 18 in well 106 and transistor 22 in well 104 are shown. Wells 104 and 106 can be part of an array of wells for individually holding transistors 18, 20, 22, 24, 30 and 32. Further, a separate well (not shown) from well 106 can be provided for transistors 18 and 20.

It is understood that while the detailed drawings and specific examples given describe the preferred exemplary embodiments of the present invention, they are for the purpose of illustration only. The apparatus and method of the invention is not limited to the precise details, geometries, dimensions, voltages and conditions disclosed. For example, although particular threshold voltages are described as being particular values, other sizes could be utilized. Further, although certain types of wells and memory cells are discussed, other types of wells and memory cells can be utilized. Further, single lines in the various drawings can represent multiple conductors. Various changes can be made to the details withFout parting from the scope of the spirit of the invention which is defined by the following claims.

Industrial Applicability

The present invention can be utilized in semiconductor devices for storing data.

Claims

CLAIMSWhat is claimed is:

1. A semiconductor memory device (5), comprising: a semiconductor substrate (70) having a well (104), the well being coupled to a well contact (101) ; a memory cell (10) including at least one pass gate transistor (30, 32) formed within the well of the semiconductor substrate and at least one pull down transistor N-channel transistor (22,

24) formed within the well of the semiconductor substrate, the pull down transistor being doped to have a threshold voltage less than a threshold voltage of the pass gate transistor; and a control circuit (100) having an output coupled to the well contact, the control circuit providing a first substrate bias signal at the output when the memory cell is being accessed and providing a second substrate bias signal at the output when the memory cell is in a storage mode, whereby a threshold voltage of the pass gate transistor and the pull down transistor is greater when the second substrate bias signal is provided than when the first substrate bias signal is provided.

2. The semiconductor memory device of claim 1 wherein the memory device is an SRAM device and the memory cell includes two N-channel pull down transistors.

3. The semiconductor memory device of claim 2 further comprising a substrate contact coupled to the semiconductor substrate, the substrate contact being coupled to ground.

4. The semiconductor memory device of claim 3 wherein the semiconductor substrate is a P-type substrate and the well is a P-type well and wherein the well is disposed in a larger N-type well, the larger N-type well being disposed in the semiconductor substrate.

5. The semiconductor memory device of claim 1 wherein the pull down transistor is a natural transistor and the pass gate transistor is a regular enhancement mode transistor.

6. The semiconductor memory device of claim 1 wherein the first substrate bias signal is generated in response to an address signal, a read/write signal, a word line decode signal, or a microprocessor control signal.

7. The semiconductor memory deviceof claim 1 wherein the first substrate bias signal is provided during a read operation, during a write operation, or during either a read operation or a write operation.

-9-

8. A method of accessing a memory cell in a semiconductor memory (51), the memory cell including at least one natural MOS transistor (22, 24), the MOS transistor being formed in a semiconductor substrate (70), the semiconductor substrate having a first well (104) and a second well (106), the first well being doped with first dopants and the second well being doped with second dopants, the first dopants being an opposite conductivity type to the second dopants, the first well being disposed in the second well and coupled to a well contact (101), the method comprising steps of: addressing the memory cell; providing a first substrate signal to the well contact; performing a read operation or a write operation on the memory cell; and providing a second substrate signal to the well contact, wherein a threshold voltage of the natural MOS transistor is greater when the second substrate signal is provided than when the first substrate signal is provided.

9. The method of claim 8, wherein the addressing step include providing an address to a word line decoder.

10. An SRAM memory (5), comprising: a semiconductor substrate (70) having a first well (104) and a second well (106), the first well being doped with first dopants and the second well being doped with second dopants, the first dopants being an opposite conductivity type to the second dopants, the first well being disposed in the second well and coupled to a well contact (101); a memory cell including a plurality of natural MOS pull down transistors (22, 24) and a plurality of regular enhancement MOS pass gate transistors, the natural MOS pull down transistors being formed within the first well (104); and a substrate bias generator (100) having an output coupled to the well contact, the substrate bias generator providing a first substrate bias signal at the output when the memory cell is being accessed and providing a second substrate bias signal at the output when the memory cell is not being accessed, whereby a threshold voltage of the natural MOS pull down transistors is greater when the second substrate bias signal is provided than when the first substrate bias signal is provided.

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