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WO1999034435A1 - Carte imprimee, son procede de fabrication, et dispositif electronique utilisant cette carte imprimee - Google Patents

Carte imprimee, son procede de fabrication, et dispositif electronique utilisant cette carte imprimee Download PDF

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Publication number
WO1999034435A1
WO1999034435A1 PCT/JP1998/005865 JP9805865W WO9934435A1 WO 1999034435 A1 WO1999034435 A1 WO 1999034435A1 JP 9805865 W JP9805865 W JP 9805865W WO 9934435 A1 WO9934435 A1 WO 9934435A1
Authority
WO
WIPO (PCT)
Prior art keywords
connection
circuit board
electrode
lsi
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP1998/005865
Other languages
English (en)
Japanese (ja)
Inventor
Yasunori Narizuka
Hiroyuki Tenmei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of WO1999034435A1 publication Critical patent/WO1999034435A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0577—Double layer of resist having the same pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0597—Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3473—Plating of solder

Definitions

  • the present invention relates to a structure of a wiring board (circuit board) and a method of manufacturing the same for electronic devices in which an LSI is mounted on a substrate and functions, and is particularly suitable for an electronic device requiring reliability.
  • the present invention relates to a structure of a wiring board and a manufacturing method thereof.
  • connection electrodes of the LSI and the connection electrodes on the wiring board are connected by flexible wiring, the thermal expansion of the LSI and the wiring board in the connection and in the heating process after the connection is performed. There was almost no failure such as disconnection due to the coefficient difference. This is because in the case of the WB method, ultrafine wires of metal such as Au, A1, and Cu are flexibly deformed. In the case of the TAB method, connection terminals are formed on a flexible resin sheet together with wiring. The reason is that the connection part can be prevented from being broken by flexible deformation in response to external force. However, in these connection methods, connection terminals have to be arranged only on four sides of the LSI device due to the connection method itself.
  • connection there is a drawback that it is not possible to respond sufficiently.
  • connection (.C4) a connection method that combines the arrangement of the array and the connection by solder balls. It is called connection (.C4) and is applied only to limited products such as large computers, and has a proven track record.
  • connection (.C4) a connection method that combines the arrangement of the array and the connection by solder balls.
  • connection (.C4) is applied only to limited products such as large computers, and has a proven track record.
  • this connection method the connection terminals of the board and the LSI are directly connected with only minute solder balls, so if there is a difference in the coefficient of thermal expansion between the LSI and the wiring board, the heat Due to thermal stress in the process, the connection is broken after connection.
  • a resin is poured between the LSI and the board, and the overall adhesion of the resin is reduced.
  • a connection method has been proposed to prevent thermal stress from concentrating only on the connection terminals by fixing it to the substrate, and some have begun to be put into practical use.
  • This resin is called an underfill material, and this has expanded the application range of the interconnection of the LSI and the electrodes of the wiring board by the arrangement of the rear array.
  • connection process since bonding is performed to the plating film 5 that has a dotted surface on the surface of the flexible resin layer 3, ultrasonic bonding is difficult, and heat is directly applied to the resin layer 3. As a result, it is not possible to raise the temperature to a sufficiently high level, and thermocompression bonding is virtually unsatisfactory. Therefore, there is a problem in the connection method in this example. In order to reduce the stress, it is necessary that the resin layer 3 is in a state where it can easily move in the direction in which the shear force acts, that is, in the direction parallel to the surface of the substrate 2.
  • the present invention has been made in view of the above-mentioned problems of the related art, and has as its object to connect a wiring board and an LSI by heating, and to provide an auxiliary board such as a chip carrier. It is an object of the present invention to provide a substrate structure that can be connected with high reliability without using such a method and a method of manufacturing the same. Disclosure of the invention
  • connection using conductive resin or conductive adhesive has begun to be applied to mass production.
  • this also requires heating, although not as much as C4, to cure the resin or adhesive.
  • C4 heating, although not as much as C4.
  • a shear stress is generated at the connection portion after cooling due to a difference in thermal expansion coefficient between the substrate and the LSI. It is widely known that when the difference in the coefficient of thermal expansion is large, the connection is broken immediately after the connection due to the shearing force, and the breakage proceeds over a period of time. To avoid this, it is necessary to reduce the shear force in some way.
  • the thickness of the connection pad on the substrate surface or the LSI surface is set to a specific thickness or more, and the electrode itself is easily deformed using the thickness of the electrode.
  • the effect of the shearing force on the surface is suppressed. It is necessary to suppress the easily deformed part to the deformation below the breaking limit, which determines the conditions regarding the electrode thickness (height).
  • the ease with which the electrodes themselves are deformed depends not only on the height but also on the electrode area as described above, but as described above, the number of connection terminals of the LSI necessarily increases.
  • the flexibility of the electrodes tends to increase because it leads to a smaller area. If the original electrode area does not provide enough flexibility, The flexibility is improved by increasing the thickness of only part of the electrode and apparently reducing the area of the connection electrode.
  • FIG. 1 is a cross-sectional view showing a layout of a connection portion between a substrate and an LSI.
  • FIG. 2 is a cross-sectional view schematically showing a deformation of a connection portion between the substrate and the LSI.
  • FIG. 4 is a cross-sectional view for explaining a deformation model of a connection portion
  • FIG. 4 is a process explanatory view of a method of manufacturing a wiring board according to an embodiment of the present invention
  • FIG. 6 is an explanatory diagram of a method of manufacturing a wiring board according to one embodiment of the present invention.
  • FIG. 6 is an explanatory diagram of steps of a method of manufacturing a wiring board according to one embodiment of the present invention.
  • FIG. 1 is a cross-sectional view showing a layout of a connection portion between a substrate and an LSI.
  • FIG. 2 is a cross-sectional view schematically showing a deformation of a connection portion between the substrate and the LSI.
  • FIG. 4 is
  • FIG. 8 is a process explanatory view of a method of manufacturing a wiring board according to one embodiment of the present invention.
  • FIG. 8 is a process explanatory view of a method of manufacturing a wiring board according to one embodiment of the present invention.
  • FIG. 9 is a process explanatory view of a method for manufacturing a wiring board according to an embodiment of the present invention.
  • FIG. 10 is a view illustrating an embodiment of the present invention.
  • FIG. 11 is a process explanatory view of a method of manufacturing a wiring board
  • FIG. 11 is a process explanatory view of a method of manufacturing a wiring board according to an embodiment of the present invention
  • FIG. FIG. 13 is a process explanatory view of a method of manufacturing a wiring board according to the embodiment, FIG.
  • FIG. 13 is a process explanatory view of a method of manufacturing a wiring board according to an embodiment of the present invention
  • FIG. FIG. 15 is a process explanatory view of a method for manufacturing a wiring board according to an embodiment of the present invention.
  • FIG. 15 is a cross-sectional view of the wiring board that allows electrode layout change according to the present invention.
  • FIG. 6 is a cross-sectional view of a circuit board when the wiring board according to the present invention is applied to solder connection.
  • FIG. 17 is a cross-sectional view of a connection portion when the present invention is applied to both a wiring board and an LSI.
  • FIG. 18 is a cross-sectional view showing an example of a connection structure according to the prior art. BEST MODE FOR CARRYING OUT THE INVENTION
  • the coefficient of thermal expansion of the substrate 2 is a l
  • the coefficient of thermal expansion of the LSI is ct 2
  • the size of the LSI chip is a
  • the connection temperature is T l
  • the room temperature is ⁇ 2
  • the LSI 6 and the substrate connected by heating A distortion is generated between the two due to the difference in the coefficient of thermal expansion.
  • Fig. 1 considering the cross section of the LSI 6 and the substrate 2, and assuming that the distortion is the largest, and assuming that the connection electrodes 1 are provided at both ends of the LSI 6, when the connection is made at a high temperature,
  • the side surface of the columnar medium 7 is modeled and approximated by two arcs 8, 8 '.
  • the length of the lower half of the side surface before deformation is defined as hZ2, and this is the circumference of the lower half arc after deformation. If stretched to the length, the elongation strain £ is expressed by the following equation.
  • ⁇ (2 (arctan (x / h)) ((x2 + h2) / 4) ( ⁇ T (x2 + h2) / x) -h / 2) / (h / 2)
  • the elongation at break is about 30 to 40% even if it is not particularly pure, so based on the above calculation, if the elongation is 40%, then the size of the LSI is In the case of a 10 mm square, a thickness of about 10 ⁇ m is sufficient.
  • FIG. 4 An embodiment of a method of manufacturing a wiring board having a thick electrode as described above will be described with reference to FIGS. 4 to 14.
  • FIG. 4 An embodiment of a method of manufacturing a wiring board having a thick electrode as described above will be described with reference to FIGS. 4 to 14.
  • FIG. 4 An embodiment of a method of manufacturing a wiring board having a thick electrode as described above will be described with reference to FIGS. 4 to 14.
  • a resin layer 11 is formed on the entire surface of the wafer or the substrate.
  • the resin layer 11 may be formed by a process of applying a varnish and performing beta treatment, or may be formed by attaching a resin sheet coated with a heat-resistant adhesive.
  • the thickness of the resin layer 11 is preferably 1 m or more, which is good.
  • the upper limit is preferably about 50 m in consideration of the subsequent steps, but is not strictly limited to this range.
  • a hole is formed in the resin layer 11 to expose the connection electrode 1 on the surface of the wafer or the wiring board. If the thickness of the resin layer 11 exceeds 1 Q ⁇ m, dry etching or laser processing is appropriate, but if the resin layer 11 is thinner, wet etching can also be used. . At the time of processing, selectivity for the processing is required between the resin layer 11 and the base of the hole. If the protective layer 10 formed on the surface of the wafer or wiring board is inorganic, the resin layer 11 The hole can be made larger than the size of the window of the protective layer 10. Protective layer 1 ⁇ is organic In this case, since selectivity cannot be expected, it is better to form the hole smaller than the window of the protective layer 10 in terms of process stability.
  • the surface of the electrode 1 is cleaned, and then, as shown in FIG. 7, Cr or Ti is formed on the entire surface of the wafer or the wiring substrate, and then Cu is formed. Is formed. Since this two-layer film is used as a plating seed film 12 in a later step, it must have excellent adhesion to the surfaces of the resin layer 11 and the electrode 1. Although the two-layer film can be formed by electroless metal plating, it is preferable to form a thin film using Cr or Ti as an adhesive layer from the viewpoint of adhesiveness. When these thin films are formed, the sputtering method is most desirable in consideration of the adhesion of the resin layer 11 into the holes, and the film thickness of Cr or Ti is about 0.1 lm. 0 11 is about 1 / ⁇ 111 which is good.
  • a resin layer 13 having a predetermined thickness is formed on the plating seed film 12 on the entire surface of the wafer or substrate, as shown in FIG.
  • the thickness of the resin layer 13 determines the final thickness of the electrode described later.
  • the resin layer 13 is formed by attaching a resin sheet coated with a heat-resistant adhesive, but a varnish-like resin is applied. ⁇ It can also be formed by beta. Thereafter, as shown in FIG. 9, a hole is formed in the resin layer 13 on the electrode 1.
  • the thickness of the resin layer 13 is as thick as several tens to several hundreds of ⁇ m, dry etching or laser processing is considered in consideration of prevention of side etching. Good.
  • an ultraviolet laser can be used to form holes with a diameter of 50 ⁇ m and a depth of 250 m or more in polyimide sheets. If so, laser processing is optimal. In these processes, the holes are stopped by the metal layer, which is the seed film 12 of the plating, and the selectivity is reduced. Is good.
  • the diameter of this hole may be larger or smaller than the diameter of the lower hole. Further, as described above, the smaller the hole diameter, the better the flexibility of the electrode.
  • the position of the hole may be such that the exposed area of the surface of the electrode 1 can be secured as long as the resistance of the connection portion can be tolerated. May be out of range.
  • a hole is formed in advance by an appropriate means, and the hole is aligned with the electrode 1 on the wafer or the wiring board, and then bonded. It is also possible to take.
  • the metal film already formed is used as the seed film 12 and electroplating is performed, and the resin layer 1 is removed.
  • Cu plating is optimal for electrical plating, in which case a copper sulfate plating solution is better in terms of plating speed, stability, solution management, and the like.
  • the plated film 14 needs to completely fill the hole, and if it is about several ⁇ m, it may be raised from the hole. If the thickness variation is large, plating is performed on at least the entire surface of the wafer or wiring board until the holes in the resin layer 13 are completely filled, and then the part that has become too thick using a method such as tape polishing. Should be removed.
  • a thin resin film 15 is formed, and a portion corresponding to the upper surface of the plating film is formed. Open the window.
  • the process is long.
  • the electrodes on the surface of the wafer or the wiring board may be corroded, the process of covering the interface with the resin film 15 is simple. Further, as shown in FIG.
  • a protective metal film 16 for protecting the plating film 14 at the time of connection and improving the connection reliability is provided on the plated film 14 in which the holes are filled.
  • a film is formed by electric plating.
  • the material of this metal film 16 differs depending on how the wafer or wiring board is connected. For example, when using solder, two layers of Ni plating film and Au plating film are used. good c also, if connection with something like conductive adhesive can be applied alone a u film.
  • the electrodes are separated so that they can move easily when an external force is applied to the electrodes.
  • the removal of the unnecessary portion is preferably performed by dry etching or laser processing, similarly to the above-described hole processing.
  • the processing is completed when the metal film as the seed film 12 of the plating is finally exposed.
  • the resin layer 13 left around the plating film 14 does not need to be left for the purpose of the present invention. Rather, the remaining resin film adversely affects the deformation of the thickly stacked plating film due to external force. However, in order to protect the plating film 14 from the environment, it is desirable that the thickness of 5 ⁇ m or more remains to cover the plating film side surface.
  • the metal film of the plating seed film 12 exposed at the bottom of the portion from which the resin layer 13 was removed by the above separation step was removed by wet etching as shown in FIG. Separate the electrodes.
  • the Cr, Cu, and Ti described above as the metal film 12 damage the protective metal film 16 because they have etching selectivity with respect to the Au film formed to protect the plating film 14. Can be removed without any problem.
  • the wiring board according to the present invention is completed.
  • solder balls 20 are fixed to the electrode surface.
  • the wafer is positioned and placed at a predetermined position on the wiring board. After that, the connection is completed by performing normal reflow. Basically, this part of the process is no different from a traditional connection.
  • solder When solder is used for the connection, the deformation of the solder occurs in addition to the deformation of the electrodes, so that the effect of alleviating the shearing force is greater and the reliability can be further improved.
  • connection portion is cut off from the outside air, and the occurrence of connection failure due to oxidation and corrosion can be prevented. It becomes possible.
  • the present invention it is possible to directly connect an LSI to a substrate having a different thermal expansion coefficient from Si, which has been difficult in the past, for example, a substrate such as a printed wiring board.
  • a substrate such as a printed wiring board.
  • sufficient connection reliability can be ensured.
  • the connection can be made without the use of the conventional auxiliary substrate, the effective connection distance is shortened, and it is possible to sufficiently cope with future high-speed driving of the LSI.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

L'invention concerne un procédé de fabrication d'une carte imprimée à faible coût, cette carte étant constituée d'une structure capable de prévenir toute connexion défaillante pouvant être provoquée par des contraintes thermiques dues à la réalisation de liaisons de fixation, lesquelles permettent de connecter une carte imprimée à une autre par leurs bornes correspondantes. La carte imprimée de cette invention comprend des électrodes de connexion, formées sur cette carte de manière à former des connexions extérieures. Chacune de ces électrodes de connexion présente une partie qui fait saillie à plus de 10 νm au-dessus du niveau supérieur de conducteurs de câblage, cette partie saillante étant utilisée pour des connexions extérieures.
PCT/JP1998/005865 1997-12-25 1998-12-24 Carte imprimee, son procede de fabrication, et dispositif electronique utilisant cette carte imprimee Ceased WO1999034435A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP35760097A JPH11186335A (ja) 1997-12-25 1997-12-25 回路基板とその製造方法及びこれを用いた電子機器
JP9/357600 1997-12-25

Publications (1)

Publication Number Publication Date
WO1999034435A1 true WO1999034435A1 (fr) 1999-07-08

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Application Number Title Priority Date Filing Date
PCT/JP1998/005865 Ceased WO1999034435A1 (fr) 1997-12-25 1998-12-24 Carte imprimee, son procede de fabrication, et dispositif electronique utilisant cette carte imprimee

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Country Link
JP (1) JPH11186335A (fr)
WO (1) WO1999034435A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008114434A1 (fr) * 2007-03-20 2008-09-25 Fujitsu Limited Substrat de montage et procédé pour sa fabrication, dispositif semi-conducteur et procédé pour sa fabrication
JP5445167B2 (ja) * 2010-01-25 2014-03-19 パナソニック株式会社 半導体装置及びその製造方法
JP6197420B2 (ja) * 2013-07-11 2017-09-20 凸版印刷株式会社 配線基板
JP6368635B2 (ja) * 2014-12-10 2018-08-01 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63236339A (ja) * 1987-03-24 1988-10-03 Nec Corp 半導体集積回路装置
JPH01187948A (ja) * 1988-01-22 1989-07-27 Nec Corp 半導体装置
JPH01238044A (ja) * 1988-03-17 1989-09-22 Nec Corp 半導体装置
JPH04151843A (ja) * 1990-10-16 1992-05-25 Casio Comput Co Ltd Ｉｃチップのボンディング方法
JPH05343471A (ja) * 1990-10-12 1993-12-24 Toshiba Corp 半導体装置
JPH07211722A (ja) * 1994-01-26 1995-08-11 Toshiba Corp 半導体装置及び半導体装置実装構造体
JPH08288336A (ja) * 1995-04-14 1996-11-01 Citizen Watch Co Ltd 半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63236339A (ja) * 1987-03-24 1988-10-03 Nec Corp 半導体集積回路装置
JPH01187948A (ja) * 1988-01-22 1989-07-27 Nec Corp 半導体装置
JPH01238044A (ja) * 1988-03-17 1989-09-22 Nec Corp 半導体装置
JPH05343471A (ja) * 1990-10-12 1993-12-24 Toshiba Corp 半導体装置
JPH04151843A (ja) * 1990-10-16 1992-05-25 Casio Comput Co Ltd Ｉｃチップのボンディング方法
JPH07211722A (ja) * 1994-01-26 1995-08-11 Toshiba Corp 半導体装置及び半導体装置実装構造体
JPH08288336A (ja) * 1995-04-14 1996-11-01 Citizen Watch Co Ltd 半導体装置

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Publication number Publication date
JPH11186335A (ja) 1999-07-09

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