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WO1999032924A1 - Afficheur a cristaux liquides - Google Patents

Afficheur a cristaux liquides Download PDF

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Publication number
WO1999032924A1
WO1999032924A1 PCT/JP1997/004719 JP9704719W WO9932924A1 WO 1999032924 A1 WO1999032924 A1 WO 1999032924A1 JP 9704719 W JP9704719 W JP 9704719W WO 9932924 A1 WO9932924 A1 WO 9932924A1
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WO
WIPO (PCT)
Prior art keywords
liquid crystal
crystal display
pair
film
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP1997/004719
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English (en)
Japanese (ja)
Inventor
Masuyuki Ohta
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Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to PCT/JP1997/004719 priority Critical patent/WO1999032924A1/fr
Publication of WO1999032924A1 publication Critical patent/WO1999032924A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]

Definitions

  • the present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device used for a display device of a system that displays a moving image and requires high-quality video.
  • Liquid crystal display devices are widely used as display devices for portable devices typified by notebook computers because of their thin and lightweight characteristics.
  • active matrix type liquid crystal display devices using active elements typified by thin-film transistor elements (TFTs) have recently been used in desktop computers because of their high image quality comparable to a brown tube. It has begun to spread widely as display terminals for monitors and OA equipment.
  • liquid crystal display devices have specific disadvantages such as a narrow viewing angle and a slow response speed.
  • a display mode called an in-plane switching mode has been proposed as a method for improving the viewing angle, and the viewing angle is drastically improved.
  • Methods for improving the response speed include, for example, an optical compensatory bending (OCB) mode and a vertical alignment (VA) mode.
  • OBCB optical compensatory bending
  • VA vertical alignment
  • in-plane switching mode for example, see "R.Kiefer, B.Weber, F.W indcheidand G.Baur, isplay '9 2) pp. 5 4 7-5 5 0 ”, and for optical compensity bending mode (0CB), for example,“ T. U chidaand T. ⁇ i ⁇ as hita, Proceedings of The 2nd International Display Workshop (IDW'95) pp. 39-42, ⁇
  • For vertical alignment mode see, for example, Nikkei Microdevices, 1996. October issue, p 1 4 7 ”.
  • An object of the present invention is to solve the above-described problems.
  • An object of the present invention is to provide a wide viewing angle comparable to that of a Brownian tube, a high-speed response capable of responding to a moving image, and stable image quality for a long time.
  • An object of the present invention is to provide a highly reliable active matrix type liquid crystal display device which can be maintained at a high level.
  • the present invention provides, A pair of substrates, a liquid crystal composition having a positive dielectric anisotropy sandwiched between the pair of substrates, and an optical axis of liquid crystal molecules in the liquid crystal composition layer substantially without a voltage applied to the substrate surface when no voltage is applied.
  • An alignment control film that can be vertically aligned; a pair of electrode structures that generate an electric field in the liquid crystal composition layer that is substantially parallel to the substrate surfaces of the pair of substrates; an electric field component parallel to the substrate surface and one light transmission An angle with respect to the axis is about 45 degrees, and the other light transmission axis has a pair of polarizing plates arranged at one light transmission axis and about 90 degrees, and the liquid crystal composition layer is formed by the electric field. It is characterized by modulating the transmittance of light passing through the light.
  • a large number of scanning wirings, a large number of signal wirings, an active element formed at each intersection of the large number of scanning wirings and the large number of signal latitude lines is employed.
  • the semiconductor device includes the first configuration, a large number of scanning wirings, a large number of signal wirings, a thin film transistor element formed at a substantially intersection of the large number of scanning wirings and the large number of signal latitude lines.
  • the fourth configuration includes a pair of electrodes capable of generating an electric field substantially parallel to the substrate surfaces of the pair of substrates.
  • the fourth configuration includes the first configuration, and shields unnecessary light leakage portions to improve insulation.
  • the configuration has a black matrix.
  • a fifth configuration includes the first configuration, wherein a transparent conductive film is provided on at least one of the substrate surfaces of the pair of substrates opposite to the holding surface of the liquid crystal composition.
  • FIG. 1 is a sectional view showing the principle of the present invention.
  • FIG. 2 is a plan view showing the principle of the present invention.
  • FIG. 3 is a diagram showing the relationship between the direction of the applied electric field and the transmission axis of the polarizing plate according to the present invention.
  • FIG. 4 is a plan view of an essential part showing one pixel of a liquid crystal display portion of the active matrix type color liquid crystal display device according to the first embodiment of the present invention and its periphery.
  • FIG. 5 is a cross-sectional view of a pixel taken along section line 6-6 in FIG.
  • FIG. 6 is a cross-sectional view of the thin-film transistor element T FT along the 7-7 section line of FIG.
  • FIG. 7 is a cross-sectional view of the storage capacitor C stg at section line 8-8 in FIG.
  • FIG. 8 is a plan view for explaining the configuration of the matrix peripheral portion of the display panel.
  • Fig. 9 is a cross-sectional view showing a scanning signal terminal on the left side and a panel edge portion without an external connection terminal on the right side.
  • FIG. 10 is a plan and cross-sectional view showing the vicinity of the connection between the gate terminal GTM and the gate wiring GL.
  • FIG. 11 is a plan and cross-sectional view showing the vicinity of the connection between the drain terminal DTM and the video signal line DL.
  • FIG. 12 is a plan and cross-sectional view showing the vicinity of a connection part of the common electrode terminal C TM 1, the common bus line CB 1, and the common voltage signal line CL.
  • FIG. 13 is a plan and cross-sectional view showing the vicinity of a connection portion of the common electrode terminal C TM2, the common bus line CB 2, and the common voltage signal line CL.
  • FIG. 14 is a circuit diagram of the active matrix type color liquid crystal display device of the present invention, including the matrix portion and its periphery.
  • FIG. 15 is the active matrix liquid of the present invention.
  • FIG. 6 is a diagram showing a driving waveform of the crystal display device.
  • FIG. 16 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing processes of processes A to C on the substrate SUB1.
  • FIG. 17 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes D to E on the substrate SUB1.
  • FIG. 18 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process in a process G on the substrate SUB 1 side.
  • FIG. 19 is a top view showing a state where peripheral driving circuits are mounted on the liquid crystal display panel.
  • FIG. 20 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI constituting a drive circuit is mounted on a flexible wiring board.
  • FIG. 21 is a cross-sectional view of a principal part showing a state where the tape carrier package TCP is connected to the scanning signal circuit terminal GTM of the liquid crystal display panel PNL.
  • FIG. 22 is an exploded perspective view of the liquid crystal display module.
  • FIG. 23 is a plan view of a principal part showing one pixel of the liquid crystal display section of the active matrix type color liquid crystal display device of the second embodiment of the present invention and the periphery thereof.
  • FIG. 24 is a plan view of a principal part showing one pixel of a liquid crystal display section of an active matrix type color liquid crystal display device according to a third embodiment of the present invention and the periphery thereof.
  • FIG. 1 and Fig. 2 show the principle diagram of the present invention.
  • Figure 1 FIG. 2 is a view of a cross section of a display portion of one pixel of the liquid crystal display device of the present invention as viewed from a direction parallel to the substrate surface, and
  • FIG. 2 is a view as viewed from a direction perpendicular to the substrate surface. 1 and FIG. 2 are not shown for simplicity of description.
  • the long axis (optical axis) of most liquid crystal molecules in the liquid crystal composition layer is perpendicular to the substrate surface when no electric field is applied.
  • the initial state is controlled by the alignment control film (orientation film) so that they are arranged in different directions. In this initial state, there is no birefringence phase difference for the incident light.
  • the transmittance T Z T of light passing through the display of the liquid crystal display device of the present invention is determined by the arrangement of the polarizing plate shown in FIG. Is as follows.
  • T / T. sin 2 (2 ⁇ ) sin 2 ( ⁇ n-d / ⁇ ).
  • T is the output light intensity
  • ⁇ Is the incident light intensity
  • X is the angle between the liquid crystal molecules and the optical axis (the effective optical axis of the liquid crystal layer) and the polarization transmission axis of the polarizer
  • s is the wavelength of the incident light
  • d is the distance between the substrates (the effective thickness of the liquid crystal layer)
  • 7 ⁇ is the pi.
  • ⁇ n of the liquid crystal layer is controlled by applying a voltage. Then, by changing the second term of Expression 1, the transmittance is controlled, and a desired display is obtained.
  • the optical axis of the liquid crystal molecules is parallel to the substrate surface, and exhibits the maximum refractive index anisotropy with respect to the incident light.
  • the product (retardation) of the refractive index anisotropy ⁇ n of the liquid crystal and the thickness d of the liquid crystal layer is defined as the lZ 2 of the wavelength ⁇ of the incident light (approximately 400 1111 to 70011111).
  • the point that the present invention differs from the conventional vertical alignment mode is that, in the present invention, an electrode configuration for applying an electric field substantially parallel to the substrate surfaces of the pair of substrates to the liquid crystal composition layer causes the lines of electric force to flow. Since the liquid crystal molecules are curved in a semicircle, the movements of the liquid crystal molecules are inevitably separated in two directions. This is not necessary, and the alignment stability, which has been a problem, is improved, and high reliability for maintaining high image quality for a long time can be obtained.
  • the second effect is that the liquid crystal molecules at the interface between the alignment film and the liquid crystal are Since the fixing force (anchoring) is small, the liquid crystal molecules are easy to move in the liquid crystal layer, so that the response speed is extremely high.
  • an electric field is applied to move the optical axis of the liquid crystal molecules in a direction parallel to the substrate surface in order to obtain a high transmittance state (white display). It is necessary to use a liquid crystal composition having a negative dielectric anisotropy ( ⁇ ⁇ 0) having a property of aligning the optical axis in a direction perpendicular to the substrate.
  • a liquid crystal composition having a positive dielectric anisotropy ⁇ > 0
  • the liquid crystal having dielectric anisotropy aligns the optical axis in the same direction as the electric field direction).
  • the fourth effect is that the direction of the applied electric field determines the direction of the optical axis of the liquid crystal molecules in a plane parallel to the substrate surface, so that the rubbing treatment or the like performed in the conventional vertical alignment mode is performed. It is not necessary to control the alignment direction at the same time. Thereby, the movement of the liquid crystal molecules due to the alignment regulating force can be improved, and the response speed can be further improved.
  • FIG. 4 is a plan view showing one pixel of the active matrix type color liquid crystal display device of the present invention and its periphery.
  • each pixel consists of a scanning signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line (counter electrode wiring), and two adjacent video signals.
  • the line (drain signal line or vertical signal line) is arranged in the intersection area with the DL (in the area surrounded by four signal lines).
  • Each pixel includes a thin film transistor TFT, a storage capacitor Cstg, a pixel electrode PX, and a counter electrode CT.
  • the scanning signal lines GL and the counter voltage signal lines CL extend in the left-right direction in the figure, and a plurality of scanning signal lines GL are arranged in the vertical direction.
  • the video signal lines DL extend in the up-down direction, and a plurality of video signal lines DL are arranged in the left-right direction.
  • the pixel electrode PX is electrically connected to the thin-film transistor TFT via the source electrode SD1, and the counter electrode CT is also electrically connected to the counter voltage signal line CL.
  • the pixel electrode PX and the counter electrode CT are opposed to each other, and the electric state of the liquid crystal composition LC is controlled by an electric field substantially parallel to the substrate surface generated between each pixel electrode PX and the counter electrode CT, and the display is performed. Control.
  • the pixel electrode PX and the counter electrode CT are formed in a comb-like shape, and each is a thin electrode extending upward and downward in the figure.
  • the counter electrode CT and the pixel electrode PX are alternately arranged, and the counter electrode CT is adjacent to the video signal line DL.
  • the electric field between the counter electrode CT and the pixel electrode PX is affected by the electric field generated from the video signal line DL.
  • unnecessary lines of electric force from the video signal line DL can be shielded by the counter electrode CT.
  • the counter electrode CT is different from the pixel electrode in that the potential is constantly supplied from the outside through the counter voltage signal line CL described later, so that the potential is stable, and the potential fluctuates almost even when adjacent to the video signal line DL. Absent. Therefore, unnecessary electric power lines from the video signal lines DL can be shielded. In addition, since the geometric position of the pixel electrode PX from the video signal line DL is farther away, the parasitic capacitance between the pixel electrode PX and the video signal line DL is greatly reduced, and the video signal of the pixel electrode potential Vs Fluctuation due to voltage can also be suppressed. Thus, it is possible to suppress crosstalk (improper image quality called vertical smear) occurring in the vertical direction.
  • crosstalk improper image quality called vertical smear
  • the electrode widths of the pixel electrode PX and the counter electrode CT are respectively 6 6 ⁇ .
  • the thickness is set to be sufficiently larger than 3.9 m of a liquid crystal composition layer described later. Desirably, the thickness is set to 1.5 times or more of the liquid crystal composition layer.
  • the video signal line DL is also 6 m.
  • the electrode width of the video signal line DL may be slightly wider than the pixel electrode PX and the counter electrode CT in order to prevent disconnection.
  • the electrode width of the video signal line DL is set to be less than twice the electrode width of the adjacent counter electrode CT.
  • the electrode width of the counter electrode CT adjacent to the video signal line DL is set to be equal to or more than 1 to 2 of the electrode width of the video signal line DL.
  • the unnecessary lines of electric force generated from the video signal line DL are absorbed by the counter electrodes CT on both sides, respectively.
  • the lines with the same width or more must be absorbed.
  • Electrode An electrode with a width is required. Therefore, since the lines of electric force generated from half (4 ⁇ m each) of the electrode of the video signal line DL need only be absorbed by the counter electrode CT on each side, the electrode of the counter electrode CT adjacent to the video signal line DL is required.
  • the width should be 1 Z 2 or more. This prevents crosstalk due to the effect of the video signal, and in particular, prevents vertical (vertical) crosstalk.
  • the width of the scanning signal line GL is set so as to satisfy a resistance value enough to transmit a scanning voltage sufficiently to the gate electrode GT of the terminal pixel (opposite to the scanning electrode terminal GTM described later).
  • a sufficient counter voltage is applied to the counter voltage signal line CL to the counter electrode CT of the pixel on the terminal side (the pixel farthest from the common bus lines CB 1 and CB 2 described later, that is, the pixel between CB 1 and CB 2).
  • the electrode spacing between the pixel electrode PX and the counter electrode CT changes depending on the liquid crystal material used. This is because the electric field intensity that achieves the maximum transmittance varies depending on the liquid crystal material, so the electrode spacing is set according to the liquid crystal material, and the signal voltage set by the withstand voltage of the video signal drive circuit (signal driver) used. This is so that the maximum transmittance can be obtained in the maximum amplitude range.
  • the electrode interval is 16 im. ⁇ Cross-sectional configuration of matrix part (pixel part) ⁇
  • FIG. 5 is a cross-sectional view of FIG. 4 taken along the line 6-6
  • FIG. 6 is a cross-sectional view of the thin film transistor TFT taken along the line 7-7 of FIG. 4
  • FIG. 7 is F. 4 is a diagram showing a cross section of the storage capacitor Cstg at the 8-8 cutting line of ig. 4.
  • FIG. 5 to Fig. 7 the lower transparent glass substrate SUB1 has a thin film transistor TFT, a storage capacitor Cstg and an electrode on the SUB1 side with respect to the liquid crystal composition layer LC. A group is formed, and a color filter FIL and a light blocking black matrix pattern BM are formed on the upper transparent glass substrate SUB2 side.
  • alignment films AF 1 and AF 2 for controlling the initial alignment of the liquid crystal are provided on the inner surface (the liquid crystal LC side) of each of the transparent glass substrates SUB 1 and SUB 2.
  • a polarizing plate is provided on the outer surface of each of the sub 2 and the sub 2.
  • the thin-film transistor TFT When a positive bias is applied to the gate electrode GT, the thin-film transistor TFT operates such that the channel resistance between the source and the drain decreases, and when the bias is reduced to zero, the channel resistance increases. .
  • the thin-film transistor TFT has a gate electrode GT, an insulating film GI, an i-type (intrinsic, not doped with intrinsic ⁇ conductivity-type-determining impurities) amorphous silicon (S i), an i-type semiconductor layer AS, a pair of source electrodes SD 1, and a drain electrode SD 2.
  • the source and drain are originally determined by the bias polarity between them, and the polarity of the liquid crystal display device is reversed during operation, so that the source and drain are switched during operation. However, in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.
  • the gate electrode GT is formed continuously with the scanning signal line GL, and is configured so that a part of the scanning signal line GL becomes the gate electrode GT.
  • Gate electrode GT exceeds the active area of thin-film transistor TFT Part.
  • the gate electrode GT is formed of a single conductive film g3.
  • a chromium-molybdenum alloy (Cr-Mo) film formed by using a spark is used, but not limited thereto.
  • the scanning signal line GL is formed of the conductive film g3.
  • the conductive film g3 of the scanning signal line GL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, and is integrally formed.
  • a gate voltage (scanning voltage) Vg is supplied from an external circuit to the gate electrode GT through the scanning signal line GL.
  • the conductive film g3 for example, a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering is used as the conductive film g3, for example, a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering is used.
  • the scanning signal lines GL and the gate electrodes GT are not limited to the chromium-molybdenum alloy, but may be made of, for example, aluminum or an aluminum alloy to reduce resistance. It may be a two-layer structure wrapped in ribden.
  • the part that intersects with the video signal line DL is made thinner to reduce the probability of a short circuit with the video signal line DL, and even if it is short-circuited, it can be separated by laser trimming. You may be bifurcated.
  • the counter voltage signal line CL is formed of the conductive film g3.
  • the conductive film g3 of the counter voltage signal line CL is formed in the same manufacturing process as the gate electrode GT, the scanning signal line GL, and the conductive film g3 of the counter electrode CT, and is electrically connected to the counter electrode CT. It is configured to be able to do so.
  • the counter voltage Vcom is supplied from an external circuit to the counter electrode CT through the counter voltage signal line CL.
  • the counter voltage signal line CL is not limited to the chromium-molybdenum alloy, but may be, for example, an aluminum alloy to reduce resistance. It may be a two-layer structure in which a chrome or aluminum alloy is wrapped with chromium-molybdenum.
  • the portion that intersects with the video signal line DL is made thinner to reduce the probability of short-circuit with the video signal line DL, and even if it is short-circuited, it can be separated by laser trimming. It may be forked.
  • the insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistor TFT.
  • the insulating film GI is formed above the gate electrode GT and the scanning signal line GL.
  • a silicon nitride film formed by plasma CVD is selected, and is formed to a thickness of 2000 to 450 persons (in this embodiment, about 350 A).
  • the insulating film GI also functions as an inter-layer insulating film of the scanning signal line GL, the counter voltage signal line CL, and the video signal line DL, and also contributes to their electrical insulation.
  • the i-type semiconductor layer AS is made of amorphous silicon and has a thickness of 150 to 250 A (in this embodiment, a thickness of about 1200 A).
  • the layer d0 is an N (+) type amorphous silicon semiconductor layer obtained by doping a phosphorus (P) for a common contact, and an i-type semiconductor layer AS exists on the lower side and an upper side on the upper side. It is left only where the conductive layer d3 is present.
  • the i-type semiconductor layer AS and the layer d0 are also provided between the scanning signal line GL and the intersection (crossover portion) between the counter voltage signal line CL and the video signal line DL.
  • the i-type semiconductor layer AS at the intersection reduces a short circuit between the scanning signal line GL and the counter voltage signal line CL and the video signal line DL at the intersection.
  • Each of the source electrode SD 1 and the drain electrode SD 2 is formed of a conductive film d3 that is in contact with the N (+) type semiconductor layer d0.
  • the conductive film d3 uses a chromium-molybdenum alloy (Cr—Mo) film formed by sputtering and has a thickness of 500 to 300 OA (in this embodiment, about 2 ⁇ 0 OA). ) Is formed. Since the Cr-Mo film has low stress, it can be formed relatively thick, which contributes to lowering the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d O.
  • Cr—Mo chromium-molybdenum alloy
  • MoSi2, TiS refractory metal silicide
  • TaSi2, WSi2 refractory metal silicide
  • the video signal line DL is formed of a conductive film d3 of the same layer as the source electrode SD1 and the drain electrode SD2.
  • the video signal line DL is formed integrally with the drain electrode SD2.
  • the conductive film d3 uses a chromium-molybdenum alloy (Cr—Mo) film formed by sputtering, and has a thickness of 500 to 300 OA (in this example, , About 250 OA). Since the Cr-Mo film has low stress, it can be formed relatively thick, which contributes to lowering the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d 0.
  • Cr—Mo chromium-molybdenum alloy
  • MoSi 2, Ti high melting point metal silicide
  • a film may be used, or a laminated structure with aluminum or the like may be used.
  • the conductive film d 3 is a thin film transistor TFT source electrode SD 2 portion In this case, it is formed so as to overlap the counter voltage signal line CL. As is clear from Fig. 7, this superposition is performed by using a storage capacitor (capacitance element) in which the source electrode SD 2 (d 3) is used as one electrode and the counter voltage signal CL is used as the other electrode.
  • the dielectric film of the storage capacitor C stg is composed of an insulating film GI used as a gate insulating film of the thin-film transistor TFT.
  • the storage capacitance C stg is formed in a part of the counter voltage signal line CL in plan view.
  • a protective film PSV1 is provided on the thin film transistor TFT.
  • the protective film PSV1 is mainly formed to protect the thin film transistor TFT from moisture and the like, and uses a film having high transparency and good moisture resistance.
  • the protective film PSV1 is formed of, for example, a silicon oxide film / silicon nitride film formed by a plasma CVD device, and has a thickness of about 0.1 to 1 m.
  • the protective film PSV1 is removed so as to expose the external connection terminals DTM and GTM.
  • the former is made thicker in consideration of the protective effect, and the latter is made thinner by the transconductance gm of the transistor.
  • through holes TH 2 and TH 1 are provided for electrical connection between the counter voltage signal line CL and a counter electrode CT described later, and for electrical connection between the source electrode SD 2 and the pixel electrode PX.
  • the protective film PSV1 and the insulating film GI are added together so that a hole up to the g3 layer is formed. A hole is made.
  • the protective film PSV 1 is made of a thick organic film such as polyimide. It may have a laminated structure with the object.
  • the pixel electrode PX is formed of the transparent conductive layer i1.
  • This transparent conductive film i1 is composed of a transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering, and has a thickness of 100 to 200 mm (in this embodiment, , About 140 people).
  • the pixel electrode ⁇ X is connected to the source electrode SD2 via the through hole ⁇ 1.
  • the transmitted light in that part improves the maximum transmittance when white display is performed, so that a brighter display is displayed than when the pixel electrode is opaque. It can be carried out.
  • the liquid crystal molecules maintain the initial alignment state, and the polarizing plate is arranged so as to display black in that state (normal black mode). Therefore, even if the pixel electrode is transparent, light of that part does not pass through, and high-quality black can be displayed. As a result, the maximum transmittance can be improved, and a sufficient contrast ratio can be achieved.
  • the counter electrode C is formed of the transparent conductive layer i1.
  • the transparent conductive film i1 is made of a transparent conductive film (Indium-Tin-Oxide ITO: Nesa film) formed by sputtering, and has a thickness of 100 to 200 A (in this embodiment, , About 140 people).
  • the common electrode CT is connected to the common voltage signal line CL via the through-hole # 2. As in the case of the pixel electrode ⁇ , by making the counter electrode transparent, the maximum transmittance when white display is performed is improved.
  • the counter electrode C ⁇ is configured so that a counter voltage V com is applied. I have.
  • the counter voltage Vcom turns off the thin-film transistor element TFT from an intermediate DC potential between the minimum level drive voltage Vdmin and the maximum level drive voltage Vdmax applied to the video signal line DL.
  • Fi over Dosuru voltage delta V s min which occurred at the time of, if you want to decrease the power supply voltage of the integrated circuit to be used in the video signal driver circuit to approximately half, by applying an alternating voltage Good.
  • the transmitted light from unnecessary gaps is emitted to the display surface side so as not to lower the contrast ratio etc.
  • a light-shielding film BM (so-called black matrix) is formed on the surface.
  • the light shielding film BM also serves to prevent external light or backlight light from entering the i-type semiconductor layer AS. That is, the i-type semiconductor layer AS of the thin film transistor TFT is sandwiched between the upper and lower light shielding films BM and the large gate electrode GT, and is exposed to external natural light or backlight light. It disappears.
  • the light-shielding film BM shown in FIG. 4 has a configuration extending linearly in the left-right direction above the thin-film transistor element TFT.
  • This pattern is an example, and the opening may be formed in a matrix shape with holes.
  • the display of that part corresponds to the video information in the pixel on a one-to-one basis, and is black in black and white in white. Therefore, it can be used as part of the display.
  • the counter electrode CT and the video signal The gap with the signal line DL is shielded from light by a second light-shielding layer SH formed in the same process as the gate electrode GT.
  • the light shielding in the vertical direction in the horizontal direction can be accurately shielded with the alignment accuracy of the TFT process, so that the boundary of the second light shielding layer S ⁇ between the electrodes of the counter electrode C ⁇ adjacent to the video signal line DL is formed. It can be set and the opening can be enlarged more than the light shielding by the light shielding film ⁇ which depends on the alignment accuracy of the upper and lower substrates.
  • the light-shielding film can be formed on the thin-film transistor substrate SUB1.
  • the opening can be further enlarged as compared with the light-shielding by the light-shielding film BM on the substrate SUB2 which depends on the accuracy of the upper and lower substrates.
  • the light-shielding film BM has a light-shielding property and is formed of a highly insulating film so as not to affect the electric field between the pixel electrode PX and the counter electrode CT.
  • the organic pigment is mixed with a resist material to form a thickness of about 1.2 im.
  • carbon and titanium oxide (TixOy) can be maintained to improve the light shielding property, and 108 ⁇ cm or more, whose insulating property does not affect the electric field in the liquid crystal composition layer, can be maintained. It may be mixed within the range.
  • the second light-shielding layer SH has conductivity so as to easily absorb electric power from the video signal line.
  • the light-shielding film BM is linearly formed in the pixels in each row in the left-right direction, and the lines partition the effective display area in each row. Therefore, the outline of the pixels in each row is made clear by the light-shielding film BM. That is, the light shielding film BM has two functions of black matrix and light shielding for the i-type semiconductor layer AS.
  • the light-shielding film BM is also formed in a frame shape at the peripheral portion, and its pattern is formed continuously with the pattern of the matrix portion shown in FIG.
  • the light-shielding film BM in the peripheral portion is extended outside the seal portion SL to prevent leakage light such as reflected light due to a mounting machine such as a personal computer from entering the matrix portion and to prevent the light from leaking. It also prevents light such as light from leaking out of the display area.
  • the light-shielding film BM is retained about 0.3 to 1.0 mm inside the edge of the substrate SUB2, and is formed so as to avoid the cut region of the substrate SUB2.
  • the color filter FIL is formed in a stripe shape by repeating red, green, and blue at a position facing the pixel.
  • the color filter FIL is formed so as to overlap the edge portion of the double light shielding film SH.
  • the color filter FIL can be formed as follows. First, a dye base such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dye base other than the red filter formation region is removed by photolithography. Thereafter, the dyed base material is dyed with a red pigment and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing a similar process. A dye may be used for dyeing.
  • a dye base such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2
  • the dye base other than the red filter formation region is removed by photolithography. Thereafter, the dyed base material is dyed with a red pigment and subjected to a fixing treatment to form a red filter R.
  • a green filter G and a blue filter B are sequentially formed by performing a similar process.
  • a dye may be used for dyeing.
  • the overcoat film 0C is provided to prevent the dye of the color filter FIL from leaking to the liquid crystal composition layer LC, and to flatten the steps due to the color filter FIL and the light shielding film BM.
  • the overcoat film 0C is formed of, for example, a transparent resin material such as an acrylic resin or an epoxy resin. Further, as the bar coat film C, an organic film such as polyimide having good fluidity may be used.
  • the liquid crystal layer, the alignment film, the polarizing plate, and the like will be described.
  • the dielectric anisotropy ⁇ £ is positive and its value is 13.2
  • the nematic liquid crystal is used.
  • the thickness (gap) of the liquid crystal composition layer is set to 3.8, and the retardation ⁇ ⁇ d is set to 0.31 m.
  • the value of this retardation ⁇ n ⁇ d (combination of refractive index anisotropy and gap) is between 0.25 ⁇ m and 0.35 ⁇ m, preferably between 0.35 ⁇ m and 0.35 ⁇ m.
  • the maximum transmittance can be obtained when the optical axes of the liquid crystal molecules are arranged in the direction of the electric field.
  • the thickness (gap) of the liquid crystal composition layer is controlled by polymer beads.
  • the liquid crystal material LC is not particularly limited.
  • the specific resistance of the liquid crystal composition 1 0 9 Q cm or more 1 0 1 4 ⁇ cm or less, preferably using the following 1 O ⁇ Q cm or more 1 0 1 3 Q cm.
  • the resistance of the liquid crystal composition is low, it is sufficiently retained child a voltage charged between the pixel electrode and the counter counter electrode, the lower limit 1 0 9 ⁇ cm, the preferred properly 1 O ⁇ Q cm. This is because the pixel electrode and the counter electrode are configured on the same substrate.
  • 1 0 1 4 Q cm or less preferred properly is 1 0 1 3 Q cm or less is good.
  • the alignment film AF for example, polyimide (JALS203) manufactured by Nippon Synthetic Rubber Co., Ltd. is used.
  • This alignment film has a hydrophobic group (eg, CH 3) on the surface, and the major axis (optical axis) of the liquid crystal molecules is arranged in a direction perpendicular to the substrate surface.
  • CH 3 hydrophobic group
  • the major axis (optical axis) of the liquid crystal molecules is arranged in a direction perpendicular to the substrate surface.
  • the polarizer POL a conductive polarizer is used, and the polarization transmission axis MAX1 of the lower polarizer POL1 is set to about the electric field application direction (the direction orthogonal to the longitudinal direction of the comb-teeth electrode). Set the angle to 45 degrees, and make the polarization transmission axis MAX2 of the upper deflector P0L2 perpendicular to it.
  • FIG. 3 shows the relationship. As a result, the display as shown in the operation can be performed, and the normally closed characteristic in which the transmittance increases as the applied voltage (the voltage between the pixel electrode PX and the counter electrode CT) increases. Can be obtained.
  • measures are taken against display failure and EMI caused by static electricity from the outside by imparting conductivity to the polarizing plate.
  • conductivity if only to measure the effects of static electricity, sheet resistance 1 0 8 ⁇ port below Nodea lever to measures against ⁇ ⁇ ⁇ , 1 0 4 ⁇ / mouth below It is desirable that Further, a conductive layer may be provided on the back surface (the surface on which the polarizing plate is adhered) of the sandwiching surface of the liquid crystal composition of the glass substrate. ⁇ Phase difference film ⁇
  • negative retardation films NRF1 and NRF2 were provided between the upper polarizing plate and the upper glass substrate and between the lower polarizing plate and the lower glass substrate, respectively. Further, between the upper polarizing plate and the upper glass substrate, a finer positive retardation film P RF was further provided.
  • either one of the negative retardation films may be used, and when only one is used, the retardation film is almost the same as the retardation of the liquid crystal layer. However, better black level can be obtained in all viewing angle directions by using two sheets.
  • the direction of n x is Ru is orthogonal to the slight inclination direction from the normal direction of the substrate surface of the optical axes of the liquid crystal molecules.
  • the horizontal direction is set. This compensates for birefringence due to a slight inclination of the substrate surface from the normal direction, and furthermore makes it possible to obtain a good black level in all viewing angle directions. Note that this is not necessary when the optical axis of the minute positive retardation film liquid crystal molecules exactly coincides with the normal direction of the substrate surface.
  • FIG. 8 is a diagram showing a plane of a main part around a matrix (AR) of a display panel PNL including upper and lower glass substrates SUB 1 and SUB 2.
  • FIG. 9 is a view showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side.
  • the external connection terminal groups T g and T d and the terminal COT exist (the upper and left sides in the figure) are exposed on the upper substrate SUB 2 so that they are exposed.
  • the size is limited inside the lower substrate SUB1.
  • the terminal groups Tg and Td are respectively a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM, and their lead-out wiring portions, which will be described later, are tape carrier packages TCP (Fig. 1) on which an integrated circuit chip CHI is mounted. 9, Fig. 20) is a group of multiple units.
  • the lead wiring from the matrix part of each group to the external connection terminal part is inclined as approaching both ends.
  • the counter electrode terminal COT is a terminal for applying a counter voltage to the counter electrode CT from an external circuit. Opposite voltage of matrix part
  • the signal line CL is drawn out to the opposite side (right side in the figure) of the scanning circuit terminal GTM, and the common voltage signal lines are grouped together by a common bus line CB and connected to the common electrode terminal COT.
  • a seal pattern SL is formed between the transparent glass substrates SUB1 and SUB2 along the edges of the transparent glass substrates SUB1 and SUB2 so as to seal the liquid crystal LC except for the liquid crystal inlet INJ.
  • the sealing material is made of, for example, an epoxy resin.
  • the layers of the alignment films ⁇ RI 1 and ⁇ RI 2 are formed inside the seal pattern SL.
  • the polarizing plates POL1 and POL2 are formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.
  • the liquid crystal LC is sealed in a region partitioned by the seal pattern SL between the lower alignment film 0RI1 and the upper alignment film 0RI2 for setting the direction of the liquid crystal molecules.
  • the lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.
  • liquid crystal display device various layers are separately stacked on the lower transparent glass substrate SUB 1 side and the upper transparent glass substrate SUB 2 side, and a seal pattern SL is formed on the substrate SUB 2 side. It is assembled by superimposing the upper transparent glass substrate SUB2, injecting liquid crystal LC through the opening INJ of the sealing material SL, sealing the inlet INJ with epoxy resin, and cutting the upper and lower substrates.
  • FIG. 10 is a diagram showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM, wherein FIG. 10 — A is a plane and FIG. 10 — B shows the cross section of the Fig. 10 — A cut at the B — B section line.
  • the figure corresponds to the vicinity of FIG. 8 below, and the diagonal wiring portion is represented by a straight line for convenience.
  • the Cr-Mo layer g3 is hatched for easy understanding.
  • the gate terminal G TM is a transparent conductive layer i for improving the reliability of the connection between the Cr-Mo layer g 3 and the surface of the Cr-Mo layer g 3 and the TCP (Tape Carrier Package). It consists of one and one.
  • the transparent conductive layer i1 uses a transparent conductive film IT # formed in the same step as the pixel electrode PX.
  • the insulating film GI and the protective film PSV1 are formed on the right side of the boundary line, and the terminal portion GTM located on the left end is exposed therefrom so that it can make electrical contact with an external circuit.
  • the terminal portion GTM located on the left end is exposed therefrom so that it can make electrical contact with an external circuit.
  • FIG. 8 In the figure, only one pair of the gate line GL and the gate terminal is shown, but in reality, such pairs are arranged in a row at the top and bottom as shown in FIG. 8, and the terminal group T g (FIG. 8) is formed, and the left end of the gate terminal is extended beyond the cut area of the substrate in the manufacturing process and is short-circuited by the wiring SH g (not shown). This is useful for preventing electrostatic breakdown during rubbing of the alignment film ORI1 in the manufacturing process.
  • FIG. 11 is a diagram showing the connection from the video signal line DL to its external connection terminal DTM, FIG. 11 1 —A indicates the plane, and FIG. Ll — B indicates FIG. 1 Shows a cross section of 1 _ A at B-B section line. 8 corresponds to the vicinity of the upper right of FIG. 8 and the direction of the drawing is changed for convenience, but the right end corresponds to the upper end of the substrate SUB1.
  • TST d is a test terminal, which is not connected to an external circuit, but is wider than the wiring part so that probe needles can be contacted.
  • the drain terminal DTM is wider than the wiring part so that it can be connected to external circuits.
  • the external connection drain terminals DTM are arranged in the vertical direction, and the drain terminals DTM constitute a terminal group Td (subscript omitted) as shown in FIG. 5 and extend beyond the cutting line of the substrate SUB1. Further All of them are wired together to prevent electrostatic breakdown during the manufacturing process.
  • the inspection terminal TSTd is formed on every other video signal line DL as shown in FIG. 11.
  • the drain connection terminal DTM is formed of the transparent conductive layer i1, and is connected to the video signal line DL at a portion where the protective film PSVI is removed.
  • This transparent conductive film # 1 uses a transparent conductive film ITO formed in the same step as the pixel electrode ⁇ ⁇ , as in the case of the gate terminal GTM.
  • the lead-out wiring from the matrix part to the drain terminal part DTM has a layer d3 at the same level as the video signal line DL.
  • Fig. 1 2 is a diagram showing the connection from the counter voltage signal line CL to its external connection terminal CTM, Fig. 1 2 —A indicates the plane, and Fig. 1 2-B is F] '. g. 1 2 — Shows the cross section of A along the line B — B The figure corresponds to the vicinity of the upper left of FIG.
  • the common voltage signal lines CL are collectively connected to a common bus line CB1 and are led to a common electrode terminal CTM.
  • the common bus line CB has a structure in which a conductive layer 3 is laminated on a conductive layer g3 and they are electrically connected by a transparent conductive layer i1. This is to reduce the resistance of the common bus line CB so that the opposing voltage is sufficiently supplied from an external circuit to each opposing voltage signal line CL.
  • the feature of this structure is that the resistance of the common bus line can be reduced without any additional load on the conductive layer.
  • the counter electrode terminal CTM has a structure in which a transparent conductive layer i1 is laminated on a conductive layer g3.
  • This transparent conductive film i 1 uses the transparent conductive film IT 0 formed in the same process as the pixel electrode PX, as in the case of the other terminals.
  • Transparent conductive layer i 1 protects its surface and prevents electrolytic corrosion Therefore, the conductive layer g3 is covered with a transparent conductive layer il having high durability.
  • the connection between the transparent conductive layer i 1 and the conductive layer g 3 and the conductive layer d 3 is formed by forming through holes in the protective film PSV 1 and the insulating film GI to establish conduction.
  • FIG. 13 is a diagram showing the connection from the other end of the counter voltage signal line CL to its external connection terminal CTM 2, and FIG. 13—A shows the plane, and FIG. 1 3 — B shows the cross section of Fig. 1 3 — A taken along section line B-B. The figure corresponds to the vicinity of the upper right in FIG. 5.
  • the common bus line CB2 the other end (gate terminal GTM side) of each counter voltage signal line CL is brought together to be drawn to the counter electrode terminal CTM2.
  • the difference from the common bus line CB1 is that the common bus line CB1 is formed of a conductive layer d3 and a transparent conductive layer i1 so as to be insulated from the scanning signal line GL. Insulation with the scanning signal line GL is performed by the insulating film GI.
  • Fig.14 shows the connection diagram of the equivalent circuit of the display matrix and its peripheral circuits. Although this figure is a circuit diagram, it is drawn corresponding to the actual geometric arrangement.
  • AR is a matrix array in which a plurality of pixels are arranged two-dimensionally.
  • X represents a video signal line DL
  • suffixes G, B, and R are added corresponding to green, blue, and red pixels, respectively.
  • Y means the scanning signal line GL, and the subscripts 1, 2, 3,..., End are added according to the order of the scanning timing.
  • the scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V, and the video signal line X (subscript omitted) is connected to the video signal driving circuit H.
  • SUP provides multiple divided and stabilized voltage sources from one voltage source. It is a circuit that includes a power supply circuit for obtaining the information and a circuit for exchanging information for the cathode ray tube (CRT) from the host (higher-level processing unit) with information for the TFT LCD.
  • CRT cathode ray tube
  • FIG. 15 shows a driving waveform of the liquid crystal display device of this embodiment.
  • the counter voltage Vc is a constant voltage. Scanning signal V g in each scanning period, takes on level, others take off level.
  • the video signal voltage is applied so that the positive and negative poles are inverted every frame and transmitted to one pixel with twice the amplitude of the voltage to be applied to the liquid crystal layer.
  • the polarity of the video signal voltage Vd is inverted every column, and the polarity is also inverted every two rows.
  • the pixels whose polarities are inverted are arranged vertically and horizontally, so that flicker and crosstalk (smear) can be suppressed.
  • the counter voltage Vc is set to a voltage which is a certain amount lower than the center voltage of the polarity inversion of the video signal voltage. This is to correct the feedthrough voltage generated when the thin film transistor element changes from ON to OFF, and is performed to apply an AC voltage having a small DC component to the liquid crystal. When a direct current is applied to a liquid crystal, afterimages, deterioration, and the like become severe.
  • the maximum amplitude of the video signal voltage can be reduced by converting the counter voltage into an alternating current, and a low withstand voltage signal can be used for the video signal drive circuit (signal-side driver).
  • the storage capacitor C stg is provided to store video information (after the thin-film transistor TFT is turned off) written to the pixel for a long time.
  • the method of applying an electric field parallel to the substrate surface used in the present invention unlike the method of applying an electric field perpendicular to the substrate surface, most of the capacitance (so-called liquid crystal capacitance) composed of the pixel electrode and the counter electrode is used.
  • No storage capacity C stg Cannot store video information in pixels. Therefore, in a system in which an electric field is applied in parallel with the substrate surface, the storage capacitance Cstg is an essential component.
  • the storage capacitor Cstg also works to reduce the influence of the gate potential change AVg on the pixel electrode potential Vs when the thin film transistor TFT switches. This situation is represented by the following equation.
  • V s ⁇ C gs / (C gs + C stg + C pix) ⁇ x ⁇ V g
  • C gs is a parasitic capacitance formed between the gate electrode GT of the thin-film transistor TFT and the source electrode SD 1
  • Cpix is a capacitance formed between the pixel electrode PX and the counter electrode CT.
  • AVs represents a so-called feed-through voltage corresponding to a change in pixel electrode potential due to AVg.
  • the change AVs causes a DC component applied to the liquid crystal LC, but the value can be reduced as the storage capacitance C stg is increased.
  • the reduction of the DC component applied to the liquid crystal LC improves the life of the liquid crystal LC, and reduces the so-called burn-in in which the previous image remains when switching the liquid crystal display screen.
  • the gate electrode GT is made large to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 increases, and therefore the parasitic capacitance is increased. C gs increases, and the pixel electrode potential Vs has an adverse effect of being easily affected by the gate (scan) signal Vg.
  • this disadvantage can be eliminated by providing the storage capacitor Cstg.
  • FIGS. 16 to 18 a method of manufacturing the above-described liquid crystal display device on the substrate SUB 1 side will be described with reference to FIGS. 16 to 18.
  • the middle letter is the abbreviation of the process name, and the left side is shown in Fig. 6.
  • the thin film transistor TFT part, the right side shows the processing flow viewed from the cross-sectional shape near the gate terminal shown in Fig. 10.
  • Processes A to I were classified according to each photographic process except process B and process D. All cross-sectional views of each process were completed after photographic process and the photo resist was removed. Shows the stages.
  • photographic processing refers to a series of operations from application of a photo resist, through selective exposure using a mask to development of the resist, and a repeated description is omitted. The following is an explanation according to the divided steps.
  • a conductive film g 3 made of Cr—Mo and having a thickness of 2000 is provided by sputtering. After the photographic processing, the conductive film g3 is selectively etched with ceric ammonium nitrate. Accordingly, the gate electrode GT, the scanning signal line GL, the counter voltage signal line C, the gate terminal GTM, the first conductive layer of the common bus line CB1, and the first conductive layer of the counter electrode terminal CTM1.
  • a bus line SH g (not shown) connecting the layer and the gate terminal GTM is formed.
  • Ammonia gas, silane gas, and nitrogen gas were introduced into the plasma CVD apparatus, and a 350 OA-thick Si nitride film was provided.
  • silane gas and hydrogen gas are introduced into the plasma CVD apparatus, After an i-type amorphous Si film of 200 A is provided, hydrogen gas and phosphine gas are introduced into a plasma CVD apparatus, and an N (+)-type amorphous Si film having a thickness of 30 OA is formed.
  • a membrane Provide a membrane.
  • an island of the i-type semiconductor layer AS is formed by selectively etching the N (+)-type amorphous Si film and the i-type amorphous Si film.
  • a conductive film d3 made of Cr having a thickness of 300 is formed by sputtering. After the photographic processing, the conductive film d3 is etched with the same liquid as in step A, and the first conductive layer of the video signal line DL, the source electrode SD1, the drain electrode SD2, the common bus line CB2, and the drain are formed. Form a bus line SH d (not shown) that shorts the terminal DTM. Next, the N (+)-type semiconductor layer between the source and the drain is etched by introducing CC14 and SF6 into the dry etching apparatus and etching the N (+)-type amorphous Si film. d O is selectively removed.
  • the N (+) type semiconductor layer dO is removed using the conductive film d3 as a mask.
  • the N (+)-type semiconductor layer d0 remaining on the i-type semiconductor layer AS portions other than the conductive film d1 and the conductive film d2 are removed by self-alignment.
  • the i-type semiconductor layer AS is also slightly etched at its surface, but the extent is the etching time. Can be controlled by
  • Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD device to provide a 0.4 // m thick nitrided Si film.
  • the passivation of the protective film PSV1 and the insulating film GI is performed by selectively etching the nitrided Si film using SF6 as a dry etching gas.
  • the protective film PSV1 and the insulating film GI are patterned with the same photomask and are processed collectively.
  • a transparent conductive film i1 composed of an IT0 film having a thickness of 1,400 people is provided by sputtering. After the photographic processing, the transparent conductive film i 1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, so that the top layer of the gate terminal GTM, the drain terminal DTM, and the counter electrode terminals CTM 1 and CTM A second conductive layer is formed.
  • FIG. 19 is a top view showing a state where the video signal drive circuit H and the vertical scanning circuit V are connected to the display panel PNL shown in FIG.
  • TCP is the driving IC chip for driving the display panel PNL (the lower five driving IC chips on the vertical scanning circuit side, and each of the left ten driving IC chips on the video signal driving circuit side).
  • TCP is a carrier package in which the driving IC chip CHI is mounted by tape automated bonding (TAB).
  • TAB tape automated bonding
  • This is a drive circuit board on which TCPs, capacitors, etc. are mounted. It is divided into two parts, one for the video signal drive circuit and the other for the scan signal drive circuit.
  • FGP is a frame ground pad, and a spring-like fragment provided by cutting into the shield case SHD is soldered.
  • FC is a flat cable for electrically connecting the lower drive circuit board PCB1 to the left drive circuit board PCB1. As shown in the figure, the flat cable FC is made up of a striped polyethylene layer and a polyvinyl alcohol layer consisting of striped polyethylene (tin bronze material with Sn plating). Use the one that is supported by the switch.
  • FIG. 20 constitutes the scanning signal drive circuit V and the video signal drive circuit H
  • FIG. 21 shows a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI is mounted on a flexible wiring board
  • FIG. 21 shows the cross-sectional structure of a liquid crystal display panel, in this example, a scanning signal circuit terminal GT.
  • FIG. 4 is a cross-sectional view of a main part showing a state connected to M.
  • TTB is an input terminal and a wiring portion of the integrated circuit CHI
  • TTM is an output terminal and a wiring portion of the integrated circuit CHI.
  • the lead pad is connected to the bonding pad PAD of the integrated circuit CHI by the so-called phase-bonding method.
  • the outer ends of the terminals TTB and TTM correspond to the inputs and outputs of the semiconductor integrated circuit chip CHI, respectively.
  • CR TZT FT conversion circuits and power supply circuits Connected to the liquid crystal display panel PNL by ACF.
  • the package TCP is connected to the panel so that its tip covers the protective film PSV 1 exposing the connection terminal GTM on the panel PNL side.
  • the external connection terminal GTM (DTM) is connected to the protective film PSV 1 or the package. At least one side of TCP is covered, making it more resistant to touch.
  • B F 1 is a base film made of polyimide or the like
  • S R S is a solder resist film for masking so that solder does not adhere to unnecessary portions during soldering.
  • the gap between the upper and lower glass substrates outside the seal pattern SL is washed and protected by epoxy resin EPX, etc., and the silicone resin SIL is further filled between the package TCP and the upper substrate SUB2 to multiplex protection. .
  • the driving circuit board PCB 2 has electronic components such as ICs, capacitors, and resistors mounted thereon.
  • This drive circuit board PCB 2 has one voltage source A power supply circuit for obtaining a plurality of divided and stabilized voltage sources from a computer, and a circuit for converting information for a CRT (cathode ray tube) from a host (high-level processing unit) to information for a TFT liquid crystal display A circuit SUP that includes is installed.
  • CJ is a connector connection part to which a connector (not shown) connected to the outside is connected.
  • the drive circuit board PCB1 and the drive circuit board PCB2 are electrically connected by a flat cable FC.
  • FIG. 22 is an exploded perspective view showing each component of the liquid crystal display module MDL.
  • SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, LCB is a light guide, RM is a reflection plate, and BL is a back plate.
  • the light fluorescent tube and LCA are backlight cases, and the components are stacked in a vertical arrangement as shown in the figure to assemble the module MDL.
  • the entire module MDL is fixed by claws and hooks provided on the shield case SHD.
  • the knock case LCA is configured to house the backlight fluorescent tube BL, light diffusion plate SPB light diffusion plate, light guide LCB, and reflection plate RM, and the battery case LCA is placed on the side of the light guide LCB.
  • the light from the fluorescent light tube BL is converted into a uniform backlight on the display surface by the light guide LCB, the reflector RM, and the light diffuser SPB, and emitted to the liquid crystal display panel PNL.
  • An inverter circuit board PCB3 is connected to the backlight fluorescent tube BL, and serves as a power source for the backlight fluorescent tube BL.
  • FIG. 23 shows the active matrix type color liquid of this embodiment.
  • FIG. 2 is a plan view of a principal part showing one pixel of a liquid crystal display portion of a liquid crystal display device and its periphery.
  • the counter electrode CT is formed integrally with the counter electrode signal line CL.
  • Other configurations are the same as those of the first embodiment, and the effects of the present invention are also the same.
  • FIG. 24 is a plan view of a principal part showing one pixel of the liquid crystal display portion of the active matrix type color liquid crystal display device of this embodiment and the periphery thereof.
  • the counter electrode CT is formed integrally with the counter electrode signal line CL
  • the pixel electrode PX is formed integrally with the source electrode SD1.
  • Other configurations are the same as those of the first embodiment, and the effects of the present invention are also the same.
  • liquid crystal display device that can achieve a high contrast ratio, a wide viewing angle characteristic, and a high reliability that can maintain high image quality.
  • the present invention is applied to liquid crystal and the like as described above, and has practical application in the liquid crystal manufacturing industry.

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Abstract

Afficheur à cristaux liquides caractérisé par un grand angle de vision, une réaction rapide avec la qualité d'un tube cathodique, une image d'excellente qualité et une grande fiabilité. L'afficheur comprend une paire de substrats; une composition d'un cristal liquide ayant une anisotropie positive de la constante diélectrique, interposée entre la paire de substrats; une couche de commande du calage, qui oriente vers la face du substrat les axes optiques de presque toutes les molécules de cristal liquide contenues dans une couche de la composition lorsqu'aucune tension n'est appliquée; et une paire d'électrodes, qui appliquent à la couche de la composition de cristal liquide un champ électrique sensiblement parallèle aux faces de la paire de substrats et qui modulent la transmission de la lumière par ladite couche de composition. Cet afficheur à cristaux liquides possède un rapport de contraste élevé, un grand angle de vision, une grande fiabilité et une bonne compatibilité de la qualité d'image. Il affiche les images avec une vitesse de réaction très élevée et peut être excité même à une tension faible.
PCT/JP1997/004719 1997-12-19 1997-12-19 Afficheur a cristaux liquides Ceased WO1999032924A1 (fr)

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PCT/JP1997/004719 WO1999032924A1 (fr) 1997-12-19 1997-12-19 Afficheur a cristaux liquides

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CN100347598C (zh) * 2003-12-22 2007-11-07 夏普株式会社 显示元件和显示装置
CN100447638C (zh) * 2002-05-31 2008-12-31 夏普株式会社 液晶显示装置及其生产方法
WO2009154258A1 (fr) * 2008-06-18 2009-12-23 シャープ株式会社 Panneau à cristaux liquides et dispositif d'affichage à cristaux liquides
WO2009154021A1 (fr) * 2008-06-18 2009-12-23 シャープ株式会社 Panneau à cristaux liquides et dispositif d’affichage à cristaux liquides
JP2010217853A (ja) * 2008-06-18 2010-09-30 Sharp Corp 液晶パネルおよび液晶表示装置
WO2011024495A1 (fr) * 2009-08-24 2011-03-03 シャープ株式会社 Dispositif d'affichage à cristaux liquides
US8054435B2 (en) 2008-06-18 2011-11-08 Sharp Kabushiki Kaisha Liquid crystal panel and liquid crystal display device
JP2012168567A (ja) * 2012-06-14 2012-09-06 Semiconductor Energy Lab Co Ltd 液晶表示装置、パーソナルコンピュータ、ディスプレイ、電子書籍
JPWO2010137217A1 (ja) * 2009-05-29 2012-11-12 シャープ株式会社 液晶パネルおよび液晶表示装置
JP5389923B2 (ja) * 2009-07-31 2014-01-15 シャープ株式会社 液晶パネルおよび液晶表示装置

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CN100447638C (zh) * 2002-05-31 2008-12-31 夏普株式会社 液晶显示装置及其生产方法
CN100347598C (zh) * 2003-12-22 2007-11-07 夏普株式会社 显示元件和显示装置
WO2009154258A1 (fr) * 2008-06-18 2009-12-23 シャープ株式会社 Panneau à cristaux liquides et dispositif d'affichage à cristaux liquides
WO2009154021A1 (fr) * 2008-06-18 2009-12-23 シャープ株式会社 Panneau à cristaux liquides et dispositif d’affichage à cristaux liquides
JP2010217853A (ja) * 2008-06-18 2010-09-30 Sharp Corp 液晶パネルおよび液晶表示装置
US8054435B2 (en) 2008-06-18 2011-11-08 Sharp Kabushiki Kaisha Liquid crystal panel and liquid crystal display device
CN102047175B (zh) * 2008-06-18 2013-11-20 夏普株式会社 液晶面板和液晶显示装置
JPWO2010137217A1 (ja) * 2009-05-29 2012-11-12 シャープ株式会社 液晶パネルおよび液晶表示装置
JP5389923B2 (ja) * 2009-07-31 2014-01-15 シャープ株式会社 液晶パネルおよび液晶表示装置
WO2011024495A1 (fr) * 2009-08-24 2011-03-03 シャープ株式会社 Dispositif d'affichage à cristaux liquides
CN102472936A (zh) * 2009-08-24 2012-05-23 夏普株式会社 液晶显示装置
JP2012168567A (ja) * 2012-06-14 2012-09-06 Semiconductor Energy Lab Co Ltd 液晶表示装置、パーソナルコンピュータ、ディスプレイ、電子書籍

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