[go: up one dir, main page]

WO1999031711A3 - Circuit de precharge pour memoire a semiconducteur - Google Patents

Circuit de precharge pour memoire a semiconducteur Download PDF

Info

Publication number
WO1999031711A3
WO1999031711A3 PCT/KR1998/000430 KR9800430W WO9931711A3 WO 1999031711 A3 WO1999031711 A3 WO 1999031711A3 KR 9800430 W KR9800430 W KR 9800430W WO 9931711 A3 WO9931711 A3 WO 9931711A3
Authority
WO
WIPO (PCT)
Prior art keywords
precharge
precharge circuit
memory device
semiconductor memory
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR1998/000430
Other languages
English (en)
Other versions
WO1999031711A2 (fr
Inventor
Dae-Soon Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
WiniaDaewoo Co Ltd
Original Assignee
Daewoo Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Daewoo Electronics Co Ltd filed Critical Daewoo Electronics Co Ltd
Publication of WO1999031711A2 publication Critical patent/WO1999031711A2/fr
Publication of WO1999031711A3 publication Critical patent/WO1999031711A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

L'invention concerne un circuit de précharge destiné à une mémoire à semiconducteur, servant à précharger des lignes de bit au moyen de lignes de données d'entrée/de sortie. Dans le circuit de précharge présenté, des lignes de données d'entrée/de sortie normales et complémentaires reçoivent sélectivement une tension de précharge ou un signal de commande d'entrée/de sortie de données et préchargent les lignes de bits normales et complémentaires de la mémoire à semiconducteur ou exécutent une détection d'informations normale en réaction au signal reçu. Des multiplexeurs normaux et complémentaires sélectionnent la tension de précharge ou le signal de commande d'entrée/de sortie de données en réaction à un signal de commande de précharge, pour émettre vers les lignes de données d'entrée/de sortie normales et complémentaires. Grâce audit circuit de précharge, l'opération de précharge est exécutée au moyen de lignes d'entrée/de sortie de données sans circuit de précharge supplémentaire. Ainsi, on évite une augmentation de surface due à un circuit de précharge lors de la conception d'une mémoire RAM dynamique qui présente donc une surface réduite.
PCT/KR1998/000430 1997-12-17 1998-12-15 Circuit de precharge pour memoire a semiconducteur Ceased WO1999031711A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1997/69620 1997-12-17
KR1019970069620A KR19990050493A (ko) 1997-12-17 1997-12-17 반도체 메모리 장치용 프리차지 회로

Publications (2)

Publication Number Publication Date
WO1999031711A2 WO1999031711A2 (fr) 1999-06-24
WO1999031711A3 true WO1999031711A3 (fr) 1999-09-30

Family

ID=19527615

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR1998/000430 Ceased WO1999031711A2 (fr) 1997-12-17 1998-12-15 Circuit de precharge pour memoire a semiconducteur

Country Status (2)

Country Link
KR (1) KR19990050493A (fr)
WO (1) WO1999031711A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108540124A (zh) * 2018-04-16 2018-09-14 电子科技大学 一种电平转换电路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2294345A (en) * 1994-10-13 1996-04-24 Samsung Electronics Co Ltd Voltage boosting circuit of a semiconductor memory
US5608688A (en) * 1995-10-05 1997-03-04 Lg Semicon Co., Ltd. DRAM having output control circuit
US5636171A (en) * 1994-06-04 1997-06-03 Samsung Electronics Co., Ltd. Semiconductor memory device having low power self refresh and burn-in functions

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5636171A (en) * 1994-06-04 1997-06-03 Samsung Electronics Co., Ltd. Semiconductor memory device having low power self refresh and burn-in functions
GB2294345A (en) * 1994-10-13 1996-04-24 Samsung Electronics Co Ltd Voltage boosting circuit of a semiconductor memory
US5608688A (en) * 1995-10-05 1997-03-04 Lg Semicon Co., Ltd. DRAM having output control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108540124A (zh) * 2018-04-16 2018-09-14 电子科技大学 一种电平转换电路

Also Published As

Publication number Publication date
KR19990050493A (ko) 1999-07-05
WO1999031711A2 (fr) 1999-06-24

Similar Documents

Publication Publication Date Title
EP0383080A3 (fr) Mémoire à semi-conducteur
EP0726577A3 (fr) Mémoire RAM synchrone à double porte
AU1424297A (en) Circuit and method for enabling a function in a multiple memory device module
TW337018B (en) Semiconductor nonvolatile memory device
KR930001226A (ko) 고속 센싱 동작을 수행하는 센스 앰프
EP0401521B1 (fr) Dispositif de mémoire à semi-conducteurs
KR960025791A (ko) 센스 앰프회로
US5506522A (en) Data input/output line sensing circuit of a semiconductor integrated circuit
TW286404B (en) Semiconductor memory device for reducing operating power consumption amount
KR880014564A (ko) 메모리 장치용 출력 버퍼 제어회로
JP2658768B2 (ja) ダイナミックｒａｍ
TW331643B (en) Bit line sensor amplifier array for semiconductor memory device
TW200615968A (en) Local input/output line precharge circuit of semiconductor memory device
US5754487A (en) Bit line precharge circuit
US5742185A (en) Data bus drive circuit for semiconductor memory device
KR960025011A (ko) 메모리장치의 데이타 입출력 감지회로
WO1999031711A3 (fr) Circuit de precharge pour memoire a semiconducteur
IE811741L (en) Semiconductor read only memory device
WO2004055821A3 (fr) Architecture pour memoires magnetiques rapides
KR960019307A (ko) 반도체 메모리장치
WO2003032322A3 (fr) Circuit de memoire reglable a auto-synchronisation
US5781041A (en) Sense amplifier with low power in a semiconductor device
KR850008238A (ko) 반도체 기억장치
KR100191022B1 (ko) 반도체 집적회로 장치
KR100238863B1 (ko) 데이타 출력버퍼의 제어회로

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

122 Ep: pct application non-entry in european phase