WO1999008204A1 - Device and method for processing data - Google Patents

Abstract

An arithmetic circuit having sum-of-product units corresponding in number to elements used for linearly converting vectors having four elements, first register files for storing 4x4 matrixes of linear conversion, second register files for storing the vectors having four elements which become the object of the linear conversion, and third register files for storing the results of linear conversion are provided as a basic mechanism for improving the processing speed of two-dimensional discrete cosine or two-dimensional inverse discrete cosine and, at the same time, the arithmetic circuit is controlled so that the reading out direction of values from the first register files can be set to the line direction when a class-1 matrix arithmetic instruction is executed and to the column direction when a class-2 matrix arithmetic instruction is executed by providing the two kinds of the class-1 and class-2 matrix arithmetic instructions as arithmetic instructions for the matrixes of the first register files and the vectors of the second register files.

Description

 Description Data processing device and data processing method

 The present invention relates to a data processing device such as a microprocessor or a microcomputer, and more particularly to a data processing device suitable for executing an image processing application program including two-dimensional discrete cosine transform and two-dimensional inverse discrete cosine transform. . Background art

 If the image data is left unprocessed, the data volume will be enormous, and there will be problems such as the need for a large-capacity memory when storing the image data and the long transmission time when transferring the data. Therefore, measures are taken such as compressing the image data before storing it in the memory and decompressing it immediately before use, or compressing the image data before transmission and decompressing it after reception.

 Hereinafter, compression and decompression of image data will be described with reference to an example of encoding of a still image conforming to the JPEG standard. According to the JPEG standard, compression is a combination of the following two methods.

 (1) Two-dimensional discrete cosine transform (D CT)

 (2) Huffman coding

On the other hand, elongation is a combination of the following two methods.

 (3) Huffman decoding

 (4) 2D inverse discrete cosine transform

The two-dimensional discrete cosine transform (1) is performed on a value group of a two-dimensional block of 8 × 8 pixels. Specifically, a product is obtained by multiplying a value group of an 8 × 8 pixel two-dimensional block by a determinant called a DCT base. Therefore, the result of the transformation (referred to as DCT coefficient) is also a value group of a 2D block of 8 × 8 pixels. The transformed DCT coefficients are quantized using a quantization table having a different value for each coefficient position (the process of replacing a value in a certain section with a representative value in that section). image In the two-dimensional discrete cosine transform of data, the lower right part of the transformed block usually has many values close to 0, and most of them have the characteristic of being 0 in the quantization process.

 The Huffman coding (2) is a process of converting the quantized value group of the 8 × 8 pixel block into a bit stream. At this time, encoding is performed using the point where the value in the 8 × 8 pixel block has many 0s. In other words, variable-length coding is performed in which a short bit string code is assigned to a signal value having a high appearance probability. As a result, the number of bytes in the bitstream after encoding is about 1/10 of the number of bytes in the data stream before conversion.

 The Huffman decoding (3) is a reverse process of the Huffman coding (2). In other words, it is the process of restoring the bit stream into the value group of the 8 × 8 pixel block. The two-dimensional inverse discrete cosine transform (4) is an inverse transform of the two-dimensional discrete cosine transform (1). That is, the value group of the 8 × 8 pixel block is subjected to the inverse processing of the two-dimensional discrete cosine transform (1), and the value group of the first 8 × 8 pixel block is restored. Specifically, the image data is restored by obtaining a product by multiplying the value group (DCT coefficient) of the 8 × 8 pixel block decoded by the Huffman decoding process and the DCT base.

Note that the quantization performed in the two-dimensional discrete cosine transform (1) allows the value group of the 8 × 8 pixel block before the two-dimensional discrete cosine transform and the value group after the two-dimensional inverse discrete cosine transform (4) to be performed. Will not exactly match the value group of the 8 × 8 pixel block in. In other words, irreversible compression and decompression processing. However, unless the quantization is extremely coarse, the difference between the current image and the restored image can hardly be discerned by the human eye, so there is no practical problem. As described above, the advantage that image compression reduces the required number of bytes of image data to about 1/10 and the storage efficiency and transfer efficiency to the storage device by about 10 times has been described. On the other hand, however, there is a disadvantage in that the time and effort required for the compression Z expansion processing of the image data increases. For example, if the image data is stored in the storage device without being compressed, the image data can be used immediately by simply reading it from the storage device. However, if the compressed image data is stored in the storage device, the image data is read from the storage device. After that, it can be used only after decompressing it and restoring the original image data. When compressing and decompressing image data using a general-purpose microprocessor studied before the present invention by the present inventors, Huffman encoding processing and Huffman decoding processing of (2) and (3) per 8 × 8 pixel block are performed. Each requires about 1000 execution instructions, and the discrete cosine transform and inverse discrete cosine transform processing (1) and (4) require about 1000-2000 each. Therefore, the encoding by (1) and (2) or the decoding by (3) and (4) requires about 2000-13000 instructions per 8 x 8 pixel block. .

 Therefore, if the required number of instructions per 640 x 480 pixel colored image is simply converted, the number of instructions required for each color is 4,800 times that of the above processing, and the total number of instructions is 14,400 times. In other words, conventional microprocessors need to execute about 28.8M-43.2M instructions (M means one million [MEGA]) per image to encode and decode image data . Here, if it takes one clock on average to process one instruction, it can be seen that a micro-processor operating at 100 MHz requires a processing time of 288 nf 432 msec per image. At such a processing speed, even if a still image is to be displayed continuously, the processing pitch is 2 to 4 per second, which makes it possible to produce a moving image effect by displaying the still image continuously. It will be difficult.

 Therefore, reducing the size of the screen, preparing special hardware for compression and decompression, reducing the number of instructions by introducing sophisticated algorithms, and machine language capable of processing two or more instructions per clock Some means such as adopting an execution method (super scalar) are required.

 Note that in the above explanation, the processing of (1) and (4)

We stated that 1000-2000 instructions are required, but a simple algorithm without any ingenuity means about 2000 instructions, and a sophisticated algorithm requires about 1000 instructions.

 An object of the present invention is to provide a data processing device capable of executing two-dimensional discrete cosine transform and two-dimensional inverse discrete cosine transform at high speed.

An object of the present invention is to provide a basic mechanism (minimum hardware conditions) of a data processing device necessary for executing a two-dimensional discrete cosine transform or a two-dimensional inverse discrete cosine transform at a high speed and to effectively utilize the same. Form for instruction and basic mechanism by the instruction To provide a control method.

 The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

 The outline of typical inventions disclosed in the present application is briefly described as follows.

 In other words, in the present invention, as a basic mechanism for speeding up the two-dimensional discrete cosine transform and the two-dimensional inverse discrete cosine transform, a multiply-accumulator of a number corresponding to the number of elements for linearly transforming a vector having four elements is used. Is prepared. Also, the first register file for storing the 4x4 matrix of the linear transformation, the second register file for storing the vector of 4 elements to be subjected to the linear transformation, and the result of the linear transformation Prepare a third Registrar file to do this. Furthermore, two types of matrix operation instructions of the first type and the second type are prepared as operation instructions for the matrix of the first register file and the vector of the second register file, and the first type of matrix operation instruction is executed. In this case, the arithmetic circuit is controlled so that the reading direction of each value from the first register file is set to the row direction, and when the second type matrix operation instruction is executed, the reading direction is set to the column direction.

 As a result, when there are two register files or when there is only one type of matrix operation instruction, it is necessary to store the data in the register file again during the 2D discrete cosine transform or 2D inverse discrete cosine transform. However, by applying the present invention, it becomes unnecessary to store data in such a register file again, and as a result, two-dimensional discrete cosine transform and two-dimensional inverse discrete cosine transform are performed at high speed. You will be able to BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a block diagram showing an embodiment of a microprocessor suitable for applying the present invention.

FIG. 2 is a block diagram showing a specific example of a central processing unit (CPU) constituting a microprocessor. Figure 3 shows a coprocessor (F) suitable for efficiently executing the TRV and TRVT instructions.

FIG. 3 is a diagram showing an example of an arithmetic circuit constituting P U).

 FIG. 4 is a diagram showing an embodiment of the product-sum unit in the arithmetic circuit of the coprocessor.

 FIG. 5 is a diagram showing an embodiment of the register unit of the coprocessor.

 FIG. 6 is a diagram showing a matrix related to the inverse discrete cosine transform and its submatrix decomposition.

 FIG. 7 is a diagram showing a matrix subjected to the inverse discrete cosine transform and its decomposition into submatrices.

 Fig. 8 is a diagram showing the definition formula of the two-dimensional inverse discrete cosine transform, and decomposing it into sub-matrices to expand the definition formula.

 FIG. 9 is a diagram showing a procedure for calculating (Equation 3-10) in FIG.

 FIG. 10 is a diagram showing the concept of a register file.

 FIG. 11 is a diagram showing the instruction format of the TRV instruction and the TRVT instruction.

 FIG. 12 is a diagram showing arithmetic expressions for explaining the instruction functions of the TRV instruction and the TRVT instruction.

 FIG. 13 is a diagram showing an arrangement of data stored in the memory when performing the inverse discrete cosine transform as viewed from a conversion program.

 Figure 14 is a diagram showing the definition formula of the two-dimensional discrete cosine transform and the expansion of the definition formula by decomposing it into sub-matrices.

 FIG. 15 is a diagram illustrating another configuration example of the register unit of the coprocessor capable of executing the TRV instruction and the TRVT instruction. BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a microprocessor suitable for applying the present invention. In FIG. 1, 1 is a central processing unit (hereinafter, referred to as a CPU), 2 is a coprocessor (hereinafter, referred to as an FPU) that performs operations such as matrix multiplication and floating-point operation in place of the CPU 1, and 3 is a peripheral circuit. In response to interrupt requests from 1, 12, and 13 and an exception request signal from MMU 4 described later, priority is determined and An interrupt control circuit that outputs an interrupt signal IRQ, 4 is a memory management unit (MMU) that converts the address signal output from the CPU 1 onto the bus 8a to manage virtual memory, and 5 is a logical address. It is an address conversion circuit consisting of an address conversion table for converting to a physical address.

 Reference numeral 6 denotes a high-speed cache memory for storing the program data frequently used by the CPU 1, and reference numeral 7 denotes an address signal output from the CPU 1 to the bus, and a predetermined replacement algorithm. The data in the external main memory (such as a hard disk storage device, not shown) is transferred to the cache memory 6 in a predetermined block unit according to the above, or the unnecessary data in the cache memory 6 is discarded or written to the cache memory 6. It is a cache controller that stores the copied data in the main memory by the copy-back method or the write-through method. The cache memory 6 and the external main memory are accessed by the physical address signal converted in the address conversion table 5.

 In the single-chip microprocessor of this embodiment, the address conversion table 5 is provided separately from the logical address bus 8a and the data bus 9a for transmitting the logical address signal and the data signal output from the CPU 1. A physical address bus 8b for transmitting the converted physical address signal and a data bus 9b for transferring data between the cache memory 6 and an external main memory are provided. An external bus interface circuit 10 for interfacing signals between the buses 8b and 9b and the external bus is provided.

 Further, in this embodiment, separately from the logical address side buses 8a and 9a and the physical address side buses 8b and 9b, a serial communication interface circuit 11 for serial communication, clocking of the current time, There are provided a peripheral address bus 8c and a peripheral data bus 9c to which peripheral circuits such as a real-time clock circuit 12 having a function such as a calendar and a timer circuit 13 for giving a timer function to the CPU 1 are connected.

Further, in FIG. 1, reference numeral 14 denotes a bus controller that controls the path states of the buses 8b and 9b on the physical address side and the peripheral buses 8c and 9c. (Phase-Locked Loop) circuit and CPU 1 inside the chip and each circuit block A clock generation circuit that generates the clock signal required for clock operation, 16 is a watchdog timer for detecting hardware errors, and 17 is a peripheral bus 8c via the external interface circuit 10 , 9c and external bus enable 1 の port, 18 can execute program at any point (instruction or address) to support system debugging during user system development This is a break controller that provides a function to stop.

The CPU 1 and circuit blocks (2 to 7, 10 to 18 and SPF) and buses (8a to 8c, 9a to 9c) shown in Fig. 1 are similar to single-crystal silicon substrates. It is formed on one semiconductor chip 100. In addition, although not particularly limited, in this embodiment, when the external main memory is constituted by DRAM (dynamic 'random'access' memory), the refresh controller for performing the refresh operation is as described above. Built in the external bus interface circuit 10. FIG. 2 shows a specific configuration example of the CPU 1. In FIG. 2, reference numeral 20 denotes a program counter indicating the address of an instruction to be executed, and 21 denotes a 32-bit instruction code for holding an instruction code fetched from the cache memory 6 or an external main memory via a data bus 9a. 22 is an instruction decoder that decodes the instruction code fetched into the instruction register 21 to generate a control signal, and 23 is a general-purpose register that holds data before operation and data after operation. REG1 to REGn, adder / subtractor ALU for performing address operation, data addition / subtraction, and logical operation, barrel shifter SFT for performing data bit shift, address output register ADR, data input / output register DTR, etc. . Arithmetic buses BUS 1, 2, and 3 are provided in the instruction execution circuit 23. The arithmetic buses BUS 1, 2, and 3 provide the above registers REG1 to REGn, ADR, DTR, adder / subtractor ALU, and barrel shifter. The connection between the SFTs is enabled and the gates GT1 to GTm provided between each register and the bus to the arithmetic unit are sequentially controlled by the control signals CS1 to CSi output from the instruction register 22. Thus, data processing corresponding to the instruction is executed. However, CPU 1 If the instruction fetched into the instruction register 22 is determined to be a dedicated instruction for the FPU (coprocessor) 2, the execution of the instruction is left to the FPU 2, and the processor itself shifts to a standby state or execution of the next instruction.

In CPU 1, status register SR to reflect internal control status, etc., status register SR to save the contents of status register SR when an exception occurs Status register SSR to save contents of program counter 20 when an exception occurs Control register consisting of registers such as SPC, base address register GBR that stores the base address in indirect addressing mode, and vector address register VBR that stores vector addresses for exception processing and interrupt processing. The status of each bit is read / written by the output from the instruction decoder 22, and the execution contents of the instruction are controlled according to the status of a predetermined bit in the control register 24. You. FIG. 3 shows a specific configuration example of the FPU 2. As shown in Fig. 3, the FPU 2 is composed of multiply-accumulators 910, 911, 912, and 913, each capable of performing a matrix product of the register section 901 and 4x4, and four latches corresponding to each accumulator. An arithmetic unit 900 comprising circuits 920, 921, 922, 923 and a latch circuit 924 common to the accumulator, and an arithmetic control unit 990 for controlling the arithmetic unit 900 according to an instruction. . Although not shown, the arithmetic control unit 990 includes an instruction register and an instruction decoder similar to the CPU 1, and the instruction fetched into the instruction register is a dedicated instruction of its own (the first matrix operation instruction and the second matrix operation instruction). Command, etc.), a control signal to the arithmetic unit 900 is formed to execute the corresponding arithmetic processing. The instruction register and the instruction decoder of the FPU 2 can be configured to be shared with the instruction register and the instruction decoder of the CPU 1. FIG. 4 shows a configuration example of the accumulators 910 to 913. Each accumulator comprises a multiplier 960, an adder 961 and a temporary register 962. The multiplier 960 performs an operation for multiplying 16-bit data supplied from the signal lines 940 and 944. The adder 96 1 is used to calculate the operation result of the multiplier 960 and the temporary register 962. The sum with the held data is stored, and the resulting value is stored in the temporary register 962 to update the content. Since the temporary register 962 needs to be set to 0 before the product-sum operation, a signal line 937 for supplying “0” as an initial value and a selector 963 are provided in this embodiment. The selector 963 is configured to select an initial value “0” and to supply a control signal via the signal line 935 to be stored in the temporary register 962 before starting the operation. FIG. 5 shows a specific configuration of the register section 901. The register section 901 is composed of four register files 500, 501, 502, 503 and selectors (selectors) 55, 55, 51 corresponding to the latch circuits 920, 921, 922, 923, 924. Each of the register files 500, 501, 502, and 503 has 16 registers each, and these registers have four sub-registers. Has been split into files. For example, the registry file 500 has subfiles 5110, 511, 512, and 513 consisting of four registers.

Four registers are arranged in each subfile, and a selector 516 for specifying the subfile is provided. Registers 0, 4, 8, and 12 are assigned to subfile 5 11, and registers 1, 5, 9, and 13 are assigned to subfile 5 12. Therefore, 16 registers 0 to 15 can be identified by a register number code consisting of a 4-bit binary number. Reference numeral 936 denotes a signal line for supplying a control signal for giving write permission to the register file, and reference numeral 950 denotes a common signal line for supplying write data to the register file. Each of the above subfiles is configured so that data can be read from two registers and data can be written to one register at the same time. Therefore, the upper 2 bits of the 4-bit register number code for specifying the register via the signal lines 930, 931, and 932 are input to the subfile. For example, in the case of a subfile 510, data read from the register specified by the selection signal supplied via the signal line 930 is sent to the selector 550, and the data is read via the signal line 934. Register data according to the register file selection signal supplied Is selected.

 The data read from the register corresponding to the selection signal (high-order 2 bits of the register number code) supplied via the signal line 931 is sent to the selector 5 16 and the signal line 9 3 The register data corresponding to the selection signal (lower 2 bits of the register number code) supplied via 3 is selected. The write data sent via the signal line 950 is stored in the register corresponding to the selection signal supplied via the signal line 932 if the signal on the signal line 9336 permits writing. Written. Properties of matrix products

 Next, before explaining the two-dimensional discrete cosine transform and the two-dimensional inverse discrete cosine transform by the microprocessor of the present invention, first, the property of the matrix product that provides a basis for the conversion method according to the present invention to be effective for speeding up. explain.

 Assume that an 8 × 8 matrix M is defined by (Equation 1) in FIG. This matrix M is a matrix related to the inverse discrete cosine transform, and this matrix can be obtained by replacing some rows and columns of the matrix of the discrete cosine transform.Hereinafter, the present invention will be described using the matrix itself. I will. Now, it is assumed that the 4 × 4 matrices A and C are defined by (Equation 2) and (Equation 3) in FIG. Then, the matrix M can be expressed as (Equation 4) in Fig. 6.

 Assume that an 8 × 8 matrix X is defined by (Equation 2-1) in FIG. This matrix X is divided into four, and each of the submatrices XI, X2, X3, and X4 is represented by (Equation 2-2), (Equation 2-3), (Equation 2-4), (Equation 2-5) Then, the matrix X can be expressed by (Equation 2-6).

 Next, FIG. 8 is a diagram for illustrating a definition expression of the discrete cosine transform and a calculation method when it is decomposed into a 4 × 4 submatrix. (Equation 3-1) is the definition of the discrete cosine transform. (Equation 3-2) expresses the 8 × 8 matrix appearing in (Equation 3-1) by decomposing it into a 4 × 4 submatrix. The matrix M in (Equation 3-1) is replaced by the side of (Equation 4), and the matrix X in (Equation 3-1) is replaced by the right side of (Equation 2-6). Then, when this (Equation 3-2) is expanded, it becomes (Equation 3-3), (Equation 3-4), and (Equation 3-5).

Also, the symbols of (Equation 3-6) to (Equation 3-9) are attached to the four types of terms appearing in (Equation 3-5). Then, the inverse discrete cosine transform can be calculated by (Equation 3-10). Here, the above (Equation 3-10) is slightly processed. FIG. 9 is a diagram for explaining the processing. First, the individual elements of the 4X4 matrices Tl, T2, T3, and T4 appearing in (Equation 3-10) in Fig. 8 are marked with symbols according to (Equation 4-1) to (Equation 4-4). Then, using these symbols, a 4X16 matrix T is defined by (Equation 4-5). Also, a 4 × 4 constant matrix B is defined by (Equation 4-6). Then, the product TB (4x16 matrix) of T and B is defined as matrix S, that is, S = TB.

 Now, mark each of the 64 elements of the matrix S according to (Equation 4-7). Then, an 8 × 8 matrix expressed as shown in FIG. 9 (Equation 4-8) using these symbols is defined as Y. Then, Y defined by (Equation 4-8) and Y defined by (Equation 3-10) in Fig. 8 are the same. For example, the upper left element of the 8 × 8 matrix Y defined by (Equation 3-10) in FIG. 8 is a 4 × 4 matrix Tl, T2, T3 defined by (Equation 4-1) to (Equation 4-4) , Top left element of each of T4

tlO, t20, t30, t40 are added. On the other hand, since the upper left element of the 8 × 8 matrix Y defined by (Equation 4-8) in FIG. 9 is S = TB, the first row (1 This is the inner product of 1 1 1) and the first line (tlO t20 t30 t40) on the right side of T (Equation 4-5), and is specifically as follows:

 Ixtl0 + ixt20 + ixt30 + ixt40 = tl0 + t20 + t30 + t40

The same applies to other elements. Therefore, it can be seen that Y defined by (Equation 4-8) in FIG. 9 is the same as Y defined by (Equation 3-10) in FIG. Regis evening file and instruction format

 Next, the configuration of the register file and the instruction format of the hardware configuration required for the present invention will be described. The processor to which the present invention is applied has at least three sets of register files composed of 16 registers. Figure 10 shows a case where there are four sets of register files RFL0, RFL1, RFL2, and RFL3. Note that the register numbers added to the left side of FIG. 10 are shown in the subfiles 5110 to 513 in FIG. 5, and the correspondence between the register numbers in the register files in FIG. 5 and FIG. 10 is shown. Represents a relationship. Further, the processor to which the present invention is applied has two types of instructions for performing a matrix product of a 4 × 4 matrix and a vector having 4 elements. The instruction shall be described as follows.

 TRV m, n, s, d (matrix operation instruction of the first kind)

TRVT m, n, s, d (matrix operation instruction of the second kind) P TJP97 / 02708

12 The instruction format is, for example, as shown in FIG. 11, an instruction code field I CF in which an instruction code is stored, and four fields OP F l, OP F in which operands m, s, d, and n are stored. 2, OP F 3, 〇 PF 4. Of these operands, m, s, and d are numbers that specify the registry file. Also, n is a number that specifies a register in the register file, and is a multiple of 4 (0, 4, 8, 12). In other words, n is a 4-bit code, the lower 2 bits of n specify the subfile in Figure 5, and the upper 2 bits specify the register in the subfile. Always set to 0). Next, the function of the type-1 matrix operation instruction TRV will be described first. The function of the TRV instruction is defined by (Equation 5-1) in Figure 12. That is, the group value of 16 registers in the register file m is regarded as a 4 × 4 matrix, and the value group of the registers n, n + 1, n † 2, n + 3 in the register file s is divided into four elements. Treat as a vector, multiply the matrix by the vector, and store the result in registers n, n + 1, n + 2, n + 3 in register file d. In other words, the operands are extracted one by one from the four subfiles in Fig. 5, and the operation results are stored in the four subfiles. In the register file of Figure 10, vectors are read from four consecutive registers and the results are stored in the corresponding four registers _; therefore, the following instruction:

 TRV 0, 0, 1, 2

 The calculation of (Equation 5-2) in FIG. 12 is performed. Also, the following instruction sequence,

 TRV 0, 0, 1, 2

 TRV 0, 4, 1, 2

 TRV 0, 8, 1, 2

 TRV 0, 12, 1, 2

Then, the operation of (Equation 5-3) in Fig. 12 is performed, and the 4X4 matrix and the 4X4 matrix as shown on the right side are multiplied, and as a result, the 4X4 matrix as shown on the left side is obtained. It will be. Next, the function of the second type matrix operation instruction TRVT will be described. The function of the TRVT instruction is defined by (Equation 5-4) in Figure 12. T used in (Equation 5-4) is the value of the above operand n consisting of a 4-bit code, shifted right by 2 bits. The upper two bits of t are 00. The matrix operation instruction of the second kind TRVT m, n, s, d regards the 16 registers in the register file m as a 4 × 4 matrix, and registers t, 4 + t, 8 + t, is regarded as a four-element vector, the matrix is multiplied by the vector, and the result is stored in the registers n, n + 1, n + 2, n + 3 in the register file d. In other words, the vector to be operated on takes the values of the four registers in one of the four subfiles in Fig. 5, and distributes the operation results to the corresponding registers of the four subfiles. Is stored. In the register file shown in Fig. 10, the values of every four registers out of 16 registers are read out as vector operands, and the results are stored consecutively in the specified register file. It is stored in four registers (the first one has a number that is a multiple of four).

 Therefore, if

 TRVT 0, 0, 1, 2

The calculation of (Equation 5-5) in FIG. 12 is performed. And the following instruction sequence:

 TRVT 0, 0, 1, 2

 TRVT 0, 4, 1, 2

 TRVT 0, 8, 1, 2

 TRVT 0, 12, 1, 2

Then, the operation of (Equation 5-6) in FIG. 12 is performed, and a 4 × 4 matrix is multiplied by a 4 × 4 matrix to obtain a 4 × 4 matrix as a result. It should be noted here that in (Equation 5-3) and (Equation 5-6), the matrix of the preceding term on the right side is transposed by (Equation 5-3) and (Equation 5-6), that is, ( The ordering of the values in the row direction of the matrix in the preceding term of Equation 5-3 is the same as the ordering of the values in the column direction of the matrix in the preceding term of (Equation 5-6). The arrangement of the value groups in the column direction of the matrix of is the same as the arrangement of the value group in the row direction of the matrix in the preceding section of (Equation 5-6).

This is achieved by using the two instructions TRU and TRUT without changing the order of the values stored in the register file, that is, without reloading from memory into the register file (Equation 5-3). ) And (Equation 5-6) Means you can do it. As a result, the number of image data calculations for the inverse discrete cosine transform according to (Equation 3-10) can be significantly reduced compared to the case where the TRU.TRUT instruction is not used.

 Note that executing the inverse discrete cosine transform according to (Equation 3-10) also requires instructions to load and store data from main memory to a register file, which is also used in conventional microprocessors. It is assumed that the following instructions are provided.

 LD4 b + disp, d, n

 ST s, n, b + disp

Here, the instruction indicated by LD4 is used to store four data from the address (in this embodiment, one of the main memory addresses) separated from the base address b by the displacement value disp (the address in the main memory). This is an instruction to load the register group n, n + l, n + 2, n + 3 in d. The instruction indicated by ST is an instruction to store the register n in the register file s from the base address b to an address (in the embodiment, any address in the main memory) separated by the displacement value disp. It is. Instruction execution procedure

 Next, a procedure when the control unit 990 of FIG. 3 executes the first type matrix operation instruction TRV m, n, s, d will be described.

 In the first step, the control unit 990 first sends “00” as a 2-bit binary code to the subfiles 510 to 513 of each of the registry files 500 to 503 via the signal line 930. In response, the subfiles 510 to 513 select the contents of register 0 to selector 550, the contents of register 1 to selector 551, and the contents of register 2 respectively. Send register 3 contents to selector 5 53 to child 5 52. Then, control unit 990 sends number m designating the register file to signal line 934. Then, the data specified by m passes through the selectors 550 to 553 and is latched by the latches 92 0, 92 1, 922, 923 (that is, the contents of registers 0, 1, 2, and 3 of the register file m are Latch 9 20, 92 1, 922, 923).

Further, the control unit 990 outputs a signal given as a 4-bit code through the signal line 931. The upper 2 bits of the disk number n are sent to each register file. In response, each register file sends the contents of the register corresponding to the upper two bits of n to the selector 516. Further, control unit 990 sends the lower two bits of n to selector 5 16 via signal line 933. Then, the selected data passes through the selector 5 16 and is sent to the selector 5 5 4. Then, control unit 990 sends number s specifying the register file to signal line 935. Then, the data specified by s passes through the selector 554 and is latched by the latch 924. At the same time, the control unit 990 controls the selector 963 via the signal line 935 so that the initial value “0” is set in the temporary register 962. In the second step, the contents of the latches 920, 921, 922, 923 are sent to the corresponding integrators 910, 911, 912, 913, respectively, and the contents of the latches 924 are read out. To the three accumulators 9 1 0, 9 1 1, 9 1 2, 9 13 Then, the first sum of products is performed in each of the accumulators 910 to 913, and the result is temporarily set in the register 962 or the like. At this time, the binary code “01” is sent to each of the register files 500 to 503 via the signal line 930 at the same time. In response, each register file sends the contents of register 4 to selector 5 50, the contents of register 5 to selector 5 51, the contents of register 6 to selector 5 52, and the contents of register 7 respectively. Send the content to selector 5 53. Then, control unit 990 sends number m designating the register file to signal line 934. Then, the data specified by m passes through the selectors 550 to 553 and is latched by the latches 920, 921, 922, and 923. Further, the control unit 990 sends the upper 2 bits of the value n + 1 obtained by incrementing (+1) the 4-bit register number n via the signal line 931 to each of the register files 500 to 503.

 In response, each register file sends the contents of the register corresponding to the upper two bits of n + 1 to the selector 5 16. Further, control section 990 sends the lower two bits of n + 1 to selector 5 16 via signal line 933. Then, the selected data passes through the selector 516 and is sent to the selector 554. Then, control unit 990 sends number s designating the register file to signal line 934. Then, the data specified by s passes through the selector 554 and is latched by the latch 924.

The operation of the third step is the same as the operation of the second step, except that The difference is that 4, 5, 6, 7 becomes 8, 9, 10, 1 1 and the 4-bit register number n11 becomes n + 2.

 The operation of the fourth step is the same as the operation of the second step, except that the register numbers 4, 5, 6, 7 are 12, 13, 14, 1 5 and the 4-bit register number n 10 1 is The difference is that n + 3.

 The fifth step is a step of writing back the four values latched in the accumulators 9, 10, 91 1, 9 12, 913 to the register section 901. The value latched by the accumulator 910 or the like is sent to the register unit 901 via the signal line 920 or the like. The control unit 990 sends the upper 2 bits of the 4-bit register number n to each subfile via the signal line 932. Further, writing to the register file corresponding to the operand "d" is permitted via the signal line 936. The four values are then set in the four subfiles of the register file specified by "d". With the above operation, the operation defined by (Equation 5-1) is performed. Next, a case where the control unit 990 of FIG. 3 executes the following type 2 matrix operation instruction TRVT m, n, s, d will be described.

 In the first step, the control unit 990 first sends a binary code “00” to each registry file via a signal line 930. In response, each register file selects the contents of register 0 to selector 550, the contents of register 1 to selector 55 1, the contents of register 2 to selector 552, and the contents of register 3 respectively. Send to child 553. Then, control unit 990 sends number m designating the register file to signal line 934. Then, the data specified by m passes through the selectors 550 to 553 and is latched by the latches 920, 921, 922, and 923. The control unit 990 sends the lower 2 bits of the 4-bit register number n to each register file via the signal line 931 (note that the upper 2 bits are used in the TRV instruction). In response, each register file sends to register 516 the contents of the register corresponding to the lower two bits of n.

Further, control unit 990 sends the upper two bits of register number n to selector 516 via signal line 933. Then, the selected data passes through the selector 516 and is sent to the selector 554. , And the control unit 990 specifies the registration file. Number s to signal line 935. Then, the data specified by s passes through the selector 554 and is latched by the latch 924. At the same time, the control unit 990 controls the selector 963 via the signal line 935 so that the initial value “0” is set in the temporary register 962.

 In a second step, the contents of latches 920, 921, 922, 923 are sent to accumulators 910, 911, 912, 913, respectively. The contents of the latch 924 are sent to the four accumulators 910, 911, 912, and 913. Then, the first sum of products is performed in each accumulator, and the result is set in the temporary register 962 or the like. At the same time, the binary code "01" is sent to each register file via signal line 930. In response, each register file selects the contents of register 4 to selector 5 50, the contents of register 5 to selector 551, the contents of register 6 to selector 552, and the contents of register 7 respectively. Send to child 553. Then, control unit 990 sends number m designating the registration file to signal line 934. Then, the data specified by m passes through selectors 550 to 553 and is latched by latches 920, 921, 922, and 923. Also, the lower two bits of register number n + 1 are sent to each register file via signal line 931. In response, the individual register file sends to register 516 the contents of the register corresponding to the lower two bits of register number n + 1. Further, the upper two bits of the register number n + 1 are sent to the selector 516 via the signal line 933. The selected data then passes through selector 516 and is sent to selector 554. Then, control unit 990 sends number s designating the register file to signal line 935. Then, the data specified by s passes through the selector 554 and is latched by the latch 924.

 The operation of the third step is the same as that of the second step, except that the register numbers 4, 5, 6, 7 are 8, 9, 10, 11 and the 4-bit register number n + 1 is The difference is that n + 2.

 The operation of the fourth step is the same as that of the second step, except that the register numbers 4, 5, 6, and 7 are 12, 13, 14, 15, and the 4-bit register number n + 1 is n + 3. Is different.

The fifth step consists of four products latched in the accumulator 9 10, 9 1 1, 912, 9 13 PC first 97/02708

This is the step of writing back the value of 18 to the register section 91. The value latched by the accumulator 910 or the like is sent to the register section 901 via the signal line 920 or the like. The control unit 990 sends the upper two bits of the register number n to each subfile via the signal line 932. Further, writing to the register file corresponding to the number d is permitted via the signal line 936. Then the four values will be set in the four subfiles of the register file with number d. With the above operation, the operation defined by (Equation 5-4) is performed. Data required for inverse discrete cosine transform

 Next, the data necessary for the inverse discrete cosine transform is organized. These data are stored in the external main memory MEM in the arrangement shown in Fig. 13 when viewed from the conversion program.

 First, data to be converted (DCT coefficients) is required, which is stored in storage areas indicated by X1T, X2T, X3T, and X4T in the main memory in FIG. The constant matrices (corresponding to the DCT basis) required for the transformation are related to (Equation 2), (Equation 3), and (Equation 4-6). Each is stored in the indicated storage area. Then, the conversion result is stored in the storage area indicated by Y in FIG. Inverse discrete cosine transform

 The inverse discrete cosine transform may be performed by sequentially performing (Equation 3-6), (Equation 3-7), (Equation 3-8), (Equation 3-9) (Equation 3-10) in FIG.

 To execute (Equation 3-6), load X1 T in Figure 13 into register file 0 with four LD4 instructions, load AT in Figure 13 into register file 1 with four LD4 instructions, The result corresponding to A Xlt in (Equation 3-6) is obtained in register file 2 by one TRVT instruction, and the result corresponding to the right-hand side of (Equation 3-6) is obtained in register file 2 by four TRV instructions. And finally store it in T in Fig. 13 with 16 ST instructions. This can be done with the following sequence of instructions.

 LD4 X1 T + 0, 0, 0

 LD4 X1 T + 4, 0, 4

LD4 X1 T + 8, 0, 8 LD4 X1T + 12, 0, 12

 LD4 (O) AT, 1, 0

 LD4 (4) AT, 1, 4

 LD4 (8) AT, 1, 8

 LD4 (12) AT, 1, 12

 TRVT 0, 0, 1, 2

 TRVT 0, 4, 1, 2

 TRVT 0, 8, 1, 2

 TRVT 0, 12, 1, 2

 TRV 1, 0, 2, 2

 TRV 1, 4, 2, 2

 TRV 1, 8, 2, 2

 TRV 1, 12, 2, 2

 ST 2, 0, T + 0

 ST 2, 1, T + 4

ST 2, 15 + 60

 To execute (Equation 3-7), load the X2T shown in Figure 13 into the register file 0 with four LD4 instructions, and use four TRVT instructions to correspond to A Xlt in (Equation 3-6). The result is obtained in register file 2, the result corresponding to the right side of (Equation 3-6) is obtained in register file 2 by four TRV instructions, and finally stored in T in Fig. 13 by 16 ST instructions. I should go. As in the case of (Equation 3-6), execution can be performed in the instruction sequence, so a specific example of the instruction sequence is omitted. Note that the loading of the AT has been omitted here.

 A specific description for executing (Equation 3-8) and (Equation 3-9) is omitted. However, it should be pointed out that it is more efficient to calculate (Equation 3-9) first because the number of AT and CT loads can be reduced.

To execute (Equation 3-10), first load B in Figure 13 into register file 0 with four LD4 instructions. Next, four lines of data from T in Fig. 13 are loaded into register file 1 by four LD4 instructions, and one-fourth of the right-hand side of (Equation 3-10) is calculated by four TRV instructions. Execute and store the result to Y in Figure 13 with 16 ST instructions. This can be repeated three more times. The first quarter of the instruction sequence looks like this:

 LD4 Β + 0, 0, 0

 LD4 Β + 4, 0, 4

 LD4 Β + 8, 0, 8

 LD4 B + 12, 0, 12

 LD4 Τ + 0, 0, 0

 LD4 Τ + 4, 0, 4

 LD4 Τ + 8, 0, 8

 LD4 TI12, 0, 12

 TRV 0, 0, 1, 1

 TRV 0, 4, 1, 1

 TRV 0, 8, 1, 1

 TRV 0, 12, 1, 1

 ST 1, 0, Υ + 0

 ST 1, 0, Υ + 4

 ST 1, 2, Υ + 32

 ST 1, 3, Υ + 36

 ST 1, 4, Y + 1

 · · · ·

 ST 1, 15, Υ + 39

The remaining 34 instruction sequences are omitted. The invention's effect

 The inverse discrete cosine transform can be executed by the above, but from (Equation 3-6)

1 12 instructions, 100 instructions to execute (Equation 3-10), for a total of about 200 instructions. In the conventional inverse discrete cosine transform, which used to take 1000 to 2000 instructions, the application of the present invention requires only about 200 instructions, indicating that the inverse discrete cosine transform process can be made much more efficient. PC first 97/02708

21 The reason why the number of instructions could be significantly reduced in this way is to prepare instructions TRV and TRVT for performing matrix multiplication and configure and control the arithmetic circuit of the coprocessor so that parentheses can be executed efficiently. It is in the point which was made. Also noteworthy are the functions related to the transpose of the TRVT instruction. To calculate (Equation 3-1) naively, it is necessary to calculate the transpose matrix after calculating the expression M X in parentheses. However, the TRVT instruction provides a function to simultaneously perform the process of creating a transposed matrix and the process of performing a matrix product, which further improves the performance improvement. It is also necessary to note that the At used in the register file is used twice using the TRVT instruction. In the above embodiment, instead of directly calculating (Equation 3-1), (Equation 3-6), (Equation 3)

3-7), (Equation 3-9), (Equation 3-8), and (Equation 3-10) were calculated sequentially, but it is also possible to calculate using other procedures.

 In the above description, the inverse discrete cosine transform is mainly described as an example. However, the present invention can be applied to the discrete cosine transform. Figure 14 shows the definition of the discrete cosine transform and the expanded form of the definition by decomposing it into submatrices. After all, (Equation 6-6) to (Equation 6-10) should be calculated sequentially. At this time, the number of executed instructions can be significantly reduced by effectively utilizing the TRV and TRVT instructions described in the above embodiment.

 Further, in the above embodiment, the case where four register files are provided has been described. However, the TRU instruction and the TRUT instruction according to the present invention include at least three register files 500, 50 as shown in FIG. It can be executed by a coprocessor having a register section composed of 1,502 and an arithmetic circuit as shown in FIG.

Further, in the above embodiment, the discrete cosine transform and the inverse discrete cosine transform by the coprocessor have been described. However, in a coprocessor having an arithmetic circuit having a configuration as shown in FIG. It is possible to perform an operation. Further, in the microprocessor according to the embodiment, a case where a coprocessor (second processor) 2 for performing a matrix operation and a floating-point operation is provided separately from a central processing unit (first processor) 1 has been described. It is also possible to configure so that the functions of one processor are realized by one processor. Industrial applicability

 In the above description, the case where the invention made by the present inventor is mainly applied to a general-purpose microprocessor has been described. However, the present invention is not limited to this case. It can be widely used in data processing equipment that performs matrix multiplication.

Claims

The scope of the claims  1. It is characterized by comprising an instruction consisting of an instruction code, first, second and third operands for specifying a register file and a fourth operand for specifying a register in the register file. Data processing device. 2. The NXN matrix in the first register file specified by the first operand and the number of register elements N specified by the fourth operand in the second register file specified by the second operand The instruction according to claim 1, further comprising an instruction for performing a matrix multiplication with the input vector and storing the resultant output vector in a third register file specified by the third operand. Data processing device. 3. The register group selected by the register number n in the fourth operand for designating a vector is provided with different instructions for the input vector and the output vector. The data processing device according to claim 1.  4. The matrix operation instruction is a first matrix operation instruction in which a register group selected by the register number n in the fourth operand for designating an input vector is in the row direction of the matrix, and the register number is 4. The data processing device according to claim 2, wherein the register group selected by n includes a second matrix operation instruction in a column direction of the matrix.  5. A data processing device that performs at least inverse discrete cosine transform using the instruction according to claim 1, 2, 3, or 4.  6. A control means for forming a control signal corresponding to the read instruction, and at least three register files including a predetermined number of registers and an arithmetic unit, and a matrix product is formed by the control signal from the control means. Computing means capable of executing processing corresponding to each of a plurality of instructions including a matrix operation instruction to be executed,  The above matrix operation instruction is composed of an instruction code, first, second, and third operands for specifying a register file and a fourth operand for specifying a register in a register file. Characteristic data processing device. 7. The NXN matrix in the first register file specified by the first operand and the number of elements N of the register specified by the fourth operand in the second register file specified by the second operand Performs a matrix product with the input vector of 7. The data processing apparatus according to claim 6, further comprising an instruction for storing a power vector in a third registry file specified by the third operand.  8. The register group selected by the register number n in the fourth operand for designating a vector is provided with different instructions for an input vector and an output vector. Data processing equipment.  9. The matrix operation instruction includes: a first matrix operation instruction in which a group of registers selected by a register number n in the fourth operand for designating an input vector is in a row direction of the matrix; 9. The data processing device according to claim 7, wherein the register group selected by the number n includes a second matrix operation instruction in a column direction of the matrix.  10. The arithmetic means includes at least three register files each including 16 registers, four selected data in the first register file specified by the first operand, and the Four multipliers that take the product of the data in the register specified by the fourth operand in the second register file specified by the two operands, and the operation results of these multipliers and the result of the previous addition 10. The data processing as claimed in claim 7, comprising four adders for calculating the sum of the data and four temporary registers for holding the operation results of these adders. apparatus.  1 1. A control means for forming a control signal corresponding to the read instruction, and a command having a register and an arithmetic unit and capable of executing a process corresponding to each of the above-mentioned instructions by a control signal from the control means. A first processor unit having an execution unit, a control unit for forming a control signal corresponding to the read instruction, and at least three registry files including a predetermined number of registry files and a computing unit, A second processor unit comprising: an operation unit capable of executing processing corresponding to each of a plurality of instructions including a matrix operation instruction for executing a matrix product by a control signal from the control unit; A data processing device characterized in that a matrix operation instruction is supplied to both the first and second processor units and is configured to be executed by a second processor. 1 2. A data processing method for reading a command into a control means to form a control signal, and supplying the control signal to an execution means to execute a process corresponding to the command. It is composed of an instruction code, first, second and third operands for specifying a register file and a fourth operand for specifying a register in a register file. The matrix product of the NXN matrix in the first register file and the input vector of the number of elements N of the register specified by the fourth operand in the second register file specified by the second operand specified in the second operand file is calculated. Prepare two types of instructions to store the output vector of the result in the third register file specified by the third operand.  In one matrix operation instruction, the register group selected by the register number n in the fourth operand for designating the input vector is in the row direction of the matrix, and the other matrix operation instruction is in the register number n A data processing method characterized in that a register group selected by the above is arranged in a column direction of a matrix.  13. The other matrix operation instruction is characterized in that a register group selected by a register number n in the fourth operand for specifying a vector is different between an input vector and an output vector. 13. The data processing method according to claim 12, wherein