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WO1999004335A3 - A method and a processor adapted for the handling of conditional jumps - Google Patents

A method and a processor adapted for the handling of conditional jumps Download PDF

Info

Publication number
WO1999004335A3
WO1999004335A3 PCT/SE1998/001334 SE9801334W WO9904335A3 WO 1999004335 A3 WO1999004335 A3 WO 1999004335A3 SE 9801334 W SE9801334 W SE 9801334W WO 9904335 A3 WO9904335 A3 WO 9904335A3
Authority
WO
WIPO (PCT)
Prior art keywords
read
processor
instructions
handling
fulfilment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/SE1998/001334
Other languages
French (fr)
Other versions
WO1999004335A2 (en
Inventor
Carl Tobias Roos
Lars-Erik Lundstroem
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Priority to BR9810768-2A priority Critical patent/BR9810768A/en
Priority to KR1020007000634A priority patent/KR20010022065A/en
Priority to AU83652/98A priority patent/AU8365298A/en
Priority to JP2000503482A priority patent/JP2001510916A/en
Priority to EP98934048A priority patent/EP0998701A2/en
Publication of WO1999004335A2 publication Critical patent/WO1999004335A2/en
Publication of WO1999004335A3 publication Critical patent/WO1999004335A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

The present invention relates to a method of handling conditional jump instructions in a computer processor (1). Space is allocated in a so-called instruction buffer (3) for respective instructions read into the processor. These spaces are given an order which corresponds to the order in which the instructions were read-in sequentially. The last position in the instruction buffer constitutes a read-out position (4). The processor (1) is adapted to predict the fulfilment of a conditional jump instruction when such a jump instruction is read-in, whereafter instructions can be read into and processed by the processor in accordance with this prediction. A wrong prediction will result in following instructions read into the processor and partially processed thereby being removed from the processor (1) so as to provide space for the read-in of correct instructions, in accordance with fulfilment of the condition.
PCT/SE1998/001334 1997-07-21 1998-07-07 A method and a processor adapted for the handling of conditional jumps Ceased WO1999004335A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
BR9810768-2A BR9810768A (en) 1997-07-21 1998-07-07 Process of handling specific instructions, and, processor
KR1020007000634A KR20010022065A (en) 1997-07-21 1998-07-07 A method and a processor adapted for the handling of conditional jumps
AU83652/98A AU8365298A (en) 1997-07-21 1998-07-07 A method for handling conditional jump instructions in a data processor
JP2000503482A JP2001510916A (en) 1997-07-21 1998-07-07 Processing method of conditional jump instruction in data processor
EP98934048A EP0998701A2 (en) 1997-07-21 1998-07-07 A method for handling conditional jump instructions in a data processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9702762A SE510295C2 (en) 1997-07-21 1997-07-21 Processor method for handling conditional jump instructions and processor adapted to operate according to the specified method
SE9702762-7 1997-07-21

Publications (2)

Publication Number Publication Date
WO1999004335A2 WO1999004335A2 (en) 1999-01-28
WO1999004335A3 true WO1999004335A3 (en) 1999-04-08

Family

ID=20407793

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE1998/001334 Ceased WO1999004335A2 (en) 1997-07-21 1998-07-07 A method and a processor adapted for the handling of conditional jumps

Country Status (8)

Country Link
EP (1) EP0998701A2 (en)
JP (1) JP2001510916A (en)
KR (1) KR20010022065A (en)
CN (1) CN1271434A (en)
AU (1) AU8365298A (en)
BR (1) BR9810768A (en)
SE (1) SE510295C2 (en)
WO (1) WO1999004335A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7281120B2 (en) * 2004-03-26 2007-10-09 International Business Machines Corporation Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor
US9952869B2 (en) 2009-11-04 2018-04-24 Ceva D.S.P. Ltd. System and method for using a branch mis-prediction buffer
EP2367102B1 (en) 2010-02-11 2013-04-10 Nxp B.V. Computer processor and method with increased security properties

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1987004821A1 (en) * 1986-01-29 1987-08-13 Digital Equipment Corporation Apparatus and method for execution of branch instructions
US4755935A (en) * 1986-01-27 1988-07-05 Schlumberger Technology Corporation Prefetch memory system having next-instruction buffer which stores target tracks of jumps prior to CPU access of instruction
US5121473A (en) * 1987-12-05 1992-06-09 International Computers Limited Pipelined system includes correction mechanism operated on history information identifying conditional jump instructions for which the jump prediction was incorrect on previous instances of execution of those instructions
WO1997042567A1 (en) * 1996-05-03 1997-11-13 Telefonaktiebolaget Lm Ericsson (Publ) Method relating to handling of conditional jumps in a multi-stage pipeline arrangement

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755935A (en) * 1986-01-27 1988-07-05 Schlumberger Technology Corporation Prefetch memory system having next-instruction buffer which stores target tracks of jumps prior to CPU access of instruction
WO1987004821A1 (en) * 1986-01-29 1987-08-13 Digital Equipment Corporation Apparatus and method for execution of branch instructions
US5121473A (en) * 1987-12-05 1992-06-09 International Computers Limited Pipelined system includes correction mechanism operated on history information identifying conditional jump instructions for which the jump prediction was incorrect on previous instances of execution of those instructions
WO1997042567A1 (en) * 1996-05-03 1997-11-13 Telefonaktiebolaget Lm Ericsson (Publ) Method relating to handling of conditional jumps in a multi-stage pipeline arrangement

Also Published As

Publication number Publication date
AU8365298A (en) 1999-02-10
SE9702762D0 (en) 1997-07-21
WO1999004335A2 (en) 1999-01-28
JP2001510916A (en) 2001-08-07
CN1271434A (en) 2000-10-25
SE9702762L (en) 1999-01-22
KR20010022065A (en) 2001-03-15
EP0998701A2 (en) 2000-05-10
BR9810768A (en) 2000-08-15
SE510295C2 (en) 1999-05-10

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