[go: up one dir, main page]

WO1999004335A2 - Procede de gestion d'instructions de sauts conditionnels dans un processeur de donnees - Google Patents

Procede de gestion d'instructions de sauts conditionnels dans un processeur de donnees Download PDF

Info

Publication number
WO1999004335A2
WO1999004335A2 PCT/SE1998/001334 SE9801334W WO9904335A2 WO 1999004335 A2 WO1999004335 A2 WO 1999004335A2 SE 9801334 W SE9801334 W SE 9801334W WO 9904335 A2 WO9904335 A2 WO 9904335A2
Authority
WO
WIPO (PCT)
Prior art keywords
processor
instructions
read
instruction
conditional jump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/SE1998/001334
Other languages
English (en)
Other versions
WO1999004335A3 (fr
Inventor
Carl Tobias Roos
Lars-Erik LUNDSTRÖM
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Priority to BR9810768-2A priority Critical patent/BR9810768A/pt
Priority to KR1020007000634A priority patent/KR20010022065A/ko
Priority to AU83652/98A priority patent/AU8365298A/en
Priority to JP2000503482A priority patent/JP2001510916A/ja
Priority to EP98934048A priority patent/EP0998701A2/fr
Publication of WO1999004335A2 publication Critical patent/WO1999004335A2/fr
Publication of WO1999004335A3 publication Critical patent/WO1999004335A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Definitions

  • the present invention relates to the handling of specific instructions, so-called conditional jumps, in a data processor.
  • a conditional jump instruction is comprised of one instruction from several instructions read sequentially into a processor, where fulfilment of the condition determines whether or not the instructions that immediately follow the conditioned jump instruction shall be read into the processor or whether a jump in the instruction sequence shall be made. Such a jump will mean that subsequent instructions shall be read-in from some other place in the sequence, in accordance with the conditional jump instruction.
  • Respective instructions read into the processor are allocated space in a so-called instruction buffer, these spaces being given an order which corresponds to the sequential order of the instructions. At least a last position in the instruction buffer is a read-out position.
  • the instructions read into the processor can be processed by the processor and the processing result stored in respective spaces belonging to respective instructions in the instruction buffer, from where it can be finally read from the read-out position in the sequential order.
  • the processor When a conditional jump instruction is read into the proces- sor, the processor is able to predict the fulfilment of the condition, whereafter instructions can be read into and processed by the processor in accordance with this prediction, immediately after the conditional jump instruction has been read in. A wrong prediction will result in the removal from the processor of subsequently read-in and partially processed instructions, so as to prepare a place for the read-in of correct instructions in accordance with fulfilment of the condition.
  • An instruction When reading-in an instruction, processing of the instruction and the read-out of the processed result takes place in different steps. When reading the instruction into a processor, possible processing of the instruction is prepared.
  • An instruction will normally include two operands and an operation that shall be applied to these operands.
  • the preparation of the instruction includes, among other things, a so-called "Fetch-step". This step includes fetching the operand values, since the actual instruction will often, but not always, merely contain an address to a position in a memory where the value of the operand is found.
  • the time taken to carry out a Fetch-step may vary with different instructions, depending on from where the different operand values shall be taken. This means that a first instruction that has been read-in before a second instruction will be processed after the said second instruction, due to the operand values of the second instruction being accessed more quickly than the operand values of the first instruction. Thus, the result obtained with the second instruction may be stored in the instruction buffer before the result obtained with the first instruction.
  • An instruction is processed in a part of the processor designated an arithmetical logical unit, ALU.
  • the ALU need not process the instructions in a sequential order, the ALU waiting times can be reduced, when the instruction Fetch-step takes a long time to complete.
  • condition-testing instruction It is also known to precede a conditional jump instruction with a condition-testing instruction. This instruction will ideally be positioned so far in front of the actual jump instruction as to enable the test instruction to be executed and its result received before the actual jump instruction enters the input port of the processor.
  • conditional jump instruction when the conditional jump instruction is read into the processor, the result regarding fulfilment of the condition will already be known because of the earlier execution of the condition-testing instruction, and correct instructions can be read-in immediately after the conditional jump instruction.
  • No instructions whose results can affect the condition for the conditional jump instruction may lie between the condition- testing instruction and the conditional jump instruction. Whether or not the condition-testing instruction may be placed at a sufficient distance in front of the conditional jump instruction will thus depend on whether instructions that can affect fulfilment of the condition lie close to or immediately precede the actual jump instruction.
  • processor-internal instructions the instructions handled in a processor can be divided up into two types of instructions, to-wit processor-external instructions and processor-internal instructions .
  • instructions in assembler code can be designated processor-external instructions, whereas those instructions that are obtained after the conversion of assembler code into micro-code can be designated processor-internal instructions.
  • processor-external instruction will normally form a series of processor-internal instructions upon conversion. It is also known that even when a processor-external instruction does not include a conditional jump instruction, such an instruction may, nevertheless, result in a processor-internal conditional jump instruction upon conversion from a processor- external code to a processor-internal code.
  • sequence number generator which is adapted to generate a sequence number for each instruction read into the instruction buffer.
  • Another technical problem is one of realising how a Fetch-step can be performed more quickly than with known techniques and the use of the processor improved, in the event of flushing the processor. Another technical problem is one of realising how this can be achieved without using condition-testing instructions that precede the conditional jump instruction, or a separate processor for processing conditional jump instructions.
  • Another technical problem is one of knowing how the truth or correctness of a prediction can be evaluated before the result obtained when processing the conditional jump instruction has reached the read-out position.
  • Another technical problem is one of realising how flushing of the processor can be effected in a correct manner in the event of a wrong prediction, when the result from processing the conditional jump instruction has still not reached the read- out position.
  • Yet another technical problem is one of realising how processor hardware shall be adapted to enable the truth of a prediction concerning the fulfilment of a condition to be evaluated before the result obtained when processing the conditional jump instruction has reached the read-out position and thereafter carry out correct flushing of the processor in the event of a wrong prediction.
  • Another technical problem is one of realising how a method or processor according to the present invention can be adapted so as to also make a processor more effective when handling processor-internal conditional jump instructions.
  • the present invention takes as its starting point a method of handling specific instructions, so-called conditional jump instructions, in a data processor, wherein respective read-in instructions are allocated spaces in a so-called instructions buffer, and wherein said spaces are allocated an order or sequence that corresponds to the sequential order in which respective instructions are read into the processor.
  • At least the last position in the instructions buffer consti- tutes a read-out position from the buffer.
  • the instructions are processed in the processor and the result is storable in respective spaces belonging to the instruction in the instructions buffer, and can be read-out from the read-out position in said sequential order.
  • the processor is adapted to predict the fulfilment of a conditional jump instruction read into the processor, whereafter instructions can be read into and processed by the processor in accordance with this prediction directly after reading-in the conditional jump instruction.
  • a wrong prediction results in removal from the processor of subsequent instructions read into and partially processed by said processor, so as to prepare room for reading into the processor correct instructions in accordance with fulfilment of the condition.
  • the present invention also relates to a method based on the processing of a processor-internal instruction as described above with respect to conditional jump instructions, in other words that the result obtained when checking the fulfilment of a prediction concerning a processor-internal conditional jump instruction is made available and is taken into account immediately it is clear, even though the space in the instruction buffer belonging to the processor-internal conditional jump instruction has still not reached a read-out position in the instruction buffer.
  • the present invention also takes as its starting point a processor that includes:
  • a read-in unit which is intended to read instructions into the processor from a memory containing mutually sequential instructions of which some are so-called conditional jump instructions, wherein fulfilment of the condition decides whether or not those instructions that follow sequentially immediately after the conditional jump instruction shall be read into the processor or whether a jump in the instruction sequence shall be made, this jump meaning that following instructions shall be read-in from some other place in the sequence in accordance with the conditional jump instruction;
  • an instruction buffer in which space can be allocated for respective instruction read into the processor, these spaces being allocated an order or sequence corresponded by the sequential order, wherein at least the last position in the instruction buffer constitutes a read-out position from said buffer;
  • processing unit which is constructed to process instructions read into the processor, wherein the result obtained can be stored in the instruction buffer in the space belonging to a respective instruction;
  • a prediction unit which is constructed to predict the fulfil- ment of a conditional jump instruction when the instruction is read into the processor, wherein the read-in unit is constructed to read instructions into the processor in accordance with said prediction immediately after reading-in the conditional jump instruc ion;
  • an evaluating unit which is constructed to evaluate whether or not the condition for the conditional jump instruction has been fulfilled in accordance with the prediction delivered by the prediction unit
  • an instruction removal unit which is constructed to remove from the processor those instructions which have been read into and partially processed in the processor after the conditional jump instruction if the prediction concerning the conditional jump instruction is found to be wrong.
  • the proces- sor will include a result indicating unit that is adapted to indicate when the result obtained by processing a conditional jump instruction is stored in the position for the conditional jump instruction in the instructions buffer.
  • the evaluating unit is adapted to fetch the result obtained when processing the conditional jump instruction, when this result is available in accordance with the result indicating unit, therewith enabling it to be ascer- tained whether or not the condition concerning the conditional jump instruction has been fulfilled or not in accordance with the prediction delivered by the prediction unit.
  • the instruction removal unit will be adapted to remove from the processor solely those instructions that have been read sequentially into the processor after the conditional jump instruction, irrespective of where these instructions are found in the instruction processing operation, in response to a signal from the evaluating unit that shows the prediction of the fulfilment of the condition to be wrong.
  • An inventive processor is also adapted to commence reading correct instructions into the processor immediately after the evaluating unit has delivered its result with respect to the correctness of a prediction when said prediction has been found to be wrong.
  • a processor that includes a conver- sion unit which is adapted to convert processor-external instructions to processor-internal instructions
  • the aforesaid units are also adapted to process both a processor-internal conditional jump instruction and a processor-external conditional jump instruction and to evaluate the result of such processing, in accordance with the above.
  • the instruction removal unit will be adapted to remove from the processor solely those instructions that have been given sequence numbers that are generated after the sequence number given to the conditional jump instruction, irrespective of where these instructions are found in the instruction processing operation, in response to a signal from the evaluating unit that shows the prediction of the fulfilment of the condition to be wrong.
  • Figure 1 is a schematic and highly simplified illustration of a processor.
  • Instructions in a program code can be divided mainly into two types, flow changing instructions and non-flow changing in- structions.
  • a non-flow changing instruction which is the most common occurring instruction, is an instruction referring to read, write and arithmetical operations. These operations normally include two operands, an instruction as to which operation shall be applied to the operands, and a destination address for the result of the operation.
  • Flow changing instructions change the flow of instructions and cause a jump in the program code.
  • the most common type of flow changing instruction is the so-called conditional jump or conditional jump instructions.
  • These latter instructions also include two operands and an instruction as to which operation shall be applied thereto.
  • This operation is, as a rule, a comparison between the operands, where the jump condition consists in similarity or dissimilarity between the operands.
  • conditional jump instructions no destination address is necessary, since the result from the operation is used locally in the processor to decide whether a jump shall be made in the flow or not. However, there is nothing to prevent a destination address being used.
  • Figure 1 shows a processor 1 in which eight instructions can be processed "simultaneously".
  • the instructions are read from a program memory 2 and are allocated a space in a so-called instructions buffer 3 which functions as a First In First Out (FIFO) buffer that has eight positions 31, 32, ..., 38 in the illustrated case.
  • FIFO First In First Out
  • the results obtained with respective operations are read out from the instructions buffer 3 and written-out to an intended destinations address when the instruction concerned is present in a so-called read-out position 4 in the instruction buffer, which in the illustrated case is the last position in said buffer 3.
  • processing or execution of the operation may have been carried out when the instruction was present in an earlier position in the instructions buffer.
  • a processor 1 has a double input port, i.e. two different input ports, that is to say a first input port 111 and a second input port 112, and associated first and second buffers 113 and 114 respectively, through which the instructions can be collected.
  • a processor-internal selector 12 decides from which input port the instructions shall be fetched.
  • a conditional jump instruction 21 enters the processor, for instance through the first input port 111, and when this condition has very likely been fulfilled, if it can be predicted, the instructions 22 are read-in immediately in accordance with the jump through the second input port 112, where the associated buffer 114 is filled with subsequent instructions.
  • the instructions 23 positioned after the conditional jump 21 continue to be read-in through the first input port 111 and stored in the first buffer 113.
  • the processor-internal selector 12 collects instructions from the second buffer 114 in accordance with the prediction. In the event of a wrong prediction, the correct instructions wait in the first buffer 113 and can be read into the processor after the instructions wrongly read into the processor have been flushed out.
  • the prediction of the fulfilment of a condition may be based on different algorithms, such as static or dynamic predic- tions, for instance.
  • a static prediction is a choice where it is always assumed that the condition is fulfilled or not fulfilled.
  • a prediction can also be based on dynamic processing to show how this condition has earlier been fulfilled.
  • the statistical outcome of the fulfilment of different conditions is then saved in a list and the list is updated each time a conditi- onal jump instruction is executed and is a basis for predictions as to whether or not these conditions are fulfilled. This is a dynamic prediction.
  • the present invention is not dependent on the use of one or more input ports, nor yet on the type of algorithm used to predict fulfilment of the condition.
  • the instructions being processed in the instructions buffer shall not be executed in the case of a wrong prediction. Consequently, these instructions shall be flushed away so as to enable correct instructions to be read into the instructions buffer for processing.
  • Processing of an instruction in a processor includes several different steps.
  • a first step is to convert the code that represents the input instruction to a processor-internal code.
  • This conversion takes place in a conversion unit, in the illustrated case a so-called Assembler to micro code Translator Unit (ATU) 5, which converts instructions in assemblers to instructions in machine language, whereafter the converted code is placed in the instruction buffer 3.
  • ATU 5 also includes the processor-internal selector 12 and controls the selector.
  • the space in the instructions buffer includes diverse fields, of which a part is shown in position 31 in the buffer 3. These fields include a field of operand A (OPA) 31A, a field for operand B ( OPB ) 31B, a field for the operation (ALSO) 31C and a field with the destination address for the result (DEST) 31D.
  • OPA operand A
  • OPB operand B
  • ALSO operand B
  • DEST destination address for the result
  • a second step is a so-called Fetch step, in which necessary operands are fetched from different memories Ml, M2 when these operands are not available in the instruction itself. This can take different lengths of time to perform, depending on the memory from which an operand shall be fetched.
  • Some memories may be processor-internal memories Ml and others may be memories that are positioned outside the processor M2, i.e. processor-external memories.
  • steps include execution of the instruction, wherewith the operands 31A, 31B and the instruction 31C are sent to an ALU 6 in which the instruction is executed and a result delivered to a result field 31E.
  • the next step is carried out when the position of the instruction in the instructions buffer has reached the read-out position 4, provided that the result from the ALU 6 is ready and has been delivered to the result field 31E.
  • This step is a so- called Commit or Write Back, in which the result is written to the address given by the content of the destination address field 31D.
  • the steps need not necessarily be executed sequentially, but can be carried out as soon as the Fetch-step of the instruction has been completed. This means that certain instructions can be ready for Commit even though instructions that lie se- quentially earlier in the instructions buffer have still not completed their respective Fetch steps .
  • Flushing of the processor in the event of a wrong prediction takes time to achieve and also impairs processor capacity.
  • the processor used has two input ports, there is obtained a certain safeguard that enables the preparation of those instructions that shall be read into the processor after the processor has been flushed in the event of a wrong prediction.
  • the invention is based on the concept of early jump reporting that enables the result 31E obtained when executing a conditi- onal jump instruction can be used before the conditional jump instruction has reached the read-out position 4 in the instruction buffer 3.
  • the earlier this result is known, the less harmful effect of a flushing process, therewith enabling correct instructions to be fetched in the event of a wrong prediction regarding the fulfilment of the condition.
  • the result obtained with the execution of a conditional jump instruction will be available in the processor as soon as execution of said jump instruction is completed.
  • the result of this execution is not used until the conditional jump instruction has reached the Commit position, i.e. the read-out position 4.
  • the invention is thus based on the concept of using the result obtained when executing a conditional jump instruction immediately the result becomes available.
  • flushing will concern solely certain instructions and not all of the instructions present in the processor. These instructions may have been processed to different extents in the processor. Regardless of where the instructions are found in this processing operation, all following instructions are flushed out and the capacity released for the execution of instructions that have still not reached the execution stage and that shall not be flushed from the processor.
  • a known processor will include:
  • a read-in unit here designated input port 111 with associated buffer 113, intended to read instructions into the pro- cessor from a memory 2, with said instructions being mutually sequential;
  • ALU 6 a processing unit, here designated ALU 6, which is adapted to process instructions read into the processor, whereafter the processing result can be stored in the space 313 allocated respective instructions in the buffer 3;
  • a check unit 13 which is adapted to check whether or not a processing result is found in the read-out position
  • a read-out unit 14 which is adapted to read the result from the read-out position 4;
  • a prediction unit 15 which is adapted to predict fulfilment of a conditional jump instruction when said instruction is read into the processor
  • an evaluating unit 16 which is adapted to evaluate whether the condition for the conditional jump instruction is fulfilled in accordance with the prediction delivered by the prediction unit;
  • an instruction removal unit 17 which is adapted to remove from the processor those instructions that were read into the processor and partially processed therein after the prediction concerning the conditional jump instruction has been found to be wrong.
  • the present invention particularly proposes that the processor will also include a result indicating unit 18 that is adapted to indicate when the result obtained by processing a conditi- onal jump instruction is stored in the position for the conditional jump instruction in the instructions buffer.
  • the evaluating unit 16 is adapted to fetch the result 31E obtained when processing the conditional jump instruction when this is available according to the result indicating unit 18, thereby enabling it to be ascertained whether or not the condition for the conditional jump instruction has been fulfilled or not in accordance with the prediction given by the prediction unit 15.
  • the result can thus be fetched regardless of whether the conditional jump instruction is positioned in the read-out position 4 in the buffer 3 or not.
  • the instruction removal unit 17 is adapted to remove from the processor solely those instructions that were read-in sequentially after the conditional jump instruction, regardless of where these instructions are found in the instruction processing chain, upon receipt of a signal from the evaluating unit 16 indicating that the prediction of the fulfilment of the condition was wrong.
  • processor-external instructions that do not include a conditional jump but where their correspondence in processor-internal code includes a conditional jump instruction.
  • processor-external instruc- tion that lacks conditional jump instructions and translated to a micro-code may result in a processor-internal loop that includes a conditional jump instruction, where the condition means that the loop shall be broken in fulfilling a given condition.
  • the present invention also relates to a method of hand- ling processor-internal conditional jump instructions in a data processor where the conditional jump instructions need not necessarily derive from a processor-external conditional jump instruction.
  • Fulfilment of the condition decides whether or not those instructions that follow sequentially immediately after said conditional jump instruction shall be processed by the processor or whether a jump in the sequence of processor-internal instructions shall be made.
  • Such a jump means that subsequent processor-internal instructions shall be read into the processor from some other place in the sequence, or from subsequent converted processor-external instructions according to the conditional jump instruc- tion.
  • a wrong prediction of the fulfilment of the condition results in following processor-internal instructions that have been read into and partially processed in the processor being flus- hed away so as to prepare room for correct processor-internal instructions with which the condition has been fulfilled to be read into the processor.
  • processor-internal conditional jump instruction When a processor-internal conditional jump instruction is found, the following processor-external instruction is not read into the ATU 5 for conversion. This means that when instructions are removed because of a wrong prediction with regard to the fulfilment of a condition, only processor- internal instructions are removed and the next processor- external instruction can be read into the ATU 5 for conversion.
  • a processor that is designed to also take into account processor-internal conditional jump instructions shall, similarly to the earlier described processor, include a result indicating unit 18 which is adapted to indicate when the result from processing a conditional jump instruction is stored in the instructions buffer.
  • the processor will also include an evaluating unit 16 which is adapted to fetch the result obtained when processing the processor-internal conditional jump instruction, when the result indicating unit 18 indicates that this result is available.
  • the evaluating unit 16 is then able to ascertain whether or not the condition for the processor-internal conditional jump instruction has been fulfilled in accordance with the prediction given by a prediction unit 15. It is also proposed in accordance with the invention that the processor includes an instruction removal unit 17 which is adapted to remove from the processor those processor-internal instructions that are read-in sequentially after the processor-internal conditional jump instruction, regardless of where these instructions are found in the instruction processing operation, upon receipt of a signal from the evaluating unit 16 to the effect that the prediction of the fulfilment of the condition was wrong.
  • a processor may include a sequence number generator 19 which is adapted to generate sequence numbers (SN) and to give each instructions read into the instruction buffer 3 a sequence number.
  • the space in the instruction buffer includes a field 31F which is intended to store the sequence number of the instruction.
  • the SN is sent together with the OPA, OPB and ALSO to the ALU 6 for processing so that the result of the processing in the ALU can be related to the right position within the instruction buffer 3.
  • sequence number is used in the flushing process in order to determine what instructions that have been read into the instruction buffer before the conditional jump instruction and what instructions that have been read into the instruction buffer after the conditional jump instruction.
  • the instruction removal unit 17 is adapted to remove from the processor 1 solely those instructions that have been given sequence numbers that are generated after the sequence number given to the conditional jump instruction, irrespective of where these instructions are found in the instruction processing operation, in response to a signal from the evaluating unit 16 that shows the prediction of the fulfilment of the condition to be wrong.
  • the use of a sequence number according to the aforedescribed can be implemented both in processors that are adapted to take into their account only processor external-instructions or both processor-internal and processor-external instructions.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

L'invention concerne un procédé de gestion des instructions de sauts conditionnels dans un processeur d'ordinateur (1). Dans un tampon d'instructions (3), un espace est réservé aux instructions mises en mémoire dans le processeur. Ces espaces se voient attribuer un ordre correspondant à l'ordre dans lequel les instructions étaient été lues séquentiellement. La dernière position du tampon d'instructions constitue une position de lecture (4). Les résultats obtenus lors du traitement des instructions respectives peuvent être sauvegardés dans des espaces réservés à ces instructions dans le tampon d'instructions (3), dans lequel finalement les résultats peuvent être lus à partir de la position de lecture (4).
PCT/SE1998/001334 1997-07-21 1998-07-07 Procede de gestion d'instructions de sauts conditionnels dans un processeur de donnees Ceased WO1999004335A2 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
BR9810768-2A BR9810768A (pt) 1997-07-21 1998-07-07 Processo de manuseio de instruções especìficas, e, processador
KR1020007000634A KR20010022065A (ko) 1997-07-21 1998-07-07 조건부 점프의 취급에 적용된 처리기 및 방법
AU83652/98A AU8365298A (en) 1997-07-21 1998-07-07 A method for handling conditional jump instructions in a data processor
JP2000503482A JP2001510916A (ja) 1997-07-21 1998-07-07 データプロセッサにおける条件付きジャンプ命令の処理方法
EP98934048A EP0998701A2 (fr) 1997-07-21 1998-07-07 Procede de gestion d'instructions de sauts conditionnels dans un processeur de donnees

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9702762A SE510295C2 (sv) 1997-07-21 1997-07-21 Metod vid processor för att hantera villkorade hoppinstruktioner samt processor anpassad att verka enligt den angivna metoden
SE9702762-7 1997-07-21

Publications (2)

Publication Number Publication Date
WO1999004335A2 true WO1999004335A2 (fr) 1999-01-28
WO1999004335A3 WO1999004335A3 (fr) 1999-04-08

Family

ID=20407793

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SE1998/001334 Ceased WO1999004335A2 (fr) 1997-07-21 1998-07-07 Procede de gestion d'instructions de sauts conditionnels dans un processeur de donnees

Country Status (8)

Country Link
EP (1) EP0998701A2 (fr)
JP (1) JP2001510916A (fr)
KR (1) KR20010022065A (fr)
CN (1) CN1271434A (fr)
AU (1) AU8365298A (fr)
BR (1) BR9810768A (fr)
SE (1) SE510295C2 (fr)
WO (1) WO1999004335A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100337194C (zh) * 2004-03-26 2007-09-12 国际商业机器公司 减少指令高速缓存和流水线处理器之间等待时间的装置和方法
EP2330500A1 (fr) * 2009-11-04 2011-06-08 Ceva D.S.P. Ltd. Système et procédé d'utilisation d'un tampon de mauvaise prédiction de branche

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2367102B1 (fr) 2010-02-11 2013-04-10 Nxp B.V. Processeur informatique et procédé avec des propriétés de sécurité améliorées

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755935A (en) * 1986-01-27 1988-07-05 Schlumberger Technology Corporation Prefetch memory system having next-instruction buffer which stores target tracks of jumps prior to CPU access of instruction
CA1285657C (fr) * 1986-01-29 1991-07-02 Douglas W. Clark Dispositif et methode d'execution d'instructions de branchement
GB8728493D0 (en) * 1987-12-05 1988-01-13 Int Computers Ltd Jump prediction
SE509499C2 (sv) * 1996-05-03 1999-02-01 Ericsson Telefon Ab L M Metod och anordning för hantering av villkorliga hopp vid instruktionsbehandling i en pipeline-arkitektur

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100337194C (zh) * 2004-03-26 2007-09-12 国际商业机器公司 减少指令高速缓存和流水线处理器之间等待时间的装置和方法
EP2330500A1 (fr) * 2009-11-04 2011-06-08 Ceva D.S.P. Ltd. Système et procédé d'utilisation d'un tampon de mauvaise prédiction de branche
US9952869B2 (en) 2009-11-04 2018-04-24 Ceva D.S.P. Ltd. System and method for using a branch mis-prediction buffer
US10409605B2 (en) 2009-11-04 2019-09-10 Ceva D.S.P. Ltd. System and method for using a branch mis-prediction buffer

Also Published As

Publication number Publication date
WO1999004335A3 (fr) 1999-04-08
AU8365298A (en) 1999-02-10
SE9702762D0 (sv) 1997-07-21
JP2001510916A (ja) 2001-08-07
CN1271434A (zh) 2000-10-25
SE9702762L (sv) 1999-01-22
KR20010022065A (ko) 2001-03-15
EP0998701A2 (fr) 2000-05-10
BR9810768A (pt) 2000-08-15
SE510295C2 (sv) 1999-05-10

Similar Documents

Publication Publication Date Title
US7024543B2 (en) Synchronising pipelines in a data processing apparatus
US6772327B2 (en) Floating point unit pipeline synchronized with processor pipeline
CA1212476A (fr) Appareil et methode de traitement de donnees utilisant la prediction de la direction des instructions
US5471626A (en) Variable stage entry/exit instruction pipeline
US7260706B2 (en) Branch misprediction recovery using a side memory
EP0335515B1 (fr) Procédé et appareil pour exécuter des instructions dans un système de traitement de vecteurs
US5404552A (en) Pipeline risc processing unit with improved efficiency when handling data dependency
US5179673A (en) Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline
JP2539974B2 (ja) 情報処理装置におけるレジスタの読出制御方式
EP0328721A2 (fr) Unité de calcul à virgule flottante multiples instructions multiples données multiples pipelines dynamique
EP0468134A2 (fr) Retour de sous-programme utilisant un tableau d'historique de branchement
JPH02234229A (ja) ソース・リスト、ポインタ・キューおよび結果キュー
JPH0334024A (ja) 分岐予測の方法とそのための装置
EP0394624A2 (fr) Système de processeur à multiples séquences
EP0093430A2 (fr) Système de traitement de données en pipe-line
CN117311814A (zh) 取指单元、指令读取方法及芯片
KR100431975B1 (ko) 분기에의한중단이없는파이프라인방식의마이크로프로세서를위한다중명령디스패치시스템
EP0496407A2 (fr) Système de traitement pipeline en parallèle pour des mots d'instruction de très grande largeur
WO1999004335A2 (fr) Procede de gestion d'instructions de sauts conditionnels dans un processeur de donnees
EP0162929A1 (fr) Procede de commande de branchement
US6108761A (en) Method of and apparatus for saving time performing certain transfer instructions
US5713012A (en) Microprocessor
JP2002014868A (ja) メモリ参照動作検出機構を有するマイクロプロセッサおよびコンパイル方法
RU2828600C1 (ru) Процессор с загрузкой команд в составе кэшлайна и предсказанием перехода
US20040128476A1 (en) Scheme to simplify instruction buffer logic supporting multiple strands

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 98809339.1

Country of ref document: CN

AK Designated states

Kind code of ref document: A2

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM GW HR HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW SD SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1020007000634

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 1998934048

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1998934048

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

NENP Non-entry into the national phase

Ref country code: CA

WWP Wipo information: published in national office

Ref document number: 1020007000634

Country of ref document: KR

WWW Wipo information: withdrawn in national office

Ref document number: 1020007000634

Country of ref document: KR

WWW Wipo information: withdrawn in national office

Ref document number: 1998934048

Country of ref document: EP