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WO1999060329A1 - Detonateur electronique a retard - Google Patents

Detonateur electronique a retard Download PDF

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Publication number
WO1999060329A1
WO1999060329A1 PCT/JP1999/002080 JP9902080W WO9960329A1 WO 1999060329 A1 WO1999060329 A1 WO 1999060329A1 JP 9902080 W JP9902080 W JP 9902080W WO 9960329 A1 WO9960329 A1 WO 9960329A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
voltage
detonation
electronic delay
delay detonator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP1999/002080
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English (en)
Japanese (ja)
Inventor
Kazuhiro Kurogi
Midori Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Kasei Corp
Asahi Chemical Industry Co Ltd
Original Assignee
Asahi Chemical Industry Co Ltd
Asahi Kasei Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Chemical Industry Co Ltd, Asahi Kasei Kogyo KK filed Critical Asahi Chemical Industry Co Ltd
Priority to AU31720/99A priority Critical patent/AU3172099A/en
Publication of WO1999060329A1 publication Critical patent/WO1999060329A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F42—AMMUNITION; BLASTING
    • F42B—EXPLOSIVE CHARGES, e.g. FOR BLASTING, FIREWORKS, AMMUNITION
    • F42B3/00—Blasting cartridges, i.e. case and explosive
    • F42B3/10—Initiators therefor
    • F42B3/12—Bridge initiators
    • F42B3/121—Initiators with incorporated integrated circuit
    • F42B3/122—Programmable electronic delay initiators
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F42—AMMUNITION; BLASTING
    • F42D—BLASTING
    • F42D1/00—Blasting methods or apparatus, e.g. loading or tamping
    • F42D1/04—Arrangements for ignition
    • F42D1/045—Arrangements for electric ignition
    • F42D1/05—Electric circuits for blasting

Definitions

  • the present invention provides a high-precision blasting operation in which a plurality of explosives are loaded on a crushing target (for example, a bedrock or a building) and each of them is sequentially or simultaneously detonated to crush the crushing target.
  • the present invention relates to an electronic delay detonator capable of controlling the detonation time, ensuring the reliability of detonation, and further capable of arbitrarily programming the detonation time.
  • a charging circuit for receiving the electric energy transmitted from the device and storing the electric energy, an electronic timer driven by the stored electric energy, and an electronic timer.
  • an ignition switch that discharges the accumulated electric energy and an ignition device that is detonated by the discharged electric energy form an electronic delay detonator. Proposed.
  • the conventional technology of this type of electronic delay detonator can be roughly classified from the functional point of view of the function of starting the timing of detonation. Sending, timing It is classified into the type that starts automatically.
  • the delay time is set at the time of shipment from the factory.
  • USP 4, 445, 435 and the user can freely program the delay time.
  • USP 4, 674, 047, USP 5, 460, 093, USP 5, 406, 890 and so on are examples of USP 4, 674, 047, USP 5, 460, 093, USP 5, 406, 890 and so on.
  • the step of programming the detonation delay time and after timing the programmed detonation time It has two operating stages: detonating the primer.
  • the two operation stages are distinguished by a difference in control signal between the signal source and the electronic delay detonator based on the communication protocol.
  • Electronic delay detonators belonging to the latter type include USP 5,363,765 and others.
  • control signal communication In communication of the control signal, there is a concern that the control signal is not transmitted to the detonator as intended, due to the noise environment and the connection reliability of the detonator. Since the connection operation of the detonator is performed artificially, it was necessary to assume that various failure phenomena would occur in the connection state, and the inspection and inspection were performed before the detonation operation Nevertheless, it is undeniable that the possibility that such a failure event as described above would occur at the time of the start of the explosion timing.
  • connection form is generally a distributed branching.
  • the (parallel connection) method is preferred, and it is composed of a plurality of detonators connected in parallel to the signal source.
  • the input impedance of an electronic delay detonator is generally designed to be relatively high, and the signal power is weak. In such cases, such concerns are even more acute.
  • Another point of concern is the safety of the program or the safety against stray currents that may occur at the blasting site.
  • the ignition element attached to the electronic delay detonator has a "designed misfire voltage", and the program is lower than the misfire voltage. It discloses the technology to be implemented.
  • the safety during programming can be avoided by the technology disclosed in the above-mentioned W092 / 1067 or similar technology. However, this does not necessarily ensure the same safety against stray currents.
  • the input impedance of the electronic delay detonator is set relatively high as described above. .
  • the type that leads to detonation only by supplying energy without exchanging the detonation signal is simple and has a simple structure, so the reliability is high, but the user can freely set the delay time.
  • the things that can be programmed are not known.
  • this type of electronic delay detonator will detonate when supplied with sufficient electrical energy to operate as indicated by its characteristics. Because it operates, it is widely armed. In the case of adding such a function that enables the program control as described above to such an electronic delay detonator of the evening eve, work safety is ensured. To maintain the distinction between program control and detonation control while maintaining it requires an extra measure.
  • the electronic delay detonator according to the present invention can be programmed with an arbitrary detonation delay time with high reliability and safety in functionality, and can be reliably detonated. Regarding delay detonators. Disclosure of invention
  • an electronic delay detonator includes a pair of input terminals for receiving electric energy transmitted from a blaster, a rectifier circuit, and the electric A charging circuit for storing energy, and an enable signal generated after a first reference time driven by the stored electric energy, and a second reference time that can be set.
  • the charging circuit After receiving the enable signal and an electronic signal that emits a trigger signal later, the charging circuit detects the charging voltage level of the charging circuit, and If the electric voltage is equal to or higher than the first voltage, the first operation leading to detonation is performed, and if the charging voltage is equal to or lower than the second voltage which is lower than the first voltage, the detonation condition is set.
  • An operation determining means for controlling to perform a second operation to be set; and receiving the trigger signal in the first operation and storing the trigger signal in the charging circuit.
  • a detonation switch for discharging electric energy, a ignition device detonated by the discharged electric energy, and a control signal for receiving a control signal in the second operation Signal receiving means and a detonation condition setting means controlled by the control signal.
  • the second voltage is a misfire voltage that is not sufficient to ignite the igniter.
  • the control signal receiving means receives a control signal composed of a pulse train applied between the input terminals after the charging circuit is charged, and sets the firing condition according to the control signal. Means are configured to set the firing conditions.
  • the firing condition set by the firing condition setting means is output as a pulse train between input terminals. It has an explosion condition output means.
  • the explosion condition output means comprises a side current signal generating means and a side current circuit for flowing a current applied between the signal input terminals, and the side current signal generating means comprises a program.
  • a side current signal consisting of a pulse train corresponding to the condition is output, and when the side current circuit receives the side current signal, the constant current received following the inspection control signal described above.
  • a controlled current is caused to flow by side to generate a voltage change between the input terminals, and the voltage change is It is configured to output to the outside as a pulse train of the firing condition.
  • the electronic delay detonator of the present invention has a side-flow resistor between the input terminals.
  • the side current resistor determines a signal voltage applied to an internal circuit of the electronic delay detonator when the control signal is applied while being controlled to a constant current.
  • the resistance value of the side current resistor is preferably
  • the side current resistor is composed of 10 ⁇ or 20 ⁇ , the signal impedance will increase due to the lower input impedance, and the S / N ratio will increase. Has been significantly improved, and the reliability of communications can be increased.
  • the input impedance of the electronic delay detonator is reduced by the side current resistor, and the safety against stray current is enhanced.
  • the operation determining means determines that the charging voltage is lower than the first voltage and higher than the second voltage, the charging is performed. It has self-discharge means for self-discharging the voltage.
  • the supply of electric energy for detonation such as when supplying electric energy by blasting an evening eve that discharges the electric energy charged to a capacitor
  • the potential between the input terminals is detected after a predetermined time that has been determined in advance after receiving the enable signal.
  • a self-discharging means for self-discharging the electric energy accumulated in the charging circuit may be provided.
  • the charging signal level of the charging circuit is continuously detected in response to the enable signal, and it is determined that the charging voltage has reached the first voltage or higher.
  • An operation determining means for detecting and generating a reset signal is provided, and the timing circuit receives the reset signal and generates a trigger signal after measuring a second reference time. It may be configured.
  • the electronic delay detonator of the present invention it is possible to distinguish the operation based on the voltage level charged in the energy storage circuit.
  • the detonation operation can be performed only by supplying the electric energy.
  • the signal source may fail unexpectedly, and the power supply voltage may be directly applied to the primer. Even if it is applied, it does not shift to the detonation mode, and self-discharge can be safely performed.
  • the detonation conditions can be set by receiving a control signal, for example, the detonation delay time can be set arbitrarily. Further set Since the detonation conditions can be output as a pulse train between the input terminals, the output pulse is analyzed and the intended detonation conditions are set without mistake. Can be confirmed.
  • FIG. 1 is an example of a structural diagram of an electronic delay detonator according to an embodiment of the present invention.
  • FIG. 2 is an example of a structural diagram of an electric detonator 3 used for the electronic delay detonator of the embodiment of the present invention.
  • FIG. 3 is an example of a hybrid IC configuration of the electronic delay detonator of the embodiment of the present invention.
  • FIG. 4 shows an example of a block diagram for explaining the operation of the electronic delay detonator of the embodiment of the present invention.
  • FIG. 5 is a flowchart illustrating an overall operation of the electronic delay detonator according to the embodiment of the present invention.
  • FIG. 6 is a flowchart illustrating the detonating operation of the electronic delay detonator according to the embodiment of the present invention.
  • FIG. 7 is a flowchart illustrating an operation for specifying an operation mode of a signal control processing operation of the electronic delay detonator according to the embodiment of the present invention.
  • FIG. 8 is a flowchart showing an example of the operation of the electronic delay detonator of the embodiment of the present invention in the id data program mode.
  • FIG. 9 is a flowchart illustrating an operation of the electronic delay detonator according to the embodiment of the present invention in the detonation time data program mode.
  • FIG. 10 shows the id delay time of the electronic delay detonator of the embodiment of the present invention.
  • 6 is a flowchart illustrating a check mode operation.
  • FIG. 11 is a flowchart illustrating an operation of the electronic delay detonator according to the embodiment of the present invention in the detonation time over time check mode operation.
  • FIG. 12 is a flowchart illustrating a pseudo ignition discharge operation of the electronic delay detonator of the embodiment of the present invention.
  • FIG. 13 is a flowchart illustrating a self-discharge operation of the electronic delay detonator of the embodiment of the present invention.
  • FIG. 1 illustrates a structural diagram of an electronic delay detonator according to the present embodiment.
  • the electronic delay detonator of this embodiment has a pair of legs 1 for receiving electric energy or a control signal supplied from a signal source or a blaster (not shown),
  • An energy storage capacitor 34 that charges the supplied electric energy, and an evening that is operated by the electric energy charged in the capacitor 34 It comprises an imaginary module 2 and an electric detonator 3 which is detonated by the electric energy charged in the capacitor 34.
  • the timer module 2 and the electric detonator 3 are inserted into the bottomed insulated tube 5, and then both the capacitors 34 and the bottomed tubes are inserted. It is stored in the metal case 6.
  • the leg 1 is connected to the timer module 2 from the outside through an embolus 4 made of synthetic resin.
  • the opening of the metal case 6 is sealed with the plug 4, and the metal case 6 is tightened and sealed.
  • FIG. 2 illustrates a structural diagram of an electric detonator 3 used in the electronic delay detonator of the present embodiment.
  • the electric detonator 3 includes a pair of legs 11 for receiving the discharge energy of the capacitor 34, and an ignition heater (electric bridge) 1 connected to an end of the leg 11. 3 and an ignition device 12 composed of an ignition device arranged around the ignition heater 13, and a priming 15 and an additive 16 are arranged in a bottomed manner as shown in FIG. 2. It is housed in a metal case 18 of the present invention.
  • the leg 11 connects the timer module 2 and the ignition heater 13 through an embolus 17 made of synthetic resin.
  • the opening of the metal case 18 is sealed with the plug 17, and the metal case 18 is tightened and sealed.
  • the metal case 6 has a thickness of, for example, 0.5 to lmm at a portion covering the timer module 2 and has a thickness covering a portion covering the electric detonator 3 at the tip.
  • it has an uneven thickness structure with a thickness of 0.2 to 0.3 mm.
  • the uneven thickness structure protects the module 2 from external shocks, for example, the explosion of an adjacent hole, and is effective to prevent the detonation power of the electric detonator 3 from being impaired.
  • the insulating tube 5 is made of an electrically insulating plastic material, for example, vinyl chloride, polyster, polyethylene, and a metal case 6. Dramatically improves the antistatic performance between the electric detonator 3 and the metal case 6 and the timer module 2, and the static electricity Prevent the explosion of the electric detonator 3 and the failure due to the damage of the timer module 2.
  • the shape is not limited, it is preferable to be molded in consideration of manufacturability. For this reason, a polystyrene excellent in moldability and preform is used as the material. It is optimal.
  • the insulating tube 5 of the present embodiment is configured to cover only the timer module 2 and the electric detonator 3, but this is extremely large.
  • the discharge point When a large amount of static electricity is received, the discharge point is discharged at the connection terminal of the capacitor 34 near the opening of the tube, and the static electricity generated at random To prevent the electric detonator 3 from exploding, but cover the capacitor 34 and extend it between the plug 4 and the case 6, and It may be tightened and sealed at the same time.
  • FIG. 3 shows an example of the timer IC module 2 of the electronic delay detonator of this embodiment.
  • FIG. 4 is a block diagram illustrating the operation of the timer IC 40 mounted on the timer module 2 of the electronic delay detonator of the present embodiment. It is a thing.
  • FIG. 5 exemplifies a flow chart of the overall operation of the electronic delay detonator of the present embodiment.
  • the electronic delay detonator has a charging circuit 34 for storing electric energy, and after a first reference time T1 which is predetermined after the charging circuit 34 is charged.
  • a self-generated enable signal (SE) is generated at a predetermined time after the enable signal (SE) is generated. Then, the charging voltage of the charging circuit 34 is detected, and the following two selectable operations are performed according to the charging voltage level.
  • the first operation that can be selected is an initiating operation that starts the electric detonator 3 by measuring a settable second reference time T2.
  • the second operation that can be selected is a signal control processing operation determined by a transmitted control signal.
  • the settable second reference time T2 can be programmed.
  • the constant voltage circuit 38 connects the capacitor C 5, the time constant circuit 47, and the timer IC 40. To output a constant voltage.
  • the oscillation circuit 100 (FIG. 4) disposed inside the IC 40 sets the XT, The driving of the crystal oscillation circuit 50 connected to the XT bar terminal is started.
  • the reset release signal output point 54 of the time constant circuit 47 is connected to the RESET terminal of the timer IC 40, and the potential of the output point 54 is input.
  • a comparator (not shown) is provided inside the timer IC 40 so that the potential at the output point reaches a predetermined value.
  • the first reference time Tl is counted. After the first reference time T1, the reset state of the RESET circuit 101 (FIG. 4) in the timer IC 40 is released.
  • the ESET circuit 101 (Fig. 4) resets all the functions of the timer IC 40 and returns to the state where the function can be operated. Become .
  • the evening image IC 40 (Fig. 3) is composed of a power supply switch 100, a control circuit system 201, and a circuit system 202.
  • the control circuit system 201 is composed of circuit systems 211 and 212.
  • Circuit system 211 has charge voltage judgment logic 111, input signal characteristic check logic 112, start signal judgment logic 113, program logic Includes 114, id data memory 115, and detonation time data memory 116.
  • Circuit system 212 includes detonation time data counting logic 118.
  • the circuit system 202 includes a REST circuit 101 and an oscillation circuit 102.
  • the power supply switching switch 100 receives and receives signals, which are fixed by the constant voltage circuit 38 (FIG. 3) via the Vcc terminal. Supply the power supply voltage to 01 and 202.
  • the RESET circuit 101 and the oscillation circuit 102 supply a reset release signal or a reset signal and an oscillation pulse to the necessary parts of the circuit system 201, respectively. . Evening IC 40 (Fig. 3) When the power is reset, the reset signal is applied to the output selection logic 1 17 from the reset circuit 101. (SP) is sent to prevent SCR 2 ( Figure 3) from being inadvertently triggered. (1st operation prohibition means)
  • VCMP 2 and VCMP 3 are respectively connected to a divided voltage output point 52 of a voltage divider circuit 42 and a divided voltage output point 53 of a voltage divider circuit 43, and The charge voltage of the capacitor 34 is detected.
  • the charge voltage judgment logic 1 1 1 judges that the potential of VCMP 2 is equal to or lower than the second voltage set in advance
  • the start signal judgment logic 1 1 3 Then, the program logic 114 is activated to start the second operation, that is, the signal control processing operation.
  • the charge voltage determination logic 111 is set so that the potential of VCMP 2 is lower than the preset first voltage, and the potential of VCMP 3 exceeds the preset second voltage. When it is determined that the voltage is a voltage that can be obtained, the charge voltage determination logic 111 sends a discharge signal (SD1) to the selected output logic 117. Selected output logic 1 1 7 Upon receiving the discharge signal (SD1), the self-discharge signal (SD) is output from the OUTB terminal of the IC 40 (FIG. 3).
  • the OUTB terminal is connected to the gate terminal of the SCR 1, and when the self-discharge signal (SD) is output, the energy is stored through the self-discharge circuit 44. Self-discharge the charge of capacitor 34.
  • the input signal characteristic confirmation logic 112 starts determination of the potential of VCMP 1, and determines the input signal characteristic in step time t 3, for example, 100 ms.
  • V CMP1 is connected to the divided output point 51 of the voltage dividing circuit 41, and detects the potential between the input terminals IN 1 and IN 2 through the rectifier 32.
  • the period from time t2 to t3 is divided by a predetermined time interval dt, and the potential of VCMP1 is determined a predetermined number of times n times.
  • V CMP 1 is continuously receiving a voltage equal to or higher than the third voltage.
  • the total of the determination results is integrated, and during a period from the time t2 to the time t3, the potential of the VCMP1 is continuously set to be equal to or less than the third voltage set in advance. Make sure there is. This prevents erroneous judgment due to accidental noise.
  • the charge voltage determination logic 1 11 determines that the potential of VCMP 3 is equal to or higher than the preset first voltage at time t 1, and the input signal characteristics If the confirmation logic 112 determines that VCMP 1 is continuously lower than or equal to the third voltage in the time width from time t2 to t3, the input signal characteristic The confirmation logic 112 activates the detonation time delay counting logic 118 and shifts to the second operation, that is, the detonation operation.
  • charge voltage determination logic 1 1 1 has determined at time t 1 that the potential of VCMP 2 is greater than or equal to the preset first voltage.
  • Input signal characteristics check Logic 1 12 determines that VCMP 1 has not been continuously below the third voltage in the time width from time t2 to t3. Then, the input signal characteristic confirmation logic 112 sends a discharge signal (SD2) to the output selection logic 117. Upon receiving the discharge signal (SD2), the selected output logic 117 outputs a self-discharge signal (SD) to the OUTB terminal.
  • SD2 discharge signal
  • the OUTB terminal is connected to the gate terminal of SCR1, and when the self-discharge signal (SD) is output, the self-discharge circuit 44 is activated. As a result, the charge stored in the energy storage capacitor 34 is self-discharged.
  • SD self-discharge signal
  • the input signal characteristic confirmation logic 112 sends a timing start signal (SS), activates the explosion time data counting logic 118, and transitions to the second operation immediately to the explosion operation. Then, the input signal characteristic confirmation logic 112 sends a protect release signal (SK1) to the selected output circuit 117. (Fig. 6, Step 9)
  • the input signal characteristic confirmation logic 112 sends a power switching signal (SV) to the power switching switch 100.
  • the power switching switch 100 is switched when it receives a power switching signal (SV), and stops the supply of the power voltage to the circuit system 211.
  • the detonation time data counting logic 118 is pre-programmed by counting the output pulses of the oscillating circuit 102, a second reference which is pre-programmed. Time T 2.
  • the detonation time data counting logic 118 is connected to the detonation time data memory 116, and is used for the time data in the detonation time data memory 116. Count the corresponding pulses.
  • the oscillation circuit 102 outputs a pulse by driving a crystal oscillation circuit 50 connected through XT and XT-bar.
  • the oscillation circuit 102 outputs the above output pulse by dividing the output pulse as needed to the circuit system 201 inside the IC 40.
  • the detonation time data counting logic 118 outputs a count end signal to the output selection circuit 117.
  • Output selection circuit 1 1 7 When a signal (Se) is received, a trigger signal (ST) is output to OUTC. (Fig. 6-Step 1 2)
  • the OUTC terminal is connected to the gate terminal of SCR 2, and when the trigger signal (ST) is output, the energy storage capacitor 3 is output.
  • the charge of 4 is ignited and discharged to the ignition discharge circuit including the OUT1 and OUT2 terminals, and the attached electric detonator 3 (Fig. 1) is detonated.
  • FIG. 6 Step 13
  • the entire operation of the second operation ie, the signal control processing operation (FIG. 5, step 5) Explain.
  • the signal control processing operation is controlled by a control signal received from an external control signal source (not shown).
  • the control signal includes a start signal, a step signal, a program data signal, and a write signal which are transmitted from an external control signal source (not shown) in chronological order in a predetermined order. It consists of a combination of the input power signal and the return reference level signal.
  • the second operation is composed of a plurality of signal control operation modes each of which is independently executed, and in each of the signal control modes, execution of the second operation is determined. It is specified by the start signal sent later from the outside, and responds to the control signal and the program data signal related to each signal control mode sent continuously. And perform the action.
  • the signal control operation mode and a start signal for specifying the operation mode will be exemplified below. • The start signal bit of the id data program mode is set.
  • [0] of the bit pattern is an "L" level signal
  • [1] is an "H" level signal.
  • the start signal is, for example, a pulse train power of 5 b it, where the first b it is [0].
  • the electronic delay detonator detects the leading bit [0], and the external control signal source (not shown) and the electronic delay detonator are synchronized.
  • the start signal and the continuous control signal are externally controlled to a constant current, input from IN 1 and IN 2, and correspond to the above-described constant current value by the input resistor R 1. It is supplied as a voltage.
  • the control signal is supplied at a voltage approximately equal to or slightly lower than the charging potential of the energy storage capacitor 34.
  • the control signal is pre-charged by a signal detection diode 33 via a rectifier 32.
  • the signal is input to the DATAIN pin of the IC 40 without being affected by the potential of the energy storage capacitor 34.
  • the electronic delay detonator stores a step status signal indicating the progress of the control operation in response to the control signal and program data stored in an internal storage circuit described later. It has a function to reply to the outside.
  • the reply operation is performed by a serial pulse from the OUTA terminal of the timer IC 40 at a predetermined timing in accordance with a predetermined communication protocol.
  • the output is sent to the gate terminal of MOS-FET 35.
  • the above-mentioned reply reference level signal is received immediately, that is, a continuous signal externally controlled to a constant current.
  • the potential between the input terminals IN1 and IN2 is controlled.
  • the voltage is held as a voltage corresponding to the constant current value by the input resistor R 1 similarly.
  • the control signal to be received via the DTA IN terminal is input to the start signal discriminating logic 113 and the program logic 114.
  • the start signal discriminating logic 113 and the program logic 114 correspond to the first bit bit of the start signal transmitted first.
  • the start signal discriminating logic 113 identifies the signal control mode by discriminating the sequentially received start signal bit pattern sequence, and the control mode indicating the control mode. Send the specified signal (SC) to the program logic 114.
  • SC control mode specific signal
  • the program logic 114 responds to the control signal which is continuously received and operates in accordance with the specific signal. Perform.
  • the id data memory 115 is preferably an electrically writable non-volatile memory such as R RM, and most preferably an EEPROM. Be composed.
  • the detonation time memory 116 is preferably an electrically writable non-volatile memory such as a ROM. Most preferably, it consists of an EEPROM.
  • control mode is id data check mode (start signal bit pattern [0 1 1 0 0])
  • id data memory 1 15 An operation of reading the id data written to the terminal and outputting the id data to the OUTA terminal via the output selection logic 117 is executed.
  • control mode is the detonation time data check mode (start signal bito n ° [0 0 1 1 0])
  • the detonation time data will be lost. Operation to read out the explosion time data written in the memory 116 and output the explosion time data to OUTA terminal via output selection logic 117. Perform.
  • control mode is the pseudo ignition discharge mode (start signal bit pattern [0101])
  • program logic 114 is selected and output. After sending a protect release signal (SK2) to the power circuit 1 17 to set the ignition circuit to a state in which ignition is possible, it is written to the ignition time data memory 116.
  • the detonation time data that is, the second reference time T2 is measured, and the pseudo ignition discharge operation is executed.
  • the pseudo-ignition discharge operation performs the same operation as the above-mentioned detonation operation (steps 9 to 11 in FIG. 6), but in this case, the energy storage capacitor 3
  • the discharge voltage of 4 is lower than the discharge voltage that can be detonated, and is configured so that it does not explode.
  • An external control signal source (not shown) is a signal controlled by a constant current immediately from the time when the second reference time is measured to the time when the pseudo ignition discharge is performed. The signal is transmitted and the pseudo-ignition is discharged. At this point, the voltage change that occurs between the input terminals (IN1, IN2) because the return reference level signal is bypassed to the ignition discharge circuit 45 (Fig. 3) (Descent) and confirm that there is no problem in the ignition discharge circuit 45.
  • control mode is the self-discharge mode (start signal bit pattern [0100])
  • program logic 114 is selected.
  • the selected output logic 117 Upon receiving the discharge signal (SD 3), the selected output logic 117 outputs a self-discharge signal (SD) to the ⁇ UTB terminal.
  • the OUTB terminal is connected to the gate terminal of the SCR 1, and when the self-discharge signal (SD) is output, the OUTB terminal passes through the self-discharge circuit 44. Then, the charge of the energy storage capacitor 34 is self-discharged.
  • the self-discharge mode is executed mainly to discharge the charge stored in the energy storage capacitor 34 when the second operation is completed, and the second operation, that is, the signal Used as the end mode of control processing operation.
  • the plurality of signal control operation modes are not completed except for the pseudo ignition discharge mode and the self-discharge mode, and after each operation mode is executed, the start signal is not reset. It returns to the state of waiting for [0] of the first bit, detects the first bit, synchronizes again with an external control signal source (not shown), and continues operation.
  • the determination of the charging voltage of the energy storage capacitor 34 is as follows.
  • the charge voltage determination logic 111 determines whether or not the potential of the VCMP 2 terminal of the timer IC 40 is equal to or lower than the second voltage.
  • the charging voltage determination port 1 1 1 1 Sends a reset signal (SR) to the RESET circuit 101.
  • the REST circuit 101 resets the operation of the circuit system 201.
  • the determination of the charging voltage of the energy storage capacitor 34 is continued until the second operation is completed. If it is determined that the charging voltage of the capacitor 34 is equal to or higher than the second voltage, all the operations are initialized and return to the initial state (FIG. 5—Step 2). Repeat the operation.
  • the start bit of the start signal is determined.
  • step 103 in FIG. 7 In the operation of discriminating the start signal (step 103 in FIG. 7), when the id data program mode start signal [01001] is recognized, A step status signal sequence [01] indicating that the start signal has been recognized is output on the reply reference level signal.
  • an external control signal source detects the step state signal and transmits the id program data string. To receive. (Fig. 8 Step 1 1 2)
  • writing of the id program data is executed by a write power signal supplied by an external control signal source (not shown).
  • Figure 8 Step 1 1 4
  • a signal indicating that the writing of the id program data string has been completed on the reply reference level signal is completed. Outputs the step status signal sequence [01].
  • the operation is terminated, and the operation returns to the detection standby state (step 101 in FIG. 7) for detecting [0] at the start bit of the start signal.
  • Step 103 in Fig. 7 when the ignition time data program mode start signal [0101] is recognized, a reply is returned.
  • a step status signal sequence [01] indicating that the start signal has been recognized is output on the reference level signal.
  • an external control signal source detects the step status signal and receives an id confirmation data string transmitted therefrom.
  • a step status signal string [01] indicating that the reception of the id data string is terminated is output on the reply reference level signal.
  • the id data is put on the reply reference level signal and It outputs a step status signal string [0 1] to the effect.
  • an external control signal source (not shown) detects the step state signal and transmits the same. Receive the column.
  • the id data string is If they do not match, reset each element that performs signal control processing, and wait for the time that continuous firing time data program mode operation should end. For example, the reset state is maintained for 150 ms.
  • step 101 in FIG. 7 the operation is terminated, and the process returns to the detection standby state (step 101 in FIG. 7) for detecting [0] at the start bit of the start signal.
  • step 103 in FIG. 7 when the detonation time data program mode start signal [010110] is recognized, A step status signal sequence [01] indicating that the start signal has been recognized is output on the reply reference level signal. (Fig. 1 1 — Step 15 1)
  • an external control signal source detects the step state signal and receives an id confirmation data sequence which is transmitted.
  • a step status signal sequence indicating that the reception of the id program data sequence has been completed with the reply reference level signal is completed. 0 1] is output.
  • step status signal sequence [01] indicating that the id data is matched is output on the reply reference level signal.
  • a step status signal string [0] indicating that the response of the detonation time program data string is terminated on the reply reference level signal 1] is output.
  • the ratio of the read id data sequence to the received id data sequence In the step for performing the comparison (FIG. 1—Step 144), when the id data does not match, each element for executing the signal control processing is performed. The reset state is maintained, and the reset state is maintained for the duration that the data explosion time data pro- gram mode operation should end, for example, for 150 ms. You (Fig. 1 1 Step 160)
  • step 103 in Fig. 7 When the id data program mode start signal [0101] is recognized in the start signal discrimination operation (step 103 in Fig. 7), a reply is returned. A step status signal sequence [01] indicating that the start signal has been recognized is output on the reference level signal.
  • step 103 in FIG. 7 when the id data program mode start signal [0100] is recognized, a reply reference is made.
  • a step status signal sequence [01] indicating that the start signal has been recognized is output on the level signal.
  • the signal control processing operations shown in FIGS. 8 to 13 can be arbitrarily combined and executed. Potential for industrial use
  • the electronic delay detonator of the present invention it is possible to distinguish the operation by detecting the level of the supplied voltage. Alternatively, it is possible to configure safety operations in various ways. This is particularly effective when the second operation for setting the detonation conditions, that is, when programming the detonation delay time.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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Abstract

L'invention concerne de l'énergie électrique émise par un exploseur et reçue par deux bornes d'entrée. Cette énergie est ensuite chargée dans un circuit de charge pour entraîner un temporisateur électronique. Ce dernier émet un signal de validation au bout d'un laps de temps prédéterminé et détecte le niveau de tension de charge du circuit de chargement. Ce temporisateur assure ainsi une première opération qui se traduit par une détonation, et une deuxième opération qui détermine des conditions de détonation. La première opération émet un signal de déclenchement au bout d'un deuxième laps de temps de référence déterminé par la deuxième opération, et décharge l'énergie électrique accumulée pour provoquer la détonation. Il n'est pas nécessaire que le signal de déclenchement de détonation soit reçu. Par conséquent, il est peu probable que la détonation soit déclenchée par erreur, et de ce fait, l'opération d'explosion se déroulera en toute sécurité et sans erreur.
PCT/JP1999/002080 1998-05-19 1999-04-20 Detonateur electronique a retard Ceased WO1999060329A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU31720/99A AU3172099A (en) 1998-05-19 1999-04-20 Electronic delay detonator

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP13704498A JPH11325799A (ja) 1998-05-19 1998-05-19 電子式遅延雷管
JP10/137044 1998-05-19

Publications (1)

Publication Number Publication Date
WO1999060329A1 true WO1999060329A1 (fr) 1999-11-25

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PCT/JP1999/002080 Ceased WO1999060329A1 (fr) 1998-05-19 1999-04-20 Detonateur electronique a retard

Country Status (4)

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JP (1) JPH11325799A (fr)
AU (1) AU3172099A (fr)
TW (1) TW406184B (fr)
WO (1) WO1999060329A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102410794A (zh) * 2011-11-03 2012-04-11 和英波 煤矿发爆器用无触点高压电子毫秒开关

Families Citing this family (5)

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Publication number Priority date Publication date Assignee Title
KR100841680B1 (ko) 2007-02-14 2008-06-26 주식회사 한화 전자유도 시한장입방식의 전자식시한시관 및 시한장입기
KR101016538B1 (ko) 2009-09-03 2011-02-24 안병호 마이크로컨트롤러에서 기준시간 설정방법 및 그 방법을 이용한 전자식 뇌관
KR101213974B1 (ko) 2010-06-08 2012-12-20 국방과학연구소 전기식 기폭관용 기폭장치, 이를 구비하는 폭파장치 및 전기식 기폭관의 기폭방법
CN105043173B (zh) * 2015-08-26 2017-06-20 成都天博威科技有限公司 延时起爆控制电路
CN113739653A (zh) * 2021-09-17 2021-12-03 无锡盛景微电子股份有限公司 一种适用于集成电路的换能器的控制电路及设备

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JPS57142499A (en) * 1980-12-11 1982-09-03 Ici Ltd Apparatus for and method of starting explosion
JPS57142500A (en) * 1981-02-25 1982-09-03 Asahi Chemical Ind Electric fuse
JPS61186278A (ja) * 1985-02-15 1986-08-19 旭化成株式会社 電気的遅延雷管
JPH01208700A (ja) * 1988-02-16 1989-08-22 Nippon Oil & Fats Co Ltd 電気発破用遅延回路
JPH04169799A (ja) * 1990-11-02 1992-06-17 Nippon Oil & Fats Co Ltd 電子式延時雷管

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JPS57142499A (en) * 1980-12-11 1982-09-03 Ici Ltd Apparatus for and method of starting explosion
JPS57142500A (en) * 1981-02-25 1982-09-03 Asahi Chemical Ind Electric fuse
JPS61186278A (ja) * 1985-02-15 1986-08-19 旭化成株式会社 電気的遅延雷管
JPH01208700A (ja) * 1988-02-16 1989-08-22 Nippon Oil & Fats Co Ltd 電気発破用遅延回路
JPH04169799A (ja) * 1990-11-02 1992-06-17 Nippon Oil & Fats Co Ltd 電子式延時雷管

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102410794A (zh) * 2011-11-03 2012-04-11 和英波 煤矿发爆器用无触点高压电子毫秒开关

Also Published As

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JPH11325799A (ja) 1999-11-26
TW406184B (en) 2000-09-21
AU3172099A (en) 1999-12-06

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