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WO1999048008A3 - Method and apparatus for intermodule data transfer - Google Patents

Method and apparatus for intermodule data transfer Download PDF

Info

Publication number
WO1999048008A3
WO1999048008A3 PCT/US1999/000545 US9900545W WO9948008A3 WO 1999048008 A3 WO1999048008 A3 WO 1999048008A3 US 9900545 W US9900545 W US 9900545W WO 9948008 A3 WO9948008 A3 WO 9948008A3
Authority
WO
WIPO (PCT)
Prior art keywords
devices
transfer
bus
data transfer
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1999/000545
Other languages
French (fr)
Other versions
WO1999048008A2 (en
Inventor
Timothy E Hoglung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Priority to EP99903037A priority Critical patent/EP0979457A2/en
Publication of WO1999048008A2 publication Critical patent/WO1999048008A2/en
Publication of WO1999048008A3 publication Critical patent/WO1999048008A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

A method and apparatus for transferring data between devices in an integrated circuit (100). The devices are coupled to each other through a bus (116, 118, 120, 122, 124, 126) in which tri-state non-contention is insured through the use of turnaround cycles. Signals driven during an address state are turned around during data states while flow control signals are turned around during address cycles. Additionally, the bus of the present invention allows for both master devices (102, 104) and slave devices (106, 108, 110, 112) to regulate the transfer of data. Decentralized decoding also is employed in the transfer.
PCT/US1999/000545 1998-01-12 1999-01-11 Method and apparatus for intermodule data transfer Ceased WO1999048008A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP99903037A EP0979457A2 (en) 1998-01-12 1999-01-11 Method and apparatus for intermodule data transfer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US471198A 1998-01-12 1998-01-12
US09/004,711 1998-01-12

Publications (2)

Publication Number Publication Date
WO1999048008A2 WO1999048008A2 (en) 1999-09-23
WO1999048008A3 true WO1999048008A3 (en) 1999-12-23

Family

ID=21712153

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/000545 Ceased WO1999048008A2 (en) 1998-01-12 1999-01-11 Method and apparatus for intermodule data transfer

Country Status (2)

Country Link
EP (1) EP0979457A2 (en)
WO (1) WO1999048008A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0579397A1 (en) * 1992-06-29 1994-01-19 Xerox Corporation Method of determining devices requesting the transfer of data signals on a bus
US5467295A (en) * 1992-04-30 1995-11-14 Intel Corporation Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit
US5502824A (en) * 1992-12-28 1996-03-26 Ncr Corporation Peripheral component interconnect "always on" protocol

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5467295A (en) * 1992-04-30 1995-11-14 Intel Corporation Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit
EP0579397A1 (en) * 1992-06-29 1994-01-19 Xerox Corporation Method of determining devices requesting the transfer of data signals on a bus
US5502824A (en) * 1992-12-28 1996-03-26 Ncr Corporation Peripheral component interconnect "always on" protocol

Also Published As

Publication number Publication date
WO1999048008A2 (en) 1999-09-23
EP0979457A2 (en) 2000-02-16

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