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WO1999046860A1 - Convertisseur a/n sigma-delta parallele au niveau pixel et a mode asynchrone pour imageurs cmos - Google Patents

Convertisseur a/n sigma-delta parallele au niveau pixel et a mode asynchrone pour imageurs cmos Download PDF

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Publication number
WO1999046860A1
WO1999046860A1 PCT/US1999/005462 US9905462W WO9946860A1 WO 1999046860 A1 WO1999046860 A1 WO 1999046860A1 US 9905462 W US9905462 W US 9905462W WO 9946860 A1 WO9946860 A1 WO 9946860A1
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WIPO (PCT)
Prior art keywords
signal
circuit
pulse
operative
pulse signal
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Application number
PCT/US1999/005462
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English (en)
Inventor
Lisa G. Mcilrath
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Northeastern University China
Northeastern University Boston
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Northeastern University China
Northeastern University Boston
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Publication of WO1999046860A1 publication Critical patent/WO1999046860A1/fr
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
    • H03M3/496—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/43—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/456—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a first order loop filter in the feedforward path

Definitions

  • On-chip analog-to-digital (A/D) conversion has been recognized as a desirable feature for CMOS image sensors, because it can reduce power and increase system integration.
  • A/D analog-to-digital
  • image sensors have been developed with column-parallel A/D conversion, such as a single-slope sensor architecture, a successive approximation architecture, and a second-order current-mode sigma-delta architecture. These designs typically require a significant amount of area and careful layout, because the pitch of the A/D converters must be matched to that of the sensor columns .
  • the architecture which is most appropriate for pixel-parallel A/D conversion is a first-order sigma-delta loop, because it can be implemented in a very small area and computations can be performed on the bit stream output before decimation with simple logic circuits.
  • n 0 (dB) e + 5.2 - 91og 2 N (2)
  • N is the oversampling ratio
  • N (2foT) -1
  • e is the root mean square quantization error from the loop A/D.
  • This equation implies that one can ideally obtain 1.5 bits of resolution for every doubling of N.
  • Many algorithms have been developed over the last three decades for recovering high resolution (multi-bit) data from sigma-delta output streams. These can be readily implemented on a digital signal processor interfaced to the imager.
  • Pixel-parallel sigma-delta A/D converter designs developed for 2D CMOS imagers are known in the art. One design is described by Boyd Fowler in his 1995 Ph.D. thesis entitled "CMOS Area Image Sensors with Pixel Level A/D -3-
  • the asynchronous architecture requires a minimal number of analog components and thus can be operated at high sampling rates with little signal-to-noise ration (SNR) degradation.
  • SNR signal-to-noise ration
  • a circuit implementation of the architecture is capable of measuring light intensities over more than 120 dB dynamic range.
  • the asynchronous design also minimizes the number of analog components that must be well matched in order to reduce fixed pattern noise, and it allows greater control of the sensitivity and frame rate of the imager.
  • An embodiment of the asynchronous sigma-delta modulator is disclosed that includes a comparator circuit whose output switches to indicate when an input signal has reached a predetermined reference level, and a latch circuit that -4 -
  • a pulse capture circuit senses the pulse signal and stores it as a logic value until sampled by a clocked output circuit.
  • Regeneration circuitry resets the input signal and the latch circuit after the pulse signal is captured by the pulse capture circuit.
  • Figure 1 is a block diagram of a canonical first-order sigma-delta modulator circuit for sampled data as is known in the prior art
  • Figure 2 is a waveform diagram illustrating the different output waveforms generated by synchronous and asynchronous modulator circuits;
  • Figure 3 is a schematic diagram of an asynchronous first-order sigma-delta A/D converter cell in accordance with the present invention
  • Figure 4 (consisting of Figures 4a, 4b and 4c) is a timing diagram of several signals in the circuit of Figure 3;
  • Figure 5 is a plot of the pixel output of the sigma- delta converter cell of Figure 3 as a function of sampling period T for constant illumination.
  • Figure 6 is a plot of the output of the sigma-delta converter cell of Figure 3 as a function of illumination at a 5 kHz sampling rate.
  • Figure 2 illustrates the outputs of both an asynchronous modulator circuit (solid line) and a -5-
  • asynchronous modulator oscillates with period (x max /x)-T, and thus the average value of the output converges to x/x max .
  • the primary advantage of the asynchronous modulator is that it is reset to a fixed level when its output level ⁇ drops to B. This is in contrast to the synchronous modulator, which requires that an accurate analog value be added back to the output upon reset. This feature of the asynchronous modulator eliminates the problem of mismatch in analog components, which is a major source of fixed pattern noise when synchronous cells are implemented in an array.
  • Figure 3 shows a schematic of an asynchronous modulator cell suitable for use in a CMOS imager with photodiode input.
  • the circuit is composed of four sections:
  • a differential amplifier/comparator formed of transistors MNDO, MNDl, MND2, MPDl, and MPD2. This circuitry continuously tests whether the photodiode voltage DIODE_IN has dropped below an assigned reference level
  • a fast path bistable circuit consisting of transistors MNLl, MPL1 and MPL2 along with set and reset transistors MPC, MRGN, and MBLK. This circuit generates a reset pulse RST for transistor MPR that brings the photodiode voltage DIODE_IN back to its initial high level after switching of the comparator has been detected.
  • a slow path regeneration circuit consisting of the pair of common-source amplifiers MPS1-MNS1 and MPS2-MNS2. This circuit controls a transistor MRGN to turn off the reset pulse RST to allow a new integration cycle to proceed.
  • a pulse capture circuit including transistors MPUL, MRST, and MBIT. This circuit senses and stores the reset pulse RST as a signal BIT until it is sampled by a -7 -
  • a transistor MOUT connected to a row select signal SEL gates the cell output onto a column bus used to read the pixel bit stream in a 2D array layout.
  • the reset transistor MPR is turned off, and the diode photocurrent passively reduces the voltage DIODE_IN on the capacitance at the gate of MNDl from a value of approximately 3 volts to a lower voltage V re __.
  • the signal DIODE_IN reaches V ref , however, it first passes through a value that is a threshold voltage below V DD .
  • the transistor MPS2 is turned on, causing the signal RG1 to rise and the signal RG2 to fall.
  • the signal RG2 reaches a value sufficient to turn off the regeneration transistor MRGN before the signal DIODE_IN reaches the reference level V ref .
  • the timing is influenced by various aspects of the circuit including the value of the reference level V ref , and may be different in alternative embodiments.
  • the comparator output quickly drops below V DD , turning on transistor MPC and raising its drain voltage BI1 towards V DD .
  • the positive feedback of the cross-coupled PMOS transistors in the half- latch MPL1-MNL1-MPL2 quickly yanks the voltage BI1 to the positive rail and forces the signal RST at the output of the inverter pair MPL1-MNL1 to ground. This assertion of the signal RST turns on both the reset transistor MPR and the pulse capture transistor MPUL.
  • MPR is conducting, the diode voltage DIODE_IN and the comparator output are returned to V DD , and the transistor MPC is turned off.
  • the high diode voltage DIODE_IN also causes the signal RG1 in the two-stage common-source amplifier pair, MPS1-MNS1 and MPS2-MNS2, to switch slowly from V DD to GND.
  • the output RG2 of the second stage MPS1-MNS1
  • the differential pair and the common-source amplifiers are biased in the weak inversion region to reduce power and maximize gain. Because of the low level of current driven by the bias transistors MNSl and MNS2, the common-source amplifiers have a slow fall time and fast rise time.
  • the time to propagate a transition from the input to the output of the regeneration circuit is long enough to ensure that the diode voltage DIODE_IN is fully reset to its initial high level before MPR is turned off. Because of the high gain and fast rise of the second stage, the low-to-high transition is very abrupt once the signal RG1 reaches the trip point, roughly V DD -V TH . This operation minimizes the time that the input latch might be held at an intermediate level, which would burn static power.
  • the pulse capture circuit is read and reset once every clock period using the signals PC, SEL and QS . If the oscillator resets during the time between two reads, MPUL turns on and a high value is stored on the gate of MBIT. -9-
  • the output bus (signal BUS) is first precharged to a high level by precharge circuitry (not shown) responsive to the signal PC.
  • precharge circuitry (not shown) responsive to the signal PC.
  • the signal SEL is asserted.
  • the bus is then discharged or not depending on the state of MBIT.
  • the signal SEL is brought low and the signal QS is brought high to reset the gate of MBIT to GND.
  • the signal QS is also applied to a blocking transistor MBLK used to prevent a pulse from occurring while the output is being reset by blocking the reset latch. It also serves to refresh the latch input from leakage due to MPC that might otherwise cause premature switching during a long integration time. It should be noted, however, that the blocking transistor is an optional component that may be omitted in alternative embodiments.
  • CMOS imager In order to build a CMOS imager, the pixels described above are arranged in a regular grid of rows and columns .
  • a row decoder designed with standard methods, is used to sample one row of the array at a time. Clock signals SEL and QS as described above are gated through the decoder onto the chosen row.
  • the pixels in each column of the array share a single bus line, which is driven by the pixel in the addressed row.
  • a standard circuit is used to precharge the bus line, which the pixel may or may not pull down depending on its state, and to latch the output bit.
  • a multiplexer is used to gate groups of column outputs, stored in the latches, onto output pins.
  • Either or both of the row and column addresses may be supplied externally or generated on-chip using counters or other address-generating circuitry.
  • the data is collected in a high-speed external memory, which is subsequently read into a computer for analysis.
  • Figures 5 and 6 illustrate some performance aspects of the sigma-delta A/D converter circuit of Figure 3.
  • Figure 5 illustrates the linear response of the pixel to changes in the sampling clock period, T, from 3.2 microseconds to 100 microseconds (corresponding to a range of sampling rates from 312.5 kHz to 10 kHz).
  • Figure 5 shows that the sigma- delta decimated and low-pass-filtered output, expressed as a fraction of saturation, is directly proportional to T, as it should be. Notably, there is no noticeable distortion at sampling rates over 300 kHz. The observed deviations in the measured values from the best line fit are attributed to variations in the light source intensity over the course of the experiment. The measured SNR at 312.5 kHz was greater than 60 dB in mid-range.
  • Figure 6 shows that the pixel response is also a linear function of incident illumination.
  • the data in Figure 6 were gathered using a sampling rate of 5 kHz and a calibrated monochromatic light source having a wavelength of 600 nm.
  • the slope of the line is related to the conversion gain of the photodiode, the value of the reference level Vr ef. and the sampling rate. It is estimated that this circuit has the potential for acquiring images with over 120 dB dynamic range with the appropriate combination of these parameters .

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

L'invention se rapporte à un circuit modulateur sigma-delta à mode asynchrone qui est susceptible de servir, par exemple, au niveau de chaque pixel d'un capteur d'images CMOS. Ledit modulateur sigma-delta asynchrone comporte un circuit comparateur (MND0), MND1, MND2, MPD1, MPD2) dont la sortie bascule pour indiquer l'instant où un signal d'entrée a atteint un niveau de référence préétabli, et un circuit de verrouillage (MNL1, MPL2, MPL2) qui délivre un signal d'impulsion lorsque la sortie du comparateur bascule. Un circuit de détection d'impulsions (MPUL, MRST, MBIT) détecte le signal d'impulsion et le mémorise comme une valeur logique jusqu'à ce qu'il soit échantillonné par un circuit de sortie de base de temps. Des circuits de régénération (MPS1, MNS1, MPS2, MNS2, MRGN) réinitialisent le signal d'entrée et le circuit de verrouillage après que le signal d'impulsion ait été détecté par le circuit de détection d'impulsions.
PCT/US1999/005462 1998-03-12 1999-03-12 Convertisseur a/n sigma-delta parallele au niveau pixel et a mode asynchrone pour imageurs cmos Ceased WO1999046860A1 (fr)

Applications Claiming Priority (2)

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US7776098P 1998-03-12 1998-03-12
US60/077,760 1998-03-12

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11218162B2 (en) 2018-03-27 2022-01-04 Koninklijke Philips N.V. Systems and methods for performing analog-to-digital conversion across multiple, spatially separated stages

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4320361A (en) * 1979-07-20 1982-03-16 Marconi Instruments Limited Amplitude and frequency modulators using a switchable component controlled by data signals
US5461425A (en) * 1994-02-15 1995-10-24 Stanford University CMOS image sensor with pixel level A/D conversion

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4320361A (en) * 1979-07-20 1982-03-16 Marconi Instruments Limited Amplitude and frequency modulators using a switchable component controlled by data signals
US5461425A (en) * 1994-02-15 1995-10-24 Stanford University CMOS image sensor with pixel level A/D conversion

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
GOES VAN DER F. M. L., MEIJER G. C. M.: "SIGMA-DELTA VERSUS OSCILLATOR-BASED CONVERTERS IN LOW-COST ACCURATE SENSOR SYSTEMS.", JOINT PROCEEDINGS OF THE IEEE INTRUMENTATION AND MEASUREMENT TECHNOLOGY CONFERENCE AND THE IMEKO TECHNICAL COMMITTEE 7. BRUSSELS, JUNE 4 - 6, 1996., NEW YORK, IEEE., US, vol. 02., 1 June 1996 (1996-06-01), US, pages 1151 - 1153., XP002920434, ISBN: 978-0-7803-3313-0 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11218162B2 (en) 2018-03-27 2022-01-04 Koninklijke Philips N.V. Systems and methods for performing analog-to-digital conversion across multiple, spatially separated stages

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