WO1999040683A1

WO1999040683A1 - A method to accomplish a high resolution digital/analog conversion and a digital/analog converter

Info

Publication number: WO1999040683A1
Application number: PCT/FI1999/000088
Authority: WO
Inventors: Juhani Sademaa
Original assignee: Nokia Telecommunications Oy; Nokia Networks Oy
Current assignee: Nokia Oyj
Priority date: 1998-02-06
Filing date: 1999-02-08
Publication date: 1999-08-12
Anticipated expiration: 2000-08-06
Also published as: FI105622B; AU2282199A; FI980272A0; FI980272L

Abstract

The invention pertains to a method for performing a digital-to-analog conversion at a high resolution and to a digital-to-analog converter. In accordance with the invention, a digital binary input is converted in a plurality of separate weighted portions, the pulse outputs of which are summed in an analog manner and low-pass filtered. In applications where the process controlled is low-pass in nature, filtering is not needed. Portioned conversion is usually performed using pulse-width modulation (PWM) and the weighted portions may also overlap.

Description

1

A method to accomplish a high resolution digital/ analog conversion and a digital/analog converter

The invention relates to a method defined in the preamble of claim 1 for performing a digital-to-analog conversion at a high resolution and a digital-to-analog converter according to claim 5.

From the prior art it is known digital-to-analog converters (DACs) comprised of a single pulse-width modulation (PWM) converter. Such DACs are used e.g. to control thermostats, electric motors and voltage-controlled oscillators (VCOs) and for automatic signal level control as well as to generate simple signaling tones.

Also known is a sigma-delta type DAC used in digital audio equipment such as laser disc players.

A problem with the known devices is that a converter based on a single PWM converter will not produce a high-resolution conversion of a high-frequency signal. For example, a 10-bit converter at a 2-MHz frequency achieves a conversion frequency of 1 kHz, which cannot be used to generate a telephone-quality analog signal.

An object of the invention is to eliminate the disadvantages mentioned above.

The method according to the invention is characterized by what is presented in claim 1. The apparatus according to the invention is characterized by what is presented in claim 5. Preferred embodiments of the invention are disclosed in the de- pendent claims.

The invention pertains to a method for performing a high-resolution digital-to-analog conversion. In accordance with the invention, a digital binary input is converted in such a manner that it is divided into a plurality of separate weighted portions the pulse outputs of which are summed in an analog manner.

In an embodiment of the method the analog sum signal is low-pass filtered. In applications where the process controlled is low-pass in nature, filtering is not needed.

In an embodiment of the method the portioned conversion is performed using pulse- width modulation.

In an embodiment of the method the weighted portions of at least two converter units are overlapped, the binary contents of the overlapping area are halved, and the halved binary contents are digitally added to initial values of counters in such a manner that one half of the overlapping area is directed to a first counter and the other half to a second counter and, finally, the analog output components are summed.

The invention also pertains to a digital-to-analog converter for performing a conversion at a high resolution. In accordance with the invention it comprises two or more converter units for the partial conversion of a binary input as well as an analog summing circuit for the weighted summing of the different converter units. The conversion is divided between a plurality of converter units the word widths of which are smaller and, hence, the conversion cycle shorter. This way, the sampling frequency of the converter entity is higher than that of a converter comprised of a single converter unit where the word width of a converter unit is greater.

In an embodiment of the digital-to-analog converter the converter units have a relatively smaller word width in the more significant range than in the less significant range. This way, the conversion accuracy of the more significant range will be higher as the computation speed and offset error caused by the different rise and fall times of the converter unit output will be smaller.

In an embodiment of the digital-to-analog converter it also comprises a low-pass filter for filtering the analog sum signal.

In an embodiment of the digital-to-analog converter the converter units are comprised of pulse-width modulation converters.

In an embodiment of the digital-to-analog converter the weighted portions of at least two converter units overlap, the binary contents of the overlapping area are halved and the halved binary contents are digitally added to initial values of counters in such a manner that one half of the overlapping area is directed to a first counter and the other half to a second counter, and it also includes a sun ing circuit for the analog output components. This reduces nonlinearity error and threshold effect at the transition points of the weighted portions. Here, suimning refers to the use of the same summing circuit as above. This embodiment requires no changes in the circuit.

In an embodiment of the digital-to-analog converter it is integrated into an application-specific integrated circuit (ASIC).

An advantage of the invention is that it facilitates a high-speed, high-resolution digital-to-analog converter with a simple circuit arrangement. Another advantage of the invention is that a converter according to the invention can be advantageously integrated into an ASIC or into a field programmable gate array (FPGA) circuit. To realize the invention in an ASIC or FPGA circuit, the circuit is preferably described using a description language such as HDL (Hardware Description Language).

Furthermore, it is an advantage of the invention that the conversion according to the invention does not involve generation and attenuation of noise at a frequency lower than the sampling frequencies, which is typical of S/D converters.

The invention will now be described in more detail with reference to the accompa- nying drawing wherein

Fig. 1 shows in a flow diagram steps of a method according to the invention,

Fig. 2 shows an arrangement for dividing a binary word according to the invention to converter units,

Fig. 3 shows a second arrangement for dividing a binary word according to the invention to converter units,

Fig. 4 shows the effect of a transition between converter units,

Fig. 5 shows a simplified circuit diagram of a digital-to-analog converter according to the invention,

Fig. 6 shows an implementation of the summing circuit in the converter units, and

Fig. 7 shows a logic diagram of a programmable logic circuit.

Fig. 1 shows steps of a method according to the invention in a flow diagram. First, a digital binary word is divided into portions one of which is directed 1 to a converter unit where said portion is D/A converted 2, and the analog conversion result is summed 3 at the output. Next, it is checked whether the whole word has been processed 4. If not, operation returns to step 1 where, this time, the next portion is directed to the next converter unit, said portion is D/A converted in the current converter unit and the analog conversion result is summed 3 at the output, where the previous result was already summed. If the word has now been processed in its entirety 4, the analog sum signal is low-pass filtered 5.

Fig. 2 shows a possible way of dividing a binary word between converter units according to the invention. The 16-bit binary word 6 is split into two 8-bit portions 7, 8. Fig. 3 shows a second possible way of dividing a binary word between converter units according to the invention. The 16-bit binary word 6 is split into three portions which comprise the six highest bits in a 6-bit byte 10, the nine lowest bits in a 9-bit byte and the seven middlemost bits in a 7-bit byte overlapping at its ends with the abovementioned bytes.

Fig. 4 shows interdependencies according to the invention between a digital binary word and output voltage. Fig. 4a illustrates the conversion into an analog voltage of a binary word portioned according to Fig. 2 to separate D/A converter units when the values of the summing resistors are not ideal. The reference curve shows at its middle section a transition as the first bit of the higher byte of the binary word changes from zero to one. Fig. 4b illustrates the conversion into an analog voltage of a binary word portioned according to Fig. 3 to separate D/A converter units when the values of the slimming resistors are not ideal. The reference curve shows no discontinuities as the effect of the D/A converter unit for the middlemost bits overlaps both the lower and the higher byte.

Fig. 5 shows a D/A converter circuit arrangement according to the invention based on a programmable gate circuit. A digital binary input 13 brings 16 bits DINO-15 to the programmable circuit 15 as data input signals. A separate oscillator circuit 14 supplies the necessary clock frequency to the input 15 XCLK of the programmable circuit 15. The programmable logic of circuit 15 distributes the data input signals in accordance with Fig. 3 to pulse-width modulators programmed in the same circuit 15, the result signals of said modulators being conducted from outputs LO OUT, MD OUT and HI OUT to the summing resistors A, B and C of the summing circuit 16 and further to the output 17 of the circuit arrangement.

Fig. 6 shows an implementation of a converter unit's summing circuit 16 in which the overall effect of the unit is dimensioned so as to be slightly attenuating. The resistor value of the summing resistor RH of the most significant counter output HI OUT is here 1.62 kΩ and the resistor value of the feedback resistor RF is 1 kΩ. The resistor values RM and RL of the other counter outputs MI OUT and LO OUT are here 12.96 kΩ and 207.4 kΩ, respectively. The summing resistors RM and RL of the latter counters are chosen according to the weight coefficients of the most significant bits of the counters. Since, in accordance with Fig. 3, the highest counter has three higher bits than the middle counter, the summing resistor RM has a resistance which is eightfold compared to the summing resistor RH, and as the highest counter has seven higher bits than the lowest counter, the summing resistor RL has a resistance which is 128 times larger than that of the summing resistor RH. The feedback resistor RF is chosen on the basis of the resistor value of the parallely connected summing resistors RH, RM, RL in such a manner that an RF resistance larger than that of the parallel connection produces the desired amplification or an RF resistance smaller than that of the parallel connection produces the desired attenuation. The summing circuit here further comprises an operational amplifier 18 such that the parallely connected summing resistors RH, RM, RL are coupled to its negative input, and its positive input is coupled to the ground potential. The output of the operational amplifier produces a sum signal SUM OUT, being coupled via the feedback resistor RF to the parallely connected summing resistors RH, RM, RL.

Fig. 7 is a general depiction of a logic diagram of a programmable logic circuit. The circuit according to the logic diagram comprises three counters the accuracies of which are 6, 7 and 9 bits. The counters overlap in such a manner that together they constitute a 16-bit counter, in other words, the counters' input vector is 16 bits wide. The input vector may come from an arbitrary source which is here ignored.

At the upper portion of Fig. 7 there is seen a 9-bit base counter 19A and control logic 19B which includes a state machine and a counter mask generator. The base counter 19A is used to deteimine the start and end times of a PWM cycle as well as the loading and stepping liming for the PWM counters together with the control logic 19B. At one side there is seen a buffer circuit 19C into which the 16-bit input vector is loaded synchronized with the PWM cycle. This input vector, which is changed preferably for each PWM cycle, determines the analog level of the converter's output proper. Timing for the control logic 19B comes from the base counter 19A. The control logic 19B gives a Ready output signal to the external device supplying the input vector when the processing of the preceding input vector has started. The Ready output signal indicates that the next input vector may be fed to the converter.

Multiplexers 19D and 19E and adders 19F and 19G process the 16-bit input vector binary line by binary line in such a manner that they produce a 22-bit binary word for counters 19H, 19J and 19K. These counters are, respectively, 6, 7 and 9 bits wide. Counters 19H, 19J and 19K are loaded through the multiplexers and adders. Loading is preferably performed alternately in order to save logic system capacity.

Counters 19H, 19 J and 19K are down-counting elements such that after the loading of the initial value they count down to zero and remain waiting for a new loading. At the moment of the loading of the initial value the one-bit pulse width output of the counter is set to the higher voltage level and when the counter value has reached zero the pulse width output is set to the lower voltage level. In addition, the counters have a logic system that loads them with a value which corresponds to the 50% level of the 16-bit input vector. In hexadecimal, this level is 7FFF. Thus the con- verter output is held at the 50% level when there is no input vector. The different counters count at different speeds allowed by their respective clock masks.

Operation of the converter is timed such that the least significant 9-bit counter 19K operates at the main clock XCLK frequency 16.38 MHz. The 7-bit middle counter 19J operates at a quarter of the main clock frequency because this counter has two bits less than the widest counter. The most significant 6-bit counter 19H operates at an eighth of the main clock frequency since this counter has three bits less than the widest counter. Thus the counting periods of the counters, i.e. the count from the full initial value to zero, are equally long. Here the counting period consists of 512 clock cycles of the main clock XCLK, which is 31.25 μs and corresponds to an operating frequency of 32 kHz.

As the arithmetic blocks, i.e. multiplexers 19D and 19E and adders 19F and 19G operate alternately, also the loadings of counters 19H, 19 J and 19K alternate, taking place preferably at intervals of two main clock cycles. Therefore, the counts of counters 19H, 19 J and 19K are partly overlapped in time. The loading and counting of counters 19H, 19 J and 19K are performed timed by three mask signals such that each signal keys the clock signal input of the corresponding counter 19H, 19J or 19K. The alternate use of the arithmetic blocks for the loading of counters 19H, 19J and 19K is realized by controlling the multiplexers 19D and 19E with timing signals from the control logic 19B. The most significant counter 19H is loaded direct from the buffer 19C.

Multiplexers 19D and 19E produce two binary line components which are summed by adders 19F and 19G so that they further comprise part of the values loaded into counters 19 J and 19K. Multiplexer 19E produces the halved overlapping portion of the values loaded into two counters. Halving is preferably performed by right- shifting the bits. The overlapping bits of the higher one of the partly overlapping counters are loaded one bit line lower than normal, and a zero is set into the highest line. Multiplexer 19D produces in the lower one of the partly overlapping counters 19J and 19K a portion that comprises the bit which would otherwise be lost in the right-shift and padding zeros. This portion and the portion produced earlier as de- scribed above are summed in two consecutive adders 19F and 19G in such a manner 7

that the lower overlapping counter 19K receives the highest bits without any data loss. The rest of the bits are loaded direct from the buffer 19C into counters 19 J and 19K.

As an example, let us consider the conversion of a 16-bit digital audio signal for analog circuits. The audio signal is sampled at a 32-kHz sampling rate and the samples are read at that same rate into a buffer 19C of a digital-to-analog converter according to the invention. The bits of the samples are loaded in the manner described above into counters 19H, 19J and 19K which quickly count down from their initial values to zero, which means the pulse width is small and a new sample can be processed soon. The pulse outputs of counters 19H, 19J and 19K are summed preferably by means of a circuit according to Fig. 6 and filtered using capacitive components, for example.

For frequencies higher than the sampling frequency the digital-to-analog converter according to the invention causes harmonic components of the sampling frequency which often have to be filtered out.

The invention is not limited to the aforementioned embodiments but many modifications are possible without departing from the scope of the inventional idea defined by the appended claims.

Claims

1. A method for performing a digital-to-analog conversion at a high resolution, characterized in that a digital binary input is converted in a plurality of separate weighted portions the pulse outputs of which are summed in an analog manner.

2. The method of claim 1, characterized in that the analog sum signal is low- pass filtered.

3. The method of claim 1 or 2, characterized in that the portioned conversion is performed using pulse-width modulation.

4. The method of claim 1, characterized in that the weighted portions of at least two converter units are overlapped, the binary contents of the overlapping area are halved, and the halved binary contents are digitally added to the initial values of the counters in such a way that one half of the overlapping area is directed to a first counter and the other half to a second counter and, finally, the analog output components are summed.

5. A digital-to-analog converter for performing a high-resolution conversion, characterized in that it comprises two or more converter units for the partial conversion of a binary input and an analog summing circuit for the weighted summing of the different converter units.

6. The digital-to-analog converter of claim 5, characterized in that in the more significant range the converter units have a relatively smaller word width than in the less significant range.

7. The digital-to-analog converter of claim 5 or 6, characterized in that it further comprises a low-pass filter for the analog sum signal.

8. The digital-to-analog converter of claim 5, 6 or 7, characterized in that the converter units are comprised of pulse-width modulation converters.

9. The digital-to-analog converter of claim 5, 6, 7 or 8, characterized in that the weighted portions of at least two converter units overlap, the binary contents of the overlapping area are halved and the halved binary contents are digitally added to the initial values of counters in such a manner that one half of the overlapping area is directed to a first counter and the other half is directed to a second counter and, finally, it includes a summing circuit for the analog output components.

10. The digital-to-analog converter of any one of the preceding claims 5 to 9, characterized in that it is integrated into an application-specific integrated circuit.