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WO1998036453A1 - Dispositif d'accord programmable base sur un transistor bipolaire de siliciure au polysilicium - Google Patents

Dispositif d'accord programmable base sur un transistor bipolaire de siliciure au polysilicium Download PDF

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Publication number
WO1998036453A1
WO1998036453A1 PCT/CA1998/000114 CA9800114W WO9836453A1 WO 1998036453 A1 WO1998036453 A1 WO 1998036453A1 CA 9800114 W CA9800114 W CA 9800114W WO 9836453 A1 WO9836453 A1 WO 9836453A1
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WO
WIPO (PCT)
Prior art keywords
layer
emitter
filament
base
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CA1998/000114
Other languages
English (en)
Inventor
Andrew V. C. Cervin-Lawry
James D. Kendall
Petrus T. Appelman
Efim Roubakha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gennum Corp
Original Assignee
Gennum Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CA002197627A external-priority patent/CA2197627C/fr
Priority claimed from US08/820,475 external-priority patent/US5920771A/en
Application filed by Gennum Corp filed Critical Gennum Corp
Priority to EP98902912A priority Critical patent/EP0960439B1/fr
Priority to AU59790/98A priority patent/AU5979098A/en
Priority to DE69818227T priority patent/DE69818227T2/de
Priority to US09/331,575 priority patent/US6218722B1/en
Priority to JP53519198A priority patent/JP2001511949A/ja
Priority to AT98902912T priority patent/ATE250281T1/de
Publication of WO1998036453A1 publication Critical patent/WO1998036453A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/645—Combinations of only lateral BJTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • This invention relates to programmable antifuses and to methods of making the same.
  • Antifuses have been known for some time and are disclosed for example in U.S. patents 3,191,151; 3,742,592; 5,019,878; and 5,298,784. Antifuses are devices which have a high impedance before programming and a low impedance after programming, and are used widely in integrated circuit structures. An antifuse is the converse of a fuse, which can be employed in a similar manner. Use of an antifuse permits the tuning of various analog circuit parameters, the programming of digital logic, and the selection of certain pieces of redundant circuitry.
  • An exemplary application for antifuses (given by way of example only) is to switch desired resistances into a voltage controlled oscillator (VCO), so that the center frequency and range of the VCO will be within desired specifications.
  • VCO voltage controlled oscillator
  • Antifuses can be formed from transistor or diode structures which normally have a high impedance when reverse biased.
  • the appropriate PN junction of the device can be shorted by applying a large reverse bias, causing part of the junction to melt and causing the metal which contacts the junction to flow into the molten region, thereby creating a low impedance metal filament.
  • Conventional antifuse structures typically require a relatively high programming voltage and energy, which may cause damage to the remainder of the integrated circuit in which the antifuse is located. It is therefore an object of the invention to provide an improved antifuse structure, and a method of forming an antifuse, which require a lower programming voltage and energy than have typically been the case in the past.
  • the invention provides a method of making an antifuse comprising:
  • an antifuse comprising:
  • an emitter structure overlying said base layer, said emitter structure projecting above said base layer and having a sidewall extending above said base layer, said emitter structure also having an upper surface, (iv) a narrow oxide spacer ring surrounding said side wall of said emitter structure, (v) a first conductive suicide layer on said upper surface of said base layer, surrounding said spacer ring, and a second conductive suicide layer on said upper surface of said emitter structure,
  • the invention provides a method of making an antifuse comprising: (a) selecting a polysilicon bipolar transistor comprising:
  • the invention provides an antifuse comprising:
  • An antifuse comprising: (a) a suicided polysilicon bipolar transistor structure comprising a collector, emitter and base, said emitter having a sidewall and a narrow spacer oxide ring surrounding said sidewall, said emitter including a first polysilicon layer and said base including a second polysilicon layer.
  • Fig. 1 is a cross-sectional view showing a prior art antifuse
  • Fig. 2 is a graph showing the breakdown characteristic of the base emitter diode of the Fig. 1 structure
  • Fig. 3 is a cross-sectional view showing an antifuse according to the invention, with the left side showing the structure before programming and the right side showing the structure after programming;
  • Fig. 4 is a schematic showing the arrangement used to program antifuses of the invention.
  • Fig. 5A is a plot showing the voltage pulse applied to program the antifuse device of Fig. 2 and also showing the voltage at the input of the device;
  • Fig. 5B is a plot similar to that of Fig. 5A but showing voltages applied after the device has been programmed;
  • Fig. 6 shows the distribution of the emitter-base breakdown voltages for a set of functional discrete transistors of the kind shown in Fig. 2, before programming;
  • Fig. 7A shows the impedances of the devices referred to in connection with Fig. 6, after programming;
  • Fig. 8 shows the entire population of the sample programmed
  • Fig. 9 shows the mean impedance after programming at a range of bias currents
  • Fig. 10 is a cross-sectional view showing the invention as applied to a double polysilicon bipolar transistor.
  • Fig. 1 shows a planar diffused bipolar transistor 10 of the kind shown in U.S. patent 3,191,151, and having a collector 12, a base 14 and an emitter 16.
  • the base-emitter junction 18 serves as an approximation to an electrical open circuit, thereby constituting the OFF state of the antifuse.
  • Fig. 2 which plots base current against base-emitter voltage, the normal reverse leakage current under reverse bias is indicated at 20.
  • the base- emitter voltage becomes high enough, electrical breakdown occurs, as indicated at 22.
  • a metal filament indicated by arrow 30 (Fig. 1) is formed between the metallic base and emitter contacts 24, 26.
  • the filament serves as an approximation to an electrical short, and constitutes the ON state of the antifuse. This is indicated by region 31 of Fig. 2.
  • the transistor 10 is formed primarily by lithographic steps, the accuracy of which is inherently limited.
  • the base 14 and emitter 16 are superimposed on the collector 12, and the oxide layers 32a, 32b are formed, all through the use of lithographic steps.
  • the total length of the metal filament indicated by arrow 30 is typically between 4 and 5 microns. The voltage, current and total energy required to create a filament of this length are relatively high, resulting in the potential for damage to surrounding circuit elements.
  • the base emitter junction of a silicided single polysilicon bipolar transistor 40 (Fig. 3) is used as an antifuse.
  • this arrangement allows the distance between the metals on the base and emitter regions to be reduced by approximately a factor of five, and this distance is better controlled since it is defined by self aligned processing steps.
  • the shorter distance between the base and emitter metals in the silicided single polysilicon bipolar transistor 40 serves to lower the applied voltage and energy required to switch the antifuse from its OFF state to its ON state by a factor of approximately two, as compared to a planar diffused bipolar transistor.
  • the lower programming voltage is a substantial advantage, because in the process of programming the antifuse, the surrounding circuitry is much less likely to be damaged.
  • the transistor 40 is constructed as follows. Firstly, the base region 42 (shown as a P-type region but the types can be reversed) is implanted into an n-epitaxial or n-well region 44 of monosilicon. Next, n-type polysilicon is deposited and patterned on top of the base region 42 to form the emitter 46. These steps are, as usual, lithographic steps.
  • a layer of silicon dioxide (not shown) is deposited by chemical vapor deposition and is then subjected to anisotropic plasma etching, resulting in a ring-shaped sidewall oxide spacer 50 encircling the sidewall 52 of the emitter 46.
  • anisotropic plasma etching of an oxide layer (as shown by U.S. patent 5,019,878) that the thinner portions of the oxide layer are removed during the etching process, but that an oxide ring remains from the thicker portion where a feature projects above the surrounding surface.
  • the radial dimensions of the sidewall ring 50 (as shown by dimension " ⁇ " in Fig. 3) are well defined by the process step and are not defined by a lithographic step.
  • the exposed emitter polysilicon 46, and the base silicon 42 are silicided by depositing one of the following metals at elevated temperature: Co, Mo, Ni, Pt, Ta, Ti or W (Pt is shown as an example).
  • metals such as an example.
  • these metals react with all exposed silicon to form a suicide, but they do not react with the silicon dioxide layer or sidewall ring 50. Consequently, etchants can be used to remove the unreacted metal and leave the suicide in place.
  • the transistor 40 shown in Fig. 3 is fabricated. As shown, the transistor 40 in Fig. 3 now has a low resistivity contact (e.g.
  • the emitter 46 56 on the emitter 46, and a surrounding low resistivity contact layer 58 (e.g. of platinum suicide) on the base 42, with only a short distance between these two contacts, defined by the oxide ring or sidewall spacer 50.
  • a controlled programming voltage is applied between the contacts 56, 58, electrical and then thermal breakdown occur between the base 42 and the emitter 46, causing a suicide filament 60 (e.g. platinum suicide) to grow.
  • the height or dimension " ⁇ " of the sidewall oxide spacer 50 is about 0.4 microns, and its thickness in the radial dimension "r" is about 0.25 microns, so the total length of the filament 60 is about 0.65 microns, while its width is typically about 0.35 microns.
  • a measuring instrument 64 is connected to transistor 40 (drawn for convenience as a zener diode) to measure the emitter-base breakdown voltage of transistor 40.
  • a voltage pulse was applied from voltage supply 66 through a 250 ohm current limiting resistor 68 to the emitter-base junction.
  • the breakdown voltage was approximately 5 volts (this varied slightly from device to device), and that a voltage pulse of 9 volts superimposed on the breakdown voltage (total approximately 14 volts) was optimum for producing the filament 60.
  • Fig. 5A shows a plot of the voltage pulse versus time used to form the antifuse (i.e. the filament 60).
  • the top trace 70 shows the pulse applied by the voltage source 66 at terminal A of the current limiting resistor 68.
  • the bottom trace 72 shows the voltage at the input terminal 58 of the device, namely the emitter-base voltage.
  • the voltage pulse was of about 5 milliseconds duration, with a rise time (shown by curve portion 74) of approximately 150 microseconds. It will be seen from the portion 74 of plots 70, 72 that the entire antifuse process (the formation of the filament 60) occurs within the short rise time of the pulse 70.
  • Fig. 5B shows the same pulse applied to the device 40 after formation of the antifuse.
  • the top trace 78 shows the voltage pulse applied to the top terminal A, while the lower trace 80 shows the voltage pulse applied to the emitter 58, i.e. the emitter-base voltage. It will be seen that no further changes to the junction are observed from this pulse, i.e. the filament 60 has already been formed and no further filaments are formed.
  • Fig. 6 displays a curve 82 showing the emitter-base breakdown voltage distribution for a number of functional discrete transistors 40 before the filament forming voltage pulse 74 was applied. It will be seen that the mean emitter-base breakdown voltage was approximately 5 volts, but that there was (as would be expected) a fairly substantial variation from this level. The voltage pulse applied was, as mentioned, 9 volts plus the measured emitter-base breakdown voltage.
  • Fig. 7 shows the data for the impedances at a 50 microampere bias current with the number of devices plotted on the vertical axis and the impedance on the horizontal axis.
  • Curve 84 plots the average of the impedances found.
  • the mean impedance was approximately 73 ohms with a standard deviation of 16 ohms. This was a relatively low impedance, bearing in mind that the impedance before formation of the filament 60 was nearly that of an open circuit.
  • Fig. 8 shows the entire population of the sample shown in Fig. 7. The number of devices appears on the vertical axis and the impedance on the horizontal axis. It will be seen that there are three outlying devices 90, 92 and 94 between 600 and 800 ohms. This indicates that a small percentage of the devices subjected to the filament forming voltage pulse will exhibit a partial antifuse characteristic. This appeared to indicate process flaws or structural differences in the transistors in question and is indicative of some yield loss during production, in the samples tested.
  • Fig. 9 plots at 100 the mean impedance (on the vertical axis) at each bias current (on the horizontal axis) for typical devices after the antifuse filament 60 was formed. It will be seen that the impedance drops from 72.9 ohms at 50 microamps bias current to 70.9 ohms at 200 microampere bias current. This relatively small variation does not cause difficulty in use.
  • pulses of less than 12 volts total were not sufficient to create the antifuse filament, while pulses greater than about 15 volts total (5 volts breakdown voltage plus 10 volts superimposed) tended to create junctions having much higher resistances (more than 300 ohms and increasing with voltage).
  • pulses of approximately 14 volts (9 volts plus the breakdown voltage) were ideal.
  • a single polysilicon bipolar transistor has been described, if desired the invention may also be applied to a double polysilicon bipolar transistor.
  • Such a transistor is shown at 110 in Fig. 10 and includes base, emitter and collector metal contacts 112, 114, 116, respectively.
  • the base, emitter and collector polysilicon is shown at 118, 120 and 122, respectively.
  • the transistor 110 also includes a monocrystalline extrinsic base 124 (of p material), and conventional silicon dioxide layers 126, 128 on a substrate 130. (Layers 126, 128 are the interlayer dielectric and field oxide layers respectively.)
  • the transistor 110 as so far described is conventional.
  • these layers are silicided by depositing (e.g. by sputtering) a layer of metal (e.g. platinum) over the surface of the wafer at elevated temperatures, thus forming a suicide with the exposed silicon but not with the silicon dioxide layer which is exposed.
  • a layer of metal e.g. platinum
  • the wafer is then treated with an agent (e.g. a strong acid) to remove the unreacted metal, leaving the silicided layers which are shown at 136, 138 and 140.
  • an agent e.g. a strong acid
  • a ring-shaped sidewall oxide spacer 142 is formed, encircling a sidewall of the emitter poly crystalline 120 (exactly as in the Fig. 3 arrangement). Since the radial dimensions of the sidewall spacer or ring 142 are defined by a process step (anisotropic etching) and not by a lithographic step, these dimensions are (as previously mentioned) very well defined.
  • a silicide filament 146 (a metal silicide, e.g. platinum silicide) to grow.
  • the filament 146 is of necessity longer than the silicide filament 60 of Fig. 3, because of the need for the filament to grow through a number of layers, namely, the emitter polysilicon layer 120, the monocrystalline silicon emitter layer 148, the extrinsic base 124, and the base polysilicon 118.
  • the filament 146 is approximately 50% longer than the filament 60 in the Fig. 3 version, it is nevertheless much shorter than in the prior art. While the voltage or current pulse needed to form the filament 146 will be larger than those needed for the filament 60, again they will be relatively low and well defined.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Dispositif d'accord programmable amélioré mettant en application la jonction base-émetteur d'un transistor bipolaire unique (40) de siliciure au polysilicium. La distance entre le métal de base et le métal d'émetteur est raccourcie, ce qui permet d'effectuer des étapes d'auto-alignement plutôt que des étapes lithographiques et d'obtenir une tension de programmation inférieure et mieux commandée, une énergie de programmation et une résistance à l'état passant améliorées. Le filament conducteur (146) constitué sur ce nouveau dispositif d'accord programmable présente normalement une longueur de 0,65 microns et est crée par une impulsion de tension, dont le temps de montée est relativement lent (par exemple, 150 microsecondes), ce qui se traduit par des propriétés améliorées présentant des avantages pour l'élaboration du circuit, ainsi que pour sa fabrication au moyen de ce nouveau dispositif. On peut utiliser une technique semblable avec un double transistor bipolaire au polysilicium (110).
PCT/CA1998/000114 1997-02-14 1998-02-13 Dispositif d'accord programmable base sur un transistor bipolaire de siliciure au polysilicium Ceased WO1998036453A1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP98902912A EP0960439B1 (fr) 1997-02-14 1998-02-13 Dispositif d'accord programmable base sur un transistor bipolaire de siliciure au polysilicium
AU59790/98A AU5979098A (en) 1997-02-14 1998-02-13 Antifuse based on silicided polysilicon bipolar transistor
DE69818227T DE69818227T2 (de) 1997-02-14 1998-02-13 Antisicherung gegrundet auf einem silicid-polysilicium-bipolartransistor
US09/331,575 US6218722B1 (en) 1997-02-14 1998-02-13 Antifuse based on silicided polysilicon bipolar transistor
JP53519198A JP2001511949A (ja) 1997-02-14 1998-02-13 シリサイド化ポリシリコンバイポーラトランジスタに基づく逆ヒューズ
AT98902912T ATE250281T1 (de) 1997-02-14 1998-02-13 Antisicherung gegrundet auf einem silicid- polysilicium-bipolartransistor

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CA002197627A CA2197627C (fr) 1997-02-14 1997-02-14 Element anti-fusion base sur un transistor bipolaire a polysilicium unique, a base de siliciures
CA2,197,627 1997-02-14
US08/820,475 US5920771A (en) 1997-03-17 1997-03-17 Method of making antifuse based on silicided single polysilicon bipolar transistor

Publications (1)

Publication Number Publication Date
WO1998036453A1 true WO1998036453A1 (fr) 1998-08-20

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7679426B2 (en) 2005-01-19 2010-03-16 Hewlett-Packard Development Company, L.P. Transistor antifuse device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985003599A1 (fr) * 1984-02-09 1985-08-15 Ncr Corporation Cellule de memoire morte programmable et son procede de fabrication
GB2222024A (en) * 1988-08-18 1990-02-21 Stc Plc Programmable integrated circuits
US5208177A (en) * 1992-02-07 1993-05-04 Micron Technology, Inc. Local field enhancement for better programmability of antifuse PROM
US5316971A (en) * 1992-09-18 1994-05-31 Actel Corporation Methods for programming antifuses having at least one metal electrode
US5565702A (en) * 1994-08-19 1996-10-15 Kawasaki Steel Corporation Antifuse element, semiconductor device having antifuse elements, and method for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985003599A1 (fr) * 1984-02-09 1985-08-15 Ncr Corporation Cellule de memoire morte programmable et son procede de fabrication
GB2222024A (en) * 1988-08-18 1990-02-21 Stc Plc Programmable integrated circuits
US5208177A (en) * 1992-02-07 1993-05-04 Micron Technology, Inc. Local field enhancement for better programmability of antifuse PROM
US5316971A (en) * 1992-09-18 1994-05-31 Actel Corporation Methods for programming antifuses having at least one metal electrode
US5565702A (en) * 1994-08-19 1996-10-15 Kawasaki Steel Corporation Antifuse element, semiconductor device having antifuse elements, and method for manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SHACHAM-DIAMAND Y: "FILAMENT FORMATION AND THE FINAL RESISTANCE MODELING IN AMORPHOUS-SILICON VERTICAL PROGRAMMABLE ELEMENT", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 40, no. 10, 1 October 1993 (1993-10-01), pages 1780 - 1788, XP000403559 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7679426B2 (en) 2005-01-19 2010-03-16 Hewlett-Packard Development Company, L.P. Transistor antifuse device

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