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WO1998036341A1 - Circuit a miroir de courant, a geometrie ajustee et auto-compensation - Google Patents

Circuit a miroir de courant, a geometrie ajustee et auto-compensation Download PDF

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Publication number
WO1998036341A1
WO1998036341A1 PCT/US1997/002355 US9702355W WO9836341A1 WO 1998036341 A1 WO1998036341 A1 WO 1998036341A1 US 9702355 W US9702355 W US 9702355W WO 9836341 A1 WO9836341 A1 WO 9836341A1
Authority
WO
WIPO (PCT)
Prior art keywords
current
voltage
field effect
effect transistor
supplying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1997/002355
Other languages
English (en)
Inventor
Ranjeet Alexis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to AU19592/97A priority Critical patent/AU1959297A/en
Priority to PCT/US1997/002355 priority patent/WO1998036341A1/fr
Publication of WO1998036341A1 publication Critical patent/WO1998036341A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • This invention relates to circui try for controlling the value of currents and, more particu larly , to methods and apparatus for prov id ing improved current mi rroring circuitry.
  • a problem with such a feedback scheme is that it produces an inherent mi smatch i n the drain voltages of the mirroring transistors and a degradation of the accuracy of the mirror.
  • circuitry which will produce a more accurate self-compensating arrangement for current mirroring.
  • a current mirror circuit It is desirable for a current mirror circuit to be able to mirror currents very accurately within its designed range of operation yet continue to mirror current with acceptable accuracy outside the designed range of operation.
  • an object of the present invention to provide apparatus and a method for mirroring current very accurately within a designed operational range of voltages.
  • apparatus which includes a first current mirroring circuit which is used to provide a precise mirroring of currents using a unique negative feedback circuit.
  • the current mirroring arrangement uses field effect transistor devices with unequal dimensions which allow the inequalities produced by self- compensation to be eliminated.
  • the first current mirroring circuit may also be used with a second current mirroring circuit and means for enabling one or the other of the circuits depending on the voltage range in which the circuits are operating.
  • the first current mirroring circuit may be used in a higher of two possible voltage ranges.
  • the second current mirroring circuit is more standard in form and is switched into operation in place of the first circuit to provide a mirroring of currents when the supply voltage falls into a lower of the two possible voltage ranges.
  • the combined circuit provides mirroring of currents across a number of possible ranges of the system while providing very precise self-compensating current mirroring in the higher voltage range.
  • Figure 1 is a block diagram of a computer system which may utilize the present invention.
  • Figure 2 is a block diagram of a self-compensating current mirroring circuit designed in accordance with the present invention.
  • Figure 3 is a block diagram of a current mirroring circuit designed in accordance with the present invention.
  • the manipulations performed are often referred to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary or desirable in most cases in any of the operations described herein which form part of the present invention; the operations are machine operations.
  • Useful machines for performing the operations of the present invention include general purpose digital computers or other similar devices. In all cases the distinction between the method operations in operating a computer and the method of computation itself should be borne in mind.
  • the present invention relates to a method and apparatus for operating a computer in processing electrical or other (e.g. mechanical, chemical) physical signals to generate other desired physical signals.
  • FIG. 1 there is illustrated a block diagram of a digital system 10 configured in accordance with one embodiment of the present invention.
  • the present invention has application in any system, including a computer system, utilizing circuitry in which a current is to be very precisely mirrored.
  • the system 10 illustrated includes a central processing unit 1 I which executes the various instructions provided to control the operations of the system 10.
  • the central processing unit 11 is typically joined by a processor bus to a bridge circuit 14 which controls access to an input/output bus 12 adapted to carry information between the various components of the system 10.
  • the bridge 14 is also typically joined by a memory bus to main memory 13 which is typically constructed of dynamic random access memory arranged in a manner well known to those skilled in the prior art to store information during a period in which power is provided to the system 10.
  • the bus 12 is preferably a peripheral component interface (PCI) bus or other local bus adapted to provide especially fast transfers of data.
  • PCI peripheral component interface
  • various input/output devices are connected as bus master and bus slave circuits to the bus
  • a flash EEPROM memory array is one instance in which the present invention finds use in a computer system.
  • a flash EEPROM memory array is constructed of a large plurality of floating-gate metal-oxide- silicon field effect transistor devices arranged as memory cells in typical row and column fashion with circuitry for accessing individual cells and placing the memory transistors of those cells in different memory conditions. Such memory transistors may be programmed by storing a charge on the floating gate. This charge remains when power is removed from the array. The charge level may be detected by interrogating the devices.
  • reference cells In order to detect the value of the charges stored in one type of flash memory manufactured by Intel Corporation of Santa Clara, California, reference cells are provided which utilize additional flash EEPROM transistor devices to furnish reference currents to each of the sensing outputs of each word. The current through the flash storage cells is compared with these reference currents through the flash reference cells to determine whether a "zero" or a "one" condition exists in the flash storage cells. Since these reference currents are used to measure the state of the storage cells, these currents must be very precise in value. In one particular flash EEPROM memory array, in order to reduce the die area used by reference cells, current from a single reference cell is mirrored a number of times to provide identical reference currents for each of sixteen sensing cells used to generate a word wide output.
  • FIG. 2 is a circuit diagram illustrating a basic configuration of a self-compensating current mirroring circuit 20 which may be used in circuitry furnishing reference currents for flash EEPROM memory arrays as well as in other circuits.
  • the circuit 20 includes a pair of identically-sized P type field effect transistor devices 21 and 22 having their source and gate terminals joined so that the voltages applied to these terminals are identical. With this configuration and appropriate biasing values to cause the devices to be operated in saturation, current from a flash EEPROM reference device 24 will produce identical currents in the two devices 21 and 22 and a N type transistor device 25.
  • Variations in temperature, noise, or other ambient conditions in the circuit 20 may cause the current through the two devices 21 or 22 to vary with respect to the other.
  • a P type field effect transistor device 23 is connected with its source and drain terminals in the current path between the flash device 24 and the device 21 and with its gate terminal at the drain terminal of the device 22.
  • This arrangement provides negative feedback which corrects for changes in ambient conditions. For example, if the voltage at the drain of the device 23 increases, the voltage at the drain of the device 21 will also increase. Increasing the voltage at the drain of the device 21 increases the voltage at the gate of the device 22, decreasing the voltage at the gale of the device 23 and reducing the level of the voltage at the drain of the device 21.
  • the change in voltage at the gate of the device 23 changes the current through the device 21 in the same manner. This feedback assures that accurate current mirroring occurs over the operational range of the devices.
  • the voltage at the drains of the two devices 21 and 22 are not equal but vary by the amount of the voltage drop between the source and gate terminals of the device 23. This means that the currents through the two devices are not, in fact, exactly equal because even in saturation the current through a device is a function of the drain voltage. Most designers simply ignore this difference. However, there are many situations such as those involved in accurately sensing the values of memory cells in which it may be desirable to provide more precise current mirroring.
  • the present invention provides equal currents through the mirroring transistors 21 and 22 by a unique approach. Rather than using identical devices 21 and 22, the dimensions of these devices are made sufficiently different to compensate for the difference in the voltages at the drain terminals of the two devices. This causes the currents through the devices 21 and 22 to be identical and restores the precise current mirroring of the non-compensated circuit.
  • the device 21 was designed with a length of five microns and a width of 150 microns while the device 22 was designed with a length of five microns and a width of 140 microns. Operating in a range in which the voltage Vcc was five volts, the circuit 20 provides the identical currents desired.
  • FIG. 3 is a block diagram of a circuit 30 designed in accordance with the present invention to allow current mirroring to take place with a plurality of different supply voltages Vcc.
  • the circuit 30 mirrors a voltage provided across a flash EEPROM memory device 31 when an enabling signal is provided at the gate terminal of the device 31.
  • a signal having a positive value is provided by a detector circuit 34 causing a pair of transmission gates 35 and 36 to switch current from the device 31 through a first current mirroring circuit 32 essentially identical to the circuit described in Figure 2.
  • the current through the device 31 thus is transferred between ground and the voltage Vcc through a compensating P type device 23a and a P type device 21a.
  • the compensating device 23a will maintain these currents equal although ambient conditions of the circuit 30 change.
  • the current through the device 22a flows to ground through a type transistors device 37.
  • the current through the device 37 provides a reference voltage level which may be used in a particular embodiment to provide an input to a sense amplifier of a flash EEPROM memory array.
  • a digital signal of a negative value is provided by the detector circuit 34 causing the transmission gates 35 and 36 to switch the current from the device 31 through a second current mirroring circuit 38.
  • the circuit 38 includes a pair of identical P type transistor devices 40 and 42 connected in a standard non-compensated current mirroring arrangement. As will be seen, current through the flash device 31 is transferred through the device 40 and mirrored through the device 42 to provide the desired reference potential at the output.
  • the present invention allows precise control of current values with compensation for ambient conditions in a first operating range but continues to provide uncompensated mirrored currents suitable for operation in the second range of operation.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

L'invention concerne un circuit à miroir de courant et auto-compensation. Ce circuit comprend un premier et un deuxième dispositifs à transistors (21 et 22), respectivement assemblés dans la trajectoire d'un courant devant être réfléchi, et la trajectoire d'un courant réfléchi. Le premier dispositif à transistors (21) est en circuit avec un dispositif à transistors à compensation (23). Les tailles des premier et deuxième dispositifs à transistors (21 et 22) sont tels que les courants qui les parcourent sont maintenus à des niveaux identiques pendant le fonctionnement.
PCT/US1997/002355 1997-02-12 1997-02-12 Circuit a miroir de courant, a geometrie ajustee et auto-compensation Ceased WO1998036341A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU19592/97A AU1959297A (en) 1997-02-12 1997-02-12 Self-compensating geometry-adjusted current mirroring circuitry
PCT/US1997/002355 WO1998036341A1 (fr) 1997-02-12 1997-02-12 Circuit a miroir de courant, a geometrie ajustee et auto-compensation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1997/002355 WO1998036341A1 (fr) 1997-02-12 1997-02-12 Circuit a miroir de courant, a geometrie ajustee et auto-compensation

Publications (1)

Publication Number Publication Date
WO1998036341A1 true WO1998036341A1 (fr) 1998-08-20

Family

ID=22260376

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/002355 Ceased WO1998036341A1 (fr) 1997-02-12 1997-02-12 Circuit a miroir de courant, a geometrie ajustee et auto-compensation

Country Status (2)

Country Link
AU (1) AU1959297A (fr)
WO (1) WO1998036341A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4300091A (en) * 1980-07-11 1981-11-10 Rca Corporation Current regulating circuitry
US4629973A (en) * 1983-07-11 1986-12-16 U.S. Philips Corporation Current stabilizing circuit operable at low power supply voltages

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4300091A (en) * 1980-07-11 1981-11-10 Rca Corporation Current regulating circuitry
US4629973A (en) * 1983-07-11 1986-12-16 U.S. Philips Corporation Current stabilizing circuit operable at low power supply voltages

Also Published As

Publication number Publication date
AU1959297A (en) 1998-09-08

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