[go: up one dir, main page]

WO1998023997A1 - Affichage a cristaux liquides et a transistor a couche mince et son procede de fabrication - Google Patents

Affichage a cristaux liquides et a transistor a couche mince et son procede de fabrication Download PDF

Info

Publication number
WO1998023997A1
WO1998023997A1 PCT/KR1996/000279 KR9600279W WO9823997A1 WO 1998023997 A1 WO1998023997 A1 WO 1998023997A1 KR 9600279 W KR9600279 W KR 9600279W WO 9823997 A1 WO9823997 A1 WO 9823997A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor layer
gate line
layer pattern
tft
lcd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR1996/000279
Other languages
English (en)
Inventor
Chul Ha Kim
Young Woo Seo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orion Electric Co Ltd Korea
Original Assignee
Orion Electric Co Ltd Korea
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Orion Electric Co Ltd Korea filed Critical Orion Electric Co Ltd Korea
Publication of WO1998023997A1 publication Critical patent/WO1998023997A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present invention relates to a liquid crystal display (LCD) employing a thin film transistor (TFT) as its switching device and a method of fabricating the same.
  • LCD liquid crystal display
  • TFT thin film transistor
  • the present invention relates to a TFT-LCD employing a bottom-gate TFT whose gate electrode is formed under its channel and a method of fabricating the same, in which a semiconductor layer pattern is formed in such a manner that a portion of the semiconductor layer pattern to be a channel in the TFT is superposed on top of a gate line, and the other portion of the semiconductor layer pattern is superposed on a data line with the gate line in order to simplify its process, prevent the gate line and data line from short-circuiting, increase the pixel aperture ratio by reducing the area occupied in the TFT, and reduce the leakage current by forming an offset region or LDD region in the source and drain junction region, thereby increasing the aperture rate and improving the production yield and reliability of the device.
  • An LCD a kind of flat panel display, forms a picture using the brightness level obtained by applying an electric field to a liquid crystal having the fluidity of liquid and the optical characteristics of crystal, and changing the optical anisotropy of the liquid crystal.
  • LCDs such as a twisted nematic (TN) LCD, super twisted nematic LCD or ferroelectric LCD.
  • TN twisted nematic
  • a TFT-LCD which includes a TFT of a switching element of the pixel, is widely used.
  • the LCD is available in a wider range than the conventional CRT since it has an easily formed compact structure, a lower rate of power consumption, a higher definition in color and greater size. Recently, the TFT-LCD has drawn attention because it has a faster response time and greater picture quality than the conventional CRT.
  • a conventional LCD is constructed in a type of liquid crystal that is sealed between upper and bottom substrates on which each of the transparent electrode pattern are formed.
  • the LCD includes a transparent pixel electrode pattern formed of indium tin oxide (ITO) or Sn0 2 formed on the upper and bottom substrates made of a transparent material such as quartz, glass or plastic film, an insulating protective film for insulating the transparent electrode pattern, and an alignment film for directing the liquid crystal in a predetermined direction.
  • the alignment film has valleys in a predetermined direction thereon. Thus, the film has an orientation. The valleys are formed in such a manner that the orientation film is rubbed by a rubbing roll of cylindrical core surrounded by a texture.
  • a color filter is formed on the bottom substrate.
  • the upper and bottom substrates are sealed at their marginal portion and have a predetermined cell gap, defining a predetermined clearance into which a liquid crystal is sealed.
  • the liquid crystal is sealed between the upper and bottom substrates .
  • the LCD cannot display pictures for itself, it is used in the form of a module including an optical source such as a light -emitting device, for example, a electroluminescence device, a light emitting diode panel, or a cold cathode fluorescence lamp.
  • the LCD forms pictures with ground colors which appear when the liquid crystal is driven.
  • a TFT for switching the pixel electrode is formed on one side of the pixel electrode formed on the bottom substrate.
  • a bottom-gate TFT is formed in such a manner that its gate is formed under its channel of silicon layer.
  • a top-gate TFT is formed in such a manner that its gate is formed on its channel.
  • Fig. 1 is a layout of a conventional TFT-LCD employing a bottom-gate TFT. Referring to Fig. l,the bottom of the TFT is comprised of a gate line 12, gate electrode 13 and semiconductor layer pattern 14.
  • the gate line 12 which is extended in a longitude direction thereof on the bottom of TFT is located on top of a transparent insulating substrate 10 .
  • the gate electrode 13 is projected from one side of gate line 12.
  • the semiconductor layer pattern 14 to be a channel in the form of a rectangle is superposed on the center of gate electrode 13.
  • a data line 16 is formed perpendicular to gate line 12.
  • a drain electrode 17 is projected from one side of data line 16 and is connected to semiconductor layer pattern 14.
  • a gate insulating layer (not shown) is formed on gate line 12 and gate electrode 13, and insulates them from semiconductor layer pattern 14 and data line 16.
  • a pixel electrode 18 having a transparent electrode pattern is formed at the other portion of substrate 10 in the TFT.
  • a source electrode 19 connects pixel electrode 18 to semiconductor layer pattern 14.
  • the aforementioned conventional TFT-LCD is fabricated through the following procedure. That is, patterning a pixel electrode on an insulating substrate, patterning a gate line and gate electrode, depositing a gate insulating layer, patterning a semiconductor layer, depositing an insulating layer on the overall surface of the substrate structure, forming source and drain contact holes, and patterning a data line and, a source and drain electrode.
  • These processes require many fabrication steps using masks. Accordingly, as the fabrication process becomes complicated, the production yield is decreased but the fabrication cost is increased.
  • the TFT is separately formed having a predetermined distance from the gate line and data line. Also, the TFT portion is covered by a block matrix. Accordingly, the aperture rate is decreased, thereby deteriorating the picture quality and luminance .
  • a TFT-LCD structure has been proposed. This structure, as shown in Fig. 2, is constructed in the following manner.
  • gate line 12 is used as a gate electrode, without employing a separate gate electrode, and semiconductor layer pattern 14 is formed on gate line 12.
  • semiconductor layer pattern 14 is connected to pixel electrode 18 through source electrode 19, a portion of data line 16 is projected and this projected portion is used as drain electrode 17 which is connected to the other side of semiconductor layer pattern 14.
  • the projected drain electrode decreases the aperture rate, and the source electrode 19 and the source and drain contacts are formed through separate processes, making the process complicated and reducing the production yield.
  • An object of the present invention is to provide a TFT- LCD in which a semiconductor layer pattern is formed on a gate line, a data line is superposed on the semiconductor layer pattern, and a TFT is placed on conducting lines, to thereby improve its aperture rate and reliability.
  • a TFT-LCD including a gate line extended in one direction on an insulating substrate; a semiconductor layer pattern superposed on the gate line, one end of the semiconductor layer pattern being projected from both sides of the gate line, the other end of the semiconductor layer pattern being projected in one direction from one side of the gate line; a data line formed so that the data line is intersected perpendicularly with the gate line and superposed on a portion projected from both sides of the gate line in the semiconductor layer pattern; and, a pixel electrode contacted with the other portion projected from the end of the semiconductor layer pattern.
  • a method of fabricating a TFT-LCD comprising the steps of : forming a gate line on an insulating layer; forming a gate insulating layer on the overall surface of the substrate; forming a semiconductor layer pattern superposed on the gate line, one end of the semiconductor layer pattern being projected from top to bottom on both sides of the gate line, the other end of the semiconductor layer pattern being projected in one direction from the top of one side of the gate line; forming a heavily doped impurity region in a portion of the semiconductor layer pattern where the semiconductor layer pattern is not superposed on the gate line; forming an insulating layer on the semiconductor layer pattern; removing a portion of the insulating layer placed on the heavily doped impurity region, to form source and drain contact holes; and forming a data line coming into contact with the heavily doped impurity region, the data line being intersected with the gate line.
  • Fig. 1 is a layout of a conventional TFT-LCD
  • Fig. 2 is a layout of another conventional TFT-LCD
  • Fig. 3 is a layout of a TFT-LCD according to a first embodiment of the present invention
  • Fig. 4 is a cross-sectional view taken along line I-I of Fig. 3;
  • Figs. 5A to 5D are cross-sectional views showing a process of fabricating the TFT-LCD according to the first embodiment of the present invention
  • Figs. 6A, 6B and 6C are plane views showing a process of fabricating a TFT-LCD according to a second embodiment of the present invention.
  • Figs . 7A and 7B are plane views showing a process of fabricating a TFT-LCD according to a third embodiment of the present invention.
  • Fig. 3 is a layout of one pixel of a TFT-LCD according to a first embodiment of the present invention.
  • TFT- LCD includes a gate line 12 extended in one direction on a transparent insulating substrate 10, a semiconductor layer pattern 14 to be a channel superposed on a portion of gate line 12, a pixel electrode 18 formed on a center portion of transparent insulating substrate 10 which is defined by gate line 12 and data line 16
  • a transparent insulating substrate 10 is made of glass, quartz or plastic material, and a gate line 12 is formed with conductive material like Al, W, Ti or Cr.
  • a semiconductor layer pattern 14 is formed of polysilicon, amorphous silicon or micro-crystal silicon. Also, a semiconductor layer pattern 14 is formed of in a predetermined form such as a J-shape. One side of the J- shape semiconductor layer pat tern 14 superposed on the data line 16 covers the gate line 12 as this shape is extended in two direction, and the other side of the semiconductor pattern is projected in one direction.
  • a heavily doped impurity region 24 to be the source and drain regions is formed in the projected portion of semiconductor layer pattern 14.
  • a predetermined end portion which is projected from both sides of the semiconductor layer pattern 14 comes into contact with the portion of the data line 16 from top to bottom, while the other portion projected from one side of the semiconductor layer pattern 14 is connected to a pixel electrode.
  • a pixel electrode 18 is formed on a portion of transparent insulating substrate 10, defined by gate line 12 and data line 16.
  • the TFT hardly occupies the pixel region so that the aperture rate is increased.
  • the semiconductor layer pattern is formed on the gate line, and thus good topology can be obtained, resulting in accurate patterning during the formation of layers through photolithography.
  • Figs. 5A to 5D are cross-sectional views showing a process of fabricating the TFT-LCD according to the first embodiment of the present invention.
  • gate line 12 is formed on transparent insulating substrate 10
  • a gate insulating layer 22 is formed of a silicon oxide or silicon nitride on the overall surface of the substrate .
  • Semiconductor layer pattern 14 is formed on gate insulating layer 22 in a J-shape as shown in Fig. 3.
  • an impurity like As, P or B is heavily ion- implanted into a portion of the semiconductor layer pattern, where semiconductor layer pattern 14 is not superposed on gate line 12, to thereby form heavily doped impurity region 24 for ohmic contact.
  • an insulating layer 28 is formed of a silicon oxide or silicon nitride on semiconductor layer pattern 14.
  • insulating layer 28 is formed only on semiconductor layer pattern 14. However, it can also be formed on the overall surface of the substrate.
  • a predetermined portion of insulating layer 28 is selectively removed to form a contact hole 26, thereby exposing heavily doped impurity region 24.
  • contacts for connecting semiconductor layer pattern 14 and data line 16 may be formed on both projected portions of the semiconductor layer pattern for the purpose of reducing the contact resistance.
  • Data line 16 is formed to come into contact with semiconductor layer pattern 14 and to intersect gate line 12.
  • Pixel electrode 18 is formed of a transparent material such as ITO, Sn0 2 or In 2 0 3 -ZnO on a predetermined portion of the substrate, which is defined by gate line 12 and data line 16.
  • pixel electrode 18 comes into contact with heavily doped impurity region 24 through contact hole 26.
  • Pixel electrode 18 may be formed before the formation of the gate line. In this case, a source electrode to which the pixel electrode is connected must be formed separately.
  • Figs. 6A to 6C are plane views showing a method of fabricating a TFT-LCD having an offset region in its source and drain regions according to a second embodiment of the present invention.
  • gate line 12 is formed on transparent insulating substrate 10, extending in one direction.
  • a gate insulating layer (not shown) is formed of a silicon oxide or silicon nitride on the overall surface of the substrate.
  • semiconductor layer pattern 14 is formed in J-shape on the gate line 12 in such a manner that a bidirectional protrude portion 14A and a monodirectional protrude portion 14B are extended from gate line 12.
  • a photoresist pattern 30 is formed on the portion where a data line is not superposed on the semiconductor layer pattern.
  • photoresist pattern 30 covers a portion of projected portion 14B of the semiconductor layer pattern 14.
  • an n-type or p-type impurity such as As, P or B is heavily ion-implanted into a portion of semiconductor layer pattern 14 where photoresist pattern 30 is not formed, to thereby form heavily doped impurity region 24 for ohmic contact.
  • an offset region 32 having a predetermined distance from gate line 12 is formed in heavily doped impurity region 24.
  • the photoresist pattern is removed, an insulating layer (not shown) having source and drain contact holes, a data line and a pixel electrode (not shown) are formed on semiconductor layer pattern 14, to thereby accomplish the TFT-LCD according to the second embodiment of the present invention.
  • offset region 32 reduces the leakage current .
  • Figs. 7A and 7B are plane views showing a method of fabricating a TFT-LCD having an LDD structure in its source and drain regions according to a third embodiment of the present invention.
  • the formation of gate line 12, gate insulating layer (not shown), semiconductor layer pattern 14 and heavily doped impurity region 24 including offset region 32 are formed on insulating substrate 10 through processes of Figs. 6A, 6B and 6C.
  • a photoresist pattern 34 is formed on gate line 12 in self-alignment through a backside exposure using gate line 12, to thereby expose offset region 32.
  • an impurity having the same conductivity as that of heavily doped impurity region 24 is lightly ion- implanted into the exposed portion of semiconductor layer pattern 14, to form a lightly doped impurity region 36, thereby forming an LDD structure. Thereafter, photoresist pattern 34 is removed, and the data line and pixel electrode (not shown) are formed, accomplishing the TFT having the LDD structure.
  • the benefit of the TFT-LCD is that the semiconductor layer pattern is projected from one side of the gate line at a portion where the semiconductor layer pattern is superposed on the gate line, and projected from both sides of the data line at a portion where the data line is superposed on the semiconductor layer pattern.
  • One end of the semiconductor layer pattern comes into contact with the data line, and the other end is connected to the pixel electrode.
  • the offset region or LDD region may be formed in the semiconductor layer pattern.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un affichage à cristaux liquides et à transistor à couche mince (TFT-LCD) comprenant une ligne de porte s'étendant dans une direction sur un substrat isolant; une mire de couche de semi-conducteur superposée sur la ligne de porte, une extrémité de la mire de la couche de semi-conducteur étant projetée à partir des deux côtés de la ligne de porte, l'autre extrémité de la mire de la couche de semi-conducteur étant projetée dans une direction donnée à partir d'un côté de la ligne de porte; une ligne de données coupée par la ligne de porte et superposée sur une partie de la mire de la couche de semi-conducteur au niveau de la partie où la mire de la couche de semi-conducteur est projetée à partir des deux côtés de la ligne de porte, la ligne de données venant en contact avec la mire de la couche de semi-conducteur au niveau de la partie superposée; et une électrode de pixels connectée à l'autre extrémité de la mire de la couche de semi-conducteur, afin d'améliorer ainsi la vitesse d'ouverture, la qualité d'image et la luminance.
PCT/KR1996/000279 1996-11-30 1996-12-31 Affichage a cristaux liquides et a transistor a couche mince et son procede de fabrication Ceased WO1998023997A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019960060357A KR19980041088A (ko) 1996-11-30 1996-11-30 박막트랜지스터 액정표시장치 및 그 제조방법
KR1996/60357 1996-11-30

Publications (1)

Publication Number Publication Date
WO1998023997A1 true WO1998023997A1 (fr) 1998-06-04

Family

ID=19485009

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR1996/000279 Ceased WO1998023997A1 (fr) 1996-11-30 1996-12-31 Affichage a cristaux liquides et a transistor a couche mince et son procede de fabrication

Country Status (3)

Country Link
KR (1) KR19980041088A (fr)
TW (1) TW348323B (fr)
WO (1) WO1998023997A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1296765C (zh) * 2003-03-18 2007-01-24 友达光电股份有限公司 一种薄膜晶体管液晶显示器面板的制作方法
CN102368499A (zh) * 2011-10-27 2012-03-07 深圳市华星光电技术有限公司 Tft阵列基板及液晶面板
WO2012177776A3 (fr) * 2011-06-23 2013-11-21 Apple Inc. Pixel d'affichage ayant un transistor à couches minces (tft) d'oxyde à charge réduite

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100542303B1 (ko) * 1998-08-24 2006-04-06 비오이 하이디스 테크놀로지 주식회사 액정 표시 장치
JP3512675B2 (ja) * 1999-04-27 2004-03-31 Ｎｅｃ液晶テクノロジー株式会社 薄膜トランジスタアレイ

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5436182A (en) * 1992-05-19 1995-07-25 Casio Comupter Co., Ltd. Method of manufacturing thin film transistor panel
US5466620A (en) * 1993-12-14 1995-11-14 Goldstar Co., Ltd. Method for fabricating a liquid crystal display device
JPH08240817A (ja) * 1995-12-21 1996-09-17 Semiconductor Energy Lab Co Ltd アクティブマトリクス表示装置の作製方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5436182A (en) * 1992-05-19 1995-07-25 Casio Comupter Co., Ltd. Method of manufacturing thin film transistor panel
US5466620A (en) * 1993-12-14 1995-11-14 Goldstar Co., Ltd. Method for fabricating a liquid crystal display device
JPH08240817A (ja) * 1995-12-21 1996-09-17 Semiconductor Energy Lab Co Ltd アクティブマトリクス表示装置の作製方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1296765C (zh) * 2003-03-18 2007-01-24 友达光电股份有限公司 一种薄膜晶体管液晶显示器面板的制作方法
WO2012177776A3 (fr) * 2011-06-23 2013-11-21 Apple Inc. Pixel d'affichage ayant un transistor à couches minces (tft) d'oxyde à charge réduite
US8988624B2 (en) 2011-06-23 2015-03-24 Apple Inc. Display pixel having oxide thin-film transistor (TFT) with reduced loading
CN102368499A (zh) * 2011-10-27 2012-03-07 深圳市华星光电技术有限公司 Tft阵列基板及液晶面板
CN102368499B (zh) * 2011-10-27 2014-04-16 深圳市华星光电技术有限公司 Tft阵列基板及液晶面板

Also Published As

Publication number Publication date
KR19980041088A (ko) 1998-08-17
TW348323B (en) 1998-12-21

Similar Documents

Publication Publication Date Title
US5940151A (en) Liquid crystal display and method for fabricating the same
US6137551A (en) Liquid crystal display, thin film transistor array, and method of fabricating same with storage capacitor providing high aspect ratio
US8183070B2 (en) Array substrate for liquid crystal display device and method of fabricating the same
US6717638B1 (en) Liquid crystal display device and method of manufacturing the same
US7888151B2 (en) Array substrate for liquid crystal display device and method of fabricating the same
KR100268007B1 (ko) 액정표시소자 제조방법
US6500702B2 (en) Method for manufacturing thin film transistor liquid crystal display
US7855033B2 (en) Photo mask and method of fabricating array substrate for liquid crystal display device using the same
KR101146522B1 (ko) 액정표시장치용 어레이기판 제조방법
US7436461B2 (en) Liquid crystal display device
US7202924B1 (en) Liquid crystal display and a fabricating method thereof
US20040252250A1 (en) Liquid crystal display device and method of manufacturing the same
US8279389B2 (en) Liquid crystal display device having storage lines overlapping active layers formed of polysilicon material
US7071045B2 (en) Process of manufacturing thin film transistor
WO1998023997A1 (fr) Affichage a cristaux liquides et a transistor a couche mince et son procede de fabrication
JP2000122096A (ja) 反射型液晶表示装置およびその製造方法
KR101136296B1 (ko) 폴리 실리콘형 박막 트랜지스터와 그를 가지는 폴리실리콘형 박막트랜지스터 기판 및 그 제조 방법
JP3647384B2 (ja) 薄膜半導体素子およびその製造方法並びに表示パネル
KR100412121B1 (ko) 박막 트랜지스터의 제조방법
US20030096463A1 (en) Thin-film semiconductor element and method of producing same
KR100267995B1 (ko) 액정표시장치 및 그 제조방법
KR0174032B1 (ko) 액정표시장치용 박막 트랜지스터 및 그 제조방법
KR100267980B1 (ko) 액정표시장치및그제조방법
KR0146249B1 (ko) 액정표시장치용 박막 트랜지스터 및 그 제조방법
KR0174031B1 (ko) 액정표시장치용 박막 트랜지스터 및 그 제조방법

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CA CN JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: JP

Ref document number: 1998524545

Format of ref document f/p: F

122 Ep: pct application non-entry in european phase