WO1998015842A1

WO1998015842A1 - Quantisation error reduction

Info

Publication number: WO1998015842A1
Application number: PCT/GB1997/002750
Authority: WO
Inventors: Tadeusz Stanislaw Dzwig
Original assignee: Conlog Pty Ltd
Current assignee: Conlog Pty Ltd
Priority date: 1996-10-08
Filing date: 1997-10-08
Publication date: 1998-04-16
Anticipated expiration: 1999-04-08
Also published as: AU4567497A

Abstract

An apparatus for reducing errors in the digital measurement of a desired characteristic of a periodic analogue signal inlcudes: a sampling facility for sampling the analogue signal over one or more periods of a signal to obtain a set of under-read samples during a first half period, each under-read sample having a corresponding under-read error, and a set of over-read samples during a second half period each over-read sample having a corresponding over-read error; and a processor for selecting the number of samples in the sample sets for each half period to be sufficient to allow the over-read errors to offset the under-read errors, to a desired extent, in a calculation of the desired characteristic of the analogue signal.

Description

QUANTISATION ERROR REDUCTION

FIELD OF THE INVENTION

This invention relates to a method of,^" and an apparatus for, error reduction in digital measurement of analogue signals.

BACKGROUND TO THE INVENTION

The accuracy with which analogue signals are converted to digital information is limited by the resolution of the type of analogue to digital convener (ADC) which is used to sample the analogue signal used. Typically such ADCs are 8, 10 or 12 bit ADCs, but various other resolutions are available.

An 8 bit ADC has 256 possible outputs. Thus, when an alternating current (AC) input signal is measured, the conversion error can be as high as 1/128 of the full scale voltage. In cases where higher accuracy is desired, higher order ADC's can be used to assist in achieving this, but this impiies additional costs.

In cost-sensitive electronic products, it is desirable to minimise the cost of electronic components. The trend is to use low cost micro-processors, which often have an integrated ADC, of which the input can be multiplexed. However, the resolution of these low cost micro-processors is normally 8 bit.

Several methods of achieving improved accuracy with ADC's have been proposed, but all of them require additional external circuitry to enhance the resolution, which increases the costs of the ADC.

OBJECT OF THE INVENTION

It is an object of this invention to provide a method of, and an apparatus for, error reduction in digital measurement of analogue signals. SUMMARY OF THE INVENTION

In accordance with this invention there is provided a method of error reduction in the digital measurement of a desired characteristic of a substantially periodic analogue signal, comprising the steps of : sampling the analogue signal over at least one period of the signal to obtain a plurality of under-read samples during a first half period each under-read sample having a corresponding under-read error, and a plurality of over-read samples during a second half period, each over-read sample having a corresponding over-read error; and selecting the number of samples for each half period, to be sufficient to allow the over-read errors to substantially offset the under-read errors, to a predetermined desired extent, in a calculation of the desired characteristic of the analogue signal.

Further features of the invention provide for the analogue signal to be symmetric, for sampling the analogue signal over a plurality of periods of the signal, for the plurality of periods to be a prime number of periods, for the selected number of over-read samples and the selected number of under-read samples to total at least eleven samples.

Still further features of the invention provide for sampling the analogue signal at a sampling rate sufficient to enable the selected number of over-read samples and the selected number of under-read samples to total at least eleven samples, even under variations in frequency of the analogue signal.

The invention extends to an apparatus for reducing errors in the digital measurement of a desired characteristic of a substantially periodic analogue signal, comprising : sampling means for sampling the analogue signal over at least one period of the signal to obtain a plurality of under-read samples during a first half period, each under-read sample having a corresponding under-read error, and a plurality of over-read samples during a second half period, each over-read sample having a corresponding over-read error; and processing means for selecting the number of samples for each half period, to be sufficient to allow the over-read errors to substantially offset the under-read errors, to a predetermined desired extent, in a calculation of the desired characteristic of the analogue signal.

Further features of the invention provide for the analogue signal to be symmetric, and for a display means to be connectable to the processing means for displaying the calculated desired characteristic.

BRIEF DESCRIPTION OF THE DRAWING

Embodiments of the invention are described below by way of example only, and with reference to the accompanying drawings, in which:

Figure 1 is a diagrammatic view of apparatus according to the invention;

Figure 2 is a graph of the output of digital samples against the original sinusoidal signal;

Figure 3 is a graph of errors in the first and second half of a cycle against the magnitude of the input signal;

Figure 4 is a graph of the average digital samples and the original sinusoidal signal; and

Figure 5 is a graphic illustration of samples overlapping.

DETAILED DESCRIPTION WITH REFERENCE TO THE DRAWINGS

Referring to Figure 1 , apparatus (1) for reducing errors in the digital measurement of an analogue signal comprises a processor (2) in an analogue to digital (A/D) converter having input connectors (3) and a display means (4). The processor (2) samples an analogue signal through the input connector (3). The samples are then processed according to the method described below to measure a desired characteristic of the analogue signal, whereafter the measured result is displayed, if required, by the display means (4). The method of this invention can be illustrated assuming a large number of samples in one repetition cycle of the measured analogue signal. If a large number of samples is collected in one cycle of a periodic waveform, the time step becomes very fine and the digital representation of the waveform appears almost continuous, as illustrated in Figure 2. Referring to Figure 2, a sinusoidal mains supply waveform is shown at the input connectors (3), with the signal level deliberately kept low for better clarity. The markings (10) show the sampling resolution of the A/D conversion in operation. Since the input is a periodic waveform, there will be a large number of samples where the A/D "uπder-reads", with a similar number of samples where A/D "over-reads". Figure 2 shows that during the first half of the cycle the A/D "under-reads" and during the second half it "over-reads".

Consequently, one can assume that the sampling error will be negative in the first half of the cycle (i.e. "under-read errors") and positive in the second half (i.e. "over-read errors").

Referring to Figure 3, the signal amplitude is plotted against the percentage reading error. The "X" symbol is used to distinguish the progression (11) in the first half period from the error progression (12) for the second half period, shown by the symbol "O". The total error is shown by numeral 13. The graph illustrates the error for the example of calculation of average value of a sinusoidal signal. The total error (13) is significantly lower than either of the two half cycle error graphs. Consequently, the total error calculated for a complete cycle of the input waveform can be very small, despite the fact that individual samples have limited accuracy. The averaging of readings will never be perfect, but the resultant error will be low, provided the number of samples is sufficiently large. It is through the fact that the alternate half of the cycle exhibits an error of opposite sign that the method achieves the desired accuracy.

Figure 4 is similar to Figure 2 but the digitised signal is averaged. The original sinusoidal signal (20) is shown against the digitised and averaged signal (21). The "under-reading" and "over- reading" in the two halves of the cycle is clearly illustrated. It is also clear that as the signal becomes larger, the average will follow the original signal more closely. There is an "apparent" offset introduced by the A/D conversion owing to truncation of the results to the nearest integer. The resulting error varies from 0 to 1 , with an average of 0.5. Adding a 0.5 least significant bit (LSB) to the input results in eliminating the difference between the lines in Figure 3. The average from Figure 4 follows the actual waveform very closely, with this correction, but the overall error does not change.

When measuring a desired characteristic, for example the root mean square, the signal is sampled, and each of the samples are squared, followed by subsequent integration over a cycie or a number of cycles. By sampling the analogue signal such that under-read errors substantially cancel the over-read errors, an acceptable result can be obtained. Thus, without using a higher order anaiogue-to-digital converter, the accuracy of the analogue-to-digital converter is in effect enhanced by way of sampling the signal such that the errors substantially cancel out. In practice, it has been found that, when sampling the analogue signal at at least eleven samples per cycle, an acceptable and better result is obtained.

Collecting samples over a period of several cycles is desirable since the time between two subsequent sampling points can be made longer, making software implementation considerably easier. However, signal frequency must remain stable during that process which is often the case. When the frequency is stable but differs from the nominal, this type of sampling method may suffer from beat phenomena. When duration of an integer number of cycles k, especially a low number such as 1 , 2, 3 or 5, is equal to an integer number of sampling periods, the samples over every subsequent k cycles will simply be a repetition of the samples collected over the first k cycles and no further averaging will take place. The resulting overlapping of samples will degrade the method to the one where a reduced number of samples is collected over k cycles. Sample overlapping can always happen whenever the sampling time does not track signal frequency, but the resulting loss of accuracy can be controlled as long as the frequency deviation is within given limits. Sample overlapping is illustrated in Figure 5.

The sampling period can be selected in such a way as to ensure that even in the worst case of sample overlapping, the number of different samples collected is sufficient to maintain the required accuracy. The error can be further reduced, without detracting from the principle of this invention, by implementation of dither (random variation) on the resulting time.

All the principles leading to the reduction of error in this method can be implemented in software. The improvement of the total error with respect to the original resolution of the ADC is typically observed for the number of distinct sample points equal to eleven or more.

Very often the number of distinct samples under nominal conditions will be much larger but the design will ensure that in the worst case of sample overlapping (e.g. a transient condition), the effective number of different samples per cycle will not be less than eleven.

Claims

CLAI S

1. A method of error reduction in the digital measurement of a desired characteristic of a substantially periodic analogue signal, comprising the steps of : sampling the analogue signal over at least one^' period of the signal to obtain a plurality of under-read samples during a first half period each under-read sample having a corresponding under-read error, and a plurality of over-read samples during a second half period, each over-read sample having a corresponding over-read error; and selecting the number of samples for each half period, to be sufficient to allow the over-read errors to substantially offset the under-read errors, to a predetermined desired extent, in a calculation of the desired characteristic of the analogue signal.

2. A method as claimed in claim 1 in which the analogue signal is symmetric.

3. A method as claimed in either one of claims 1 or 2 in which the analogue signal is sampled over a plurality of periods of the signal.

4. A method as claimed in claim 3 in which the plurality of periods is a prime number of periods.

5. A method as claimed in either one of claims 1 or 2 in which the selected number of over-read samples and the selected number of under-read samples total at least eleven samples.

6. A method as claimed in any one of claims 1 , 2 or 5 in which the analogue signal is sampled at a sampling rate sufficient to enable the selected number of over-read samples and the selected number of under-read samples total at least eleven samples, even under variations in frequency of the analogue signal.

7. An apparatus for reducing errors in the digital measurement of a desired characteristic of a substantially periodic analogue signal, comprising : sampling means for sampling the analogue signal over at least one period of the signal to obtain a plurality of under-read samples during a first half period, each under-read sample having a corresponding under-read error, and a plurality of over-read samples during a second half period, each over-read sample having a corresponding over-read error; and processing means for selecting the number of samples for each half period, to be sufficient to allow the over-read errors to substantially offset the under-read errors, to a predetermined desired extent, in a calculation of the desired characteristic of the analogue signal.

8. An apparatus as claimed in claim 7 in which the analogue signal is symmetric.

9. An apparatus as claimed in either one of claims 7 or 8 in which a display means is connectable to the processing means for displaying the average of the selected samples.