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WO1998015060A1 - Tampon cmos de commutation de niveau de haute tension - Google Patents

Tampon cmos de commutation de niveau de haute tension Download PDF

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Publication number
WO1998015060A1
WO1998015060A1 PCT/US1997/016922 US9716922W WO9815060A1 WO 1998015060 A1 WO1998015060 A1 WO 1998015060A1 US 9716922 W US9716922 W US 9716922W WO 9815060 A1 WO9815060 A1 WO 9815060A1
Authority
WO
WIPO (PCT)
Prior art keywords
buffer
voltage
level
parallel circuit
operating voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1997/016922
Other languages
English (en)
Inventor
Richard L. Hull
Randy L. Yach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Microchip Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Priority to EP97943473A priority Critical patent/EP0864203A4/fr
Priority to JP10516616A priority patent/JPH11500896A/ja
Priority to KR1019980704021A priority patent/KR19990071743A/ko
Publication of WO1998015060A1 publication Critical patent/WO1998015060A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit

Definitions

  • the present invention relates generally to buffer circuits which are useful across a wide voltage range, and more particularly to a high voltage level shifting CMOS buffer which has the capability to perform as a level shifter with shared breakdown in a high voltage mode and as a non-contending CMOS (complementary metal-oxide-silicon) logic gate in a low voltage mode.
  • CMOS complementary metal-oxide-silicon
  • EPROM devices are fabricated using semiconductor process technology. As line widths are reduced in progression of the process technology it may be desirable not only to design and fabricate entirely new versions of products but to "shrink" or scale existing products to a smaller size with the new technology. This requires review and analysis of the design and architecture of the product and the manner in which the attempted scaling of its size may adversely affect its operation. The task presented is to shrink an EPROM product according to a new process technology, in a cost-effective and operation-feasible manner.
  • the scaling process imposes restrictions which, when coupled with the device requirements, makes the task extremely difficult.
  • Some of the issues encountered in implementing a scaling process for such a device are wide voltage range, low program read margins, high speed, and low current.
  • the read margins of the scaled EPROM are typically lower than the operating voltage range of the device.
  • the supply voltage of the microcontroller is used to control the EPROM memory element so as to enable reading of the data stored in the element.
  • a measurement of the programmed threshold voltage of the memory element is required.
  • the memory element is said to be erased if the threshold voltage of the EPROM cell is low, and to be programmed if the threshold voltage is high.
  • the cell is read by applying a voltage to the control gate of a transistor comprising the cell. If the applied voltage is higher than the threshold, current flows through the cell.
  • the programming margin of the cell is the voltage difference between the maximum applied control gate voltage and the programmed threshold voltage of the programmed cell.
  • a programmed EPROM cell will not conduct current when read by application of a control gate voltage of lower magnitude than the high threshold voltage of the cell.
  • the control gate voltage used to read the memory array is the supply voltage of the system. If the programmed threshold of the memory cell is lower than the maximum value of that supply voltage, a programmed cell cannot be detected using the classic techniques. Scaling the device to smaller size also has the effect of reducing the voltage range which is used to operate the EPROM. When an EPROM memory cell is shrunk, the programmed threshold voltage is decreased and the effective programming margin is lowered. Also, a smaller EPROM cell typically dictates a lower read current. All of this makes it difficult to read the data in a scaled EPROM cell by means of standard techniques.
  • the read margin voltage below the supply voltage requires that the row voltage (i.e., the voltage that controls the gate of the EPROM memory element) be regulated to a lower value. If the control gate voltage is not reduced to a level below the magnitude of the programmed threshold voltage, the contents of the EPROM memory cell cannot be read. Regulating the read voltage usually requires the consumption of significant amounts of current, especially if the electrical node being driven requires high speed operation or is heavily loaded with capacitance.
  • a typical solution to regulate the row voltage would be to clamp the row voltage by bleeding off current proportional to the supply voltage to limit the final voltage that is applied to the EPROM element.
  • the row drive circuitry is also required to be high speed and has a significant amount of capacitive loading. This makes the job of regulating the final voltage very difficult when given the constraints of low current consumption and high speed operation.
  • the EPROM architecture has used a high voltage supply applied directly to the sense amplifier and the X-decoder of the EPROM array. Either the X-decoder, which translates into a row in the array, or the sense amplifier, which translates into a column in the array, is driven, which brings both devices to high voltage.
  • a transistor is present at the intersection of a row with a column, and current flows through the memory cell that comprises the transistor, to program it.
  • the EPROM program memory device associated with a microcontroller undergoes a shrink to smaller size, the maximum voltage that may be applied to the device is less than the value that was used with the previous larger-sized device. Nevertheless, the device requires a magnitude of voltage for programming which is determined by a requirement that does not undergo a comparable size reduction.
  • the programming threshold of the memory cell may be exceeded, and equally or more important, the relatively high voltage levels present for programming the EPROM cell may damage the transistor in the cell. It has been industry-wide common practice to place two transistors in series circuit to share a breakdown voltage, because it is unlikely that both will suffer breakdown simultaneously. Rather, since the voltage is split between them, the two transistors are subjected to lower voltage levels than they would otherwise experience.
  • the present invention provides a high voltage level shifting CMOS buffer circuit that operates differently, and effectively, in high voltage and low voltage modes.
  • the buffer circuit of the invention assists in solving the problem of implementing a high speed, low power EPROM array in a scaled process technology.
  • transistor damage is prevented by use of the buffer, which in its high voltage mode, provides conventional shared voltage operation with gated breakdown protection, in which two transistors are connected with their source-drain paths in series to share the high voltage applied to the circuit.
  • the buffer acts as a CMOS logic gate with no contention, i.e., with no digital contention between NMOS and PMOS transistors, to provide very high speed and low voltage operation. This assures that the device provides high speed operation over the wide voltage range of interest.
  • FIG. 1 is a circuit diagram of an EPROM array circuit embedded in a microcontroller device, as an exemplary application utilizing a high voltage level shifting CMOS buffer according to the present invention
  • FIG. 2 is a simplified circuit diagram of a presently preferred embodiment of the high voltage level shifting CMOS buffer of the invention.
  • EPROM array 12 is embedded as a program memory in a microcontroller 10.
  • the memory array has conventional rows and columns, at each intersection of which the state of a transistor (i.e., presence or absence of a device) represents the value ("0" or "1") of the bit stored at that array location.
  • the EPROM has as its operating voltage supply, the voltage V DD of the microcontroller.
  • An X-decoder 13 is the row driver circuit for EPROM array 12, generating the control gate voltage and the control programming voltage for the array.
  • High voltage buffer 15 is coupled for translation of the supply voltage V DD to a voltage sufficiently high to program the EPROM memory element.
  • the buffer is also used with a sense amplifier 17 for the array.
  • a voltage reference 18 employed in the array 12 limits the read voltage of the control gate and the drain of the EPROM memory element.
  • a row precharge circuit in the EPROM improves the time for accessing array locations to read data, and reduces DC power dissipation.
  • the row precharge 20 is performed in the regulator circuit and is passed to X-decoder 13 to drive the control gate.
  • Sense amplifier 17 senses the current in the memory element, and determines the threshold of the EPROM element.
  • a switched ground circuit 21 further speeds up the access time of the EPROM array. Current will flow in the memory element only if the control gate of the element is high, the drain of the element is connected to the sense amplifier, and the source of the element is connected to ground. During setup of the row voltage, the source is removed from ground until the voltage has reached a predetermined proper value, and, at that point, the source is grounded and current flows to read the memory element.
  • the high voltage buffer of the present invention used in the exemplary EPROM circuit application of FIG. 1 is illustrated in the simplified circuit diagram of FIG. 2. By means of this buffer circuit, high programming voltages are more effectively dealt with. In the high voltage mode, the buffer uses two transistors to share the burden of the high programmed voltage, similarly to what has been shown in the prior art.
  • the buffer circuit in the low voltage mode, constitutes a CMOS logic gate.
  • the shared voltage operation of the dual transistor high voltage mode provides high voltage breakdown protection, and in the low voltage mode the invention provides high speed CMOS gate operation over a wide CMOS voltage range.
  • the overall buffer circuit includes PMOS (p-channel
  • the buffer circuit comprises two parallel circuit paths between the voltage source terminal 40 (Z) labeled "high voltage/ V DD " and the analog ground terminal (reference potential).
  • Each transistor has source, drain, and gate electrodes or nodes, as well as a substrate connection.
  • the source-drain current paths of the transistors 30, 31, and 35 are connected in series circuit in one of the two parallel paths, and the source-drain paths of transistor 32, 33, and 36 are connected in series in the other of the two parallel paths.
  • the substrate connections for PMOS transistors 30, 31, 32, and 33 are tied to voltage source terminal 40, and the substrate connections (not shown) for NMOS transistors 35 and 36 are tied to ground.
  • each of transistors 30 and 31 is connected to the other parallel path (i.e., to the series circuit containing the source-drain path of the other of those two transistors), and the gate nodes of the other two transistors in each series path are connected together (i.e., the gates of transistors 31 and 35, and separately, the gates of transistors 33 and 36).
  • the inverter 38 is connected between the gates of NMOS transistors 35 and 36 (and thus, also between the gates of PMOS transistors 31 and 33).
  • An input (X) to the buffer circuit is applied at terminal 43 which is connected to the gates of transistors 31 and 35, and outputs (X 0 , nXJ of the buffer are taken at terminals 45 and 47 which are connected to separate ones of the parallel paths.
  • the voltage applied at terminal 40 (Z) is greater than V DD .
  • the voltage applied to the inverter 38 is V DD .
  • transistors 30, 31, and 36 will be “on”, so that a "0" output is present at terminal 45 (X 0 ) and a high voltage output is present at terminal 47 (nXJ.
  • the high voltage is shut off through transistors 32 and 33, which share the breakdown voltage by applying V DD from the output of inverter 38 to the gate of transistor 33.
  • transistors 32, 33, and 35 will be “on”, so that a high voltage output appears at terminal 45 (X 0 ) and a "0" output is present at terminal 47 (nX 0 ). In that case, transistors 30 and 31 will hold the high voltage off and will share the breakdown voltage relatively equally between them.
  • V DD , transistors 31, 33, 35, and 36 act completely as a CMOS gate by virtue of the interconnection of the gate nodes of each pair of those opposite conductivity type transistors in each of the two parallel circuit paths, and the presence of the inverter 38 in the path interconnecting those gate connections.
  • the circuit of the invention works at the normal power supply levels as a non-contending CMOS gate; that is, as a true CMOS logic gate without digital contention between the PMOS and NMOS transistors.
  • the buffer circuit fulfills a dual role; namely, as a high voltage level shifter with gated breakdown protection at voltage levels above V DD , and as a true CMOS logic gate when used at normal power supply levels at or below V DD .

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Read Only Memory (AREA)
  • Logic Circuits (AREA)

Abstract

La présente invention concerne un tampon de commutation de niveau de tension à silicium et oxyde métallique complémentaire (CMOS) (30-47), aménagé et configuré de façon à fonctionner selon deux modes distincts (haute tension et basse tension) dépendants du niveau de tension d'alimentation (40) du tampon par rapport à la tension de fonctionnement (VDD) d'un appareil dans lequel le tampon est intégré. En mode haute tension, dans lequel le niveau de tension d'alimentation est supérieur au niveau de tension de fonctionnement, le tampon est contraint de fonctionner comme un commutateur de niveau haute tension. En mode basse tension, dans lequel le niveau de tension d'alimentation est égal ou inférieur au niveau de tension de fonctionnement, le tempon est contraint de se comporter comme une porte logique CMOS.
PCT/US1997/016922 1996-10-01 1997-09-25 Tampon cmos de commutation de niveau de haute tension Ceased WO1998015060A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP97943473A EP0864203A4 (fr) 1996-10-01 1997-09-25 Tampon cmos de commutation de niveau de haute tension
JP10516616A JPH11500896A (ja) 1996-10-01 1997-09-25 高電圧レベルシフトｃｍｏｓバッファ
KR1019980704021A KR19990071743A (ko) 1996-10-01 1997-09-25 고전압레벨시프팅cmos버퍼

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US72392596A 1996-10-01 1996-10-01
US08/723,925 1996-10-01

Publications (1)

Publication Number Publication Date
WO1998015060A1 true WO1998015060A1 (fr) 1998-04-09

Family

ID=24908277

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/016922 Ceased WO1998015060A1 (fr) 1996-10-01 1997-09-25 Tampon cmos de commutation de niveau de haute tension

Country Status (5)

Country Link
EP (1) EP0864203A4 (fr)
JP (1) JPH11500896A (fr)
KR (1) KR19990071743A (fr)
TW (1) TW357361B (fr)
WO (1) WO1998015060A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1102402A1 (fr) * 1999-11-18 2001-05-23 Oki Electric Industry Co., Ltd. Circuit d'ajustement de niveau et circuit de sortie l'utilisant
US8046599B2 (en) 2006-07-31 2011-10-25 Mitsumi Electric Co., Ltd. Semiconductor integrated circuit device including semiconductor integrated circuit board supplied with no high voltage

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100585168B1 (ko) * 2004-12-22 2006-06-02 삼성전자주식회사 다중경로 입력버퍼회로
EP2029001B1 (fr) * 2006-06-02 2014-11-12 Koninklijke Philips N.V. Dispositif sans fil de surveillance cognitif pour un equipement de sante
US10263621B2 (en) 2017-03-24 2019-04-16 Taiwan Semiconductor Manufacturing Company Limited Level shifter with improved voltage difference

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4845381A (en) * 1987-10-01 1989-07-04 Vlsi Technology, Inc. Voltage level shifting circuit
US4978870A (en) * 1989-07-19 1990-12-18 Industrial Technology Research Institute CMOS digital level shifter circuit
US5039882A (en) * 1988-10-15 1991-08-13 Sony Corporation Address decoder circuit for non-volatile memory
US5157280A (en) * 1991-02-13 1992-10-20 Texas Instruments Incorporated Switch for selectively coupling a power supply to a power bus

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5243236A (en) * 1991-12-31 1993-09-07 Intel Corporation High voltage CMOS switch with protection against diffusion to well reverse junction breakdown
US5175512A (en) * 1992-02-28 1992-12-29 Avasem Corporation High speed, power supply independent CMOS voltage controlled ring oscillator with level shifting circuit
JP3144166B2 (ja) * 1992-11-25 2001-03-12 ソニー株式会社 低振幅入力レベル変換回路
JPH0774616A (ja) * 1993-07-06 1995-03-17 Seiko Epson Corp 信号電圧レベル変換回路及び出力バッファ回路
US5510748A (en) * 1994-01-18 1996-04-23 Vivid Semiconductor, Inc. Integrated circuit having different power supplies for increased output voltage range while retaining small device geometries
JP3204848B2 (ja) * 1994-08-09 2001-09-04 株式会社東芝 レベル変換回路及びこのレベル変換回路を用いてレベル変換されたデータを出力する方法
US5455526A (en) * 1994-08-10 1995-10-03 Cirrus Logic, Inc. Digital voltage shifters and systems using the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4845381A (en) * 1987-10-01 1989-07-04 Vlsi Technology, Inc. Voltage level shifting circuit
US5039882A (en) * 1988-10-15 1991-08-13 Sony Corporation Address decoder circuit for non-volatile memory
US4978870A (en) * 1989-07-19 1990-12-18 Industrial Technology Research Institute CMOS digital level shifter circuit
US5157280A (en) * 1991-02-13 1992-10-20 Texas Instruments Incorporated Switch for selectively coupling a power supply to a power bus

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0864203A4 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1102402A1 (fr) * 1999-11-18 2001-05-23 Oki Electric Industry Co., Ltd. Circuit d'ajustement de niveau et circuit de sortie l'utilisant
US6459322B1 (en) 1999-11-18 2002-10-01 Oki Electric Industry Co. Inc. Level adjustment circuit and data output circuit thereof
US6593795B2 (en) 1999-11-18 2003-07-15 Oki Electric Industry Co., Ltd. Level adjustment circuit and data output circuit thereof
US8046599B2 (en) 2006-07-31 2011-10-25 Mitsumi Electric Co., Ltd. Semiconductor integrated circuit device including semiconductor integrated circuit board supplied with no high voltage

Also Published As

Publication number Publication date
KR19990071743A (ko) 1999-09-27
TW357361B (en) 1999-05-01
EP0864203A4 (fr) 2001-02-07
JPH11500896A (ja) 1999-01-19
EP0864203A1 (fr) 1998-09-16

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