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WO1998013968A1 - Dispositif, systeme et methode pour l'elimination adaptable du bruit propre et pour la recuperation decisionnelle du rythme - Google Patents

Dispositif, systeme et methode pour l'elimination adaptable du bruit propre et pour la recuperation decisionnelle du rythme Download PDF

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Publication number
WO1998013968A1
WO1998013968A1 PCT/US1997/016935 US9716935W WO9813968A1 WO 1998013968 A1 WO1998013968 A1 WO 1998013968A1 US 9716935 W US9716935 W US 9716935W WO 9813968 A1 WO9813968 A1 WO 9813968A1
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Prior art keywords
self
samples
noise
timing
sampling
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Jian Yang
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Motorola Solutions Inc
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Motorola Inc
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Priority to AU46492/97A priority Critical patent/AU4649297A/en
Publication of WO1998013968A1 publication Critical patent/WO1998013968A1/fr
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Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection

Definitions

  • This invention relates to adaptive self-noise cancellation for decision directed timing recovery and more particularly for such noise cancellation in timing recovery in modems used for data communications over the public switched telephone network (PSTN).
  • PSTN public switched telephone network
  • the PSTN consists of a digital backbone network and analog local loops that connect users to this backbone.
  • the analog signal sent by the local user is digitized at the local central office and converted into a 64 kbit/s bitstream which is carried across the digital backbone network and then converted back to analog at the remote central office for delivery to the remote user over the remote local loop.
  • Dial-up modems communicate over the PSTN by modulating the digital information into an analog signal for transmission.
  • the digital-to-analog conversion process described above introduces quantization noise which limits the data transmission speed to around 30 kbit/s.
  • ISDN is a circuit-switched public network which allows end-to-end digital communication using 64 kbit/s circuits.
  • the analog information generated at the ISDN site is converted into a 64 kbit/s bitstream in an ISDN terminal adapter, in the same manner the central office digitizes an analog signal that originates at a PSTN site.
  • a PSTN end-point can also be reached using other forms of digital access. For example, medium-to-large size corporations often use T1 lines to access the PSTN. Regardless of the digital access medium, the traditional method of converting the modem signal into a 64 kbit/s bitstream limits the achievable modem speed to around 30 kbit/s.
  • FIG. 1 is a schematic block diagram of data communications system used for transmission of data over the PSTN;
  • FIG. 1A is a schematic block diagram of the sampler of FIG. 1 ;
  • FIG. 1 B is a schematic diagram of another configuration of the sampler of FIG. 1 ;
  • FIG. 2 is a schematic block diagram of the timing recovery circuit of FIG. 1 configured according to this invention;
  • FIG. 3 is a schematic block diagram of the timing error estimator of FIG. 2;
  • FIG. 4 is a schematic block diagram of a conventional timing error generator of FIG, 3;
  • FIG. 5 is a plot of a PAM signal and its component impulses
  • FIG. 6 is a plot of one of the component impulses of FIG. 5 with properly taken sample points
  • FIG. 7 is a plot of the component impulse of FIG. 6 with the sample points taken too early;
  • FIG. 8 is a plot of the component impulse of FIG. 6 with the sample points taken too late;
  • FIG. 9 is a schematic block diagram of the timing error generator of FIG. 3 configured according to this invention.
  • FIG. 10 is schematic block diagram of the self-noise canceller of FIG. 3 according to this invention.
  • FIG. 11 is schematic block diagram of an alternative self-noise canceller according to this invention.
  • FIG. 12 is a schematic block diagram of the NCO of FIG. 2. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
  • the encoded data is first mapped into ⁇ - law (outside of North America, A-law ) octets for transmission at a rate of 8000 octets per second, and then in the remote user's central office these octets are converted into the desired amplitude levels in the D/A converter.
  • the resulting 8 kHz sequence of levels is then passed through a low pass filter (LPF) and sent over the analog loop to the remote user.
  • LPF low pass filter
  • the output of the D/A converter can be viewed as a sequence of impulses each having an amplitude corresponding to one of the D/A levels.
  • a receiving modem recovers the original information by first detecting which D/A levels were transmitted, and then inverse mapping these to obtain an estimate of the original digital information.
  • This technique theoretically enables the transmission of data at 64kbps, however, with actual system constraints, acheiving transmission rates of 48kbps to 56kpbs is more pragmatic. These transmission rates are a significant improvement over the once thought theoretical limit of about 35kbps.
  • the analog impulses are typically filtered and output every T seconds (1/8Khz) over the analog loop to the receiving modem.
  • Received by the modem is a pulse amplitude modulated (PAM) signal which consists of a plurality of impulses on the loop.
  • PAM pulse amplitude modulated
  • the PAM signal In order for the receiving modem to decode the data accurately after transmission over the channel, the PAM signal must be sampled at the proper points on the impulse every T/2 seconds so that each impulse can be interpreted. This is accomplished by feedback means known as timing recovery.
  • the impulses are not discrete, but rather, generally a number of impulses are overlapping. This impulse overlap is referred to as self-noise or intersymbol interference (ISI) which makes timing recovery more difficult.
  • ISI intersymbol interference
  • the sampled signal is then equalized to remove the ISI introduced to the signal by the channel, and decoded by, for example, a Viterbi decoder.
  • a properly sampled impulse is sampled at a controlled point, such as at its peak. From the sampled voltage the m-law level is determined and from the ⁇ -law level the digital information the level represents is ascertained by the decoder. To determine if the impulses are being properly sampled, e.g. at their peaks, they are also sampled at other sample points (timing sample points), e.g. on either side of the peaks, and these sample points are compared to determine if proper sampling is occurring. If the impulses are being sampled improperly, i.e. too early or too late, the impulses are not sampled at their controlled point (the peak) and are therefore improperly decoded.
  • the equalizer output and the decoder output or decisions are utilized by a timing error generator to generate a timing error signal.
  • the equalizer is designed to optimize decoding reliability typically by means of a long adaptive feedforward filter section. This is especially true for systems involving trellis coding.
  • a problem with these schemes is that since the equalizer output is fed back to the timing recovery circuit an adverse interaction between the equalizer and the timing recovery circuit is introduced. More specifically, perturbations in the equalizer feedforward taps alter the impulse shape and thus shift the sampling points causing the timing recovery circuit to compensate for these shifts by adjusting the sampling phase. Since the timing recovery loop is coupled with the adaptation of the equalizer, this causes unwanted timing clock jitter which adversely effects the performance of the timing loop and reduces the accuracy of data detection.
  • timing clock jitter introduced by the above timing recovery scheme is acceptable. With this amount of jitter, sampling accuracy within approximately one tenth of a period T is achievable.
  • timing recovery scheme which provides the necessary improved sampling accuracy is described below.
  • FIG. 1 data communications system 10 which includes digital transmitter 12, directly connected to the digital telephone network 14.
  • Digital transmitter 12 encodes, as described in the copending applications, digital data to be transmitted by grouping bits of information, correlating each group with a ⁇ -law octet representing the group and transmitting the octet over digital network 14.
  • the digital data from network 14 is received at the telephone company central office 16 where each octet is converted to a voltage level by a ⁇ -law to linear converter.
  • the voltage levels are filtered and transmitted as impulses every T seconds over analog loop 17.
  • the signal on line 17 consisting of a plurality of impulses, the PAM signal, is provided to modem 18.
  • the PAM signal is sampled by sampler 20 at a multiple of the impulse transmission frequency and the samples are provided over line 21 to an adaptive equalizer 22, which may be a fractionally spaced partial response linear equalizer.
  • Adaptive equalizer 22 removes the self-noise or intersymbol interference introduced by the channel.
  • the equalized signals are then provided over line 23 to a decoder circuit 24, such as a Viterbi decoder or any other suitable type of decoder, which outputs a digital data stream over line 25 that is a reproduction of the transmitted digital data.
  • a decoder circuit 24 such as a Viterbi decoder or any other suitable type of decoder
  • Timing recovery circuit 26 uses the output of decoder 24, also referred to as the decisions, and the unequalized received signal samples from sampler 20 to generate a control or clock signal provided over line 27 to adjust the sampling phase of sampler 20. Timing recovery schemes which utilize the decoder output to generate the timing error signal, such as with the present scheme, are referred to as decision directed timing recovery.
  • the control signal derives from an error signal which, as described below, is related to the levels of the timing sample points, e.g.. the ones taken before and after the controlled (or decoder) sample point. In the example described below, the timing sample points are the points taken on either side of the controlled or peak sample point of each impulse.
  • Sampler 20 may be configured as shown in FIG. 1A with a switch 28 which samples the analog input signal at the sampling epoch controlled by the clock signal from timing recovery circuit 26 provided over line 27. Or, preferably, as shown in FIG. 1 B, it can include a switch 30 which samples at the sampling epoch controlled by a free running clock and a digital interpolator 32 which, operating under the control of the control signal from line 27, adjusts the sampling phase.
  • Timing recovery circuit 26, FIG. 2 includes delay 34, reference switch 36, timing error estimator 38 and numerical controlled oscillator (NCO) or voltage controlled oscillator (VCO) 40.
  • NCO numerical controlled oscillator
  • VCO voltage controlled oscillator
  • NCO 40 When switch 30 and digital interpolator 32, FIG. 1 B, are used for sampler 12, an NCO is used to generate from the timing error signal a sampler control signal z n .
  • the configuration of NCO 40 is depicted in FIG. 12 described below.
  • the samples from sampler 20 are provided to timing error estimator 38 through delay 34 which provides a fixed delay to compensate for the processing delays of adaptive equalizer 22 and decoder 16. The delay ensures that the samples being fed back to timing recovery circuit 26 from sampler 20 are the samples which produced the output from decoder 24 which is also being fed back to timing recovery circuit 26.
  • the other input signal to timing error estimator emanates from reference switch 36 which either directs thereto a timing reference signal or the signal from decoder 24.
  • a training sequence is undertaken to establish a sampling phase for sampler 20 which closely approximates the sampling phase necessary to sample the incoming PAM signal properly.
  • the training sequence is achieved by connecting reference switch 36 to the reference input.
  • the reference input signal is a good approximation of a correctly decoded signal, i.e. one that was sampled at the proper points on the impulses to be sampled.
  • This reference signal is provided to timing error estimator 38 which, in conjunction with the samples from sampler 20, provides an error signal to NCO 40 that sets the sampling phase of sampler 20 proximate the expected proper sampling phase.
  • impulses to be decoded are received by sampler 20 and reference switch 36 connects the output of decoder 24 to timing error estimator 38.
  • the decoded output signals which are now assumed to be a reliable representation of the signals that should be received, in conjunction with the unequalized data samples from sampler 20, which are samples of the actual received signals, are used by timing error estimator 38 to generate a timing error signal which in turn is used by NCO 40 to adjust the sampling phase of sampler 20 if it is sampling off of the desired sampling points of the incoming impulses which are being decoded.
  • NCO 40 averages a number of timing error signals before adjusting the sampling phase of sampler 20. This feedback loop maintains the appropriate sampling phase which allows the received impulses to be sampled at the desired sampling points.
  • Timing error estimator 38 is shown in more detail in FIG. 3 to include timing error generator 42 and self-noise canceller 44.
  • Timing error generator 42 receives two inputs, one from decoder 24 over line 45 and one from self-noise canceller 44 over line 46 and generates the timing error signal discussed above which is provided to NCO 40.
  • Self-noise canceller 44 receives the output of decoder 24 and the output of delay 34, FIG. 2.
  • the unequalized samples from delay 34 include contributions from the impulse which is to be decoded as well as the self-noise from the overlapping impulses.
  • Self-noise canceller 44 produces an estimate of the self-noise generated by the channel without using feedforward taps and those contributions are subtracted from the samples before the samples are provided to timing error generator 42.
  • the timing error signal is thus generated without the self-noise contributions from the channel and without the perturbations caused by the adaptive equalizer associated with some conventional timing recovery schemes.
  • These conventional timing recovery schemes do not use the output of the sampler as an input to the timing recovery circuit (the other being the decoder output), but rather, these systems use the output of the adaptive equalizer.
  • perturbations in the feedforward equalizer taps of the adaptive equalizer cause jitter in the clock signal which reduces the ability of the sampler to sample very close to the desired sample points.
  • Timing error generator 42 which is configured in a known manner, except that one of its inputs is from self-noise canceller 44, is depicted in more detail in FIG. 4.
  • the function of timing error generator 42 is to determine if sampler 20 is sampling at the desired sample points on each impulse which is to be decoded or if it is sampling too early or too late and, if it is, to generate a timing error signal which will enable the sampling phase of sampler 20 to be adjusted accordingly.
  • Timing error generator 42 is only exemplary, as any comparable timing error generator could be used with this invention.
  • FIG. 5 there is shown an example of a portion of a received PAM signal 50 x(t) which is input over analog loop 17, FIG. 1 , to sampler 20.
  • PAM signal 50 is the sum of a number of overlapping impulses g(t).
  • the impulse of interest 52 which is the impulse to be presently decoded, is depicted in FIG. 6 being properly sampled at the stable point of the timing recovery loop.
  • the controlled sample point g 0 57 is properly taken at the peak of impulse 52, and, because it is properly sampled, timing sample points g.
  • 1/2 58 and g 1/2 59 are equivalent in magnitude. If sampler 20, FIG. 1 , is sampling too early, the peak or controlled sample point g 0 57', FIG. 7, is not taken at the peak of impulse 52 and the magnitudes of timing sample points g. 1 2 58' and g 1/2 59' are unequal, with the point g. ⁇ /2 58' having a lower magnitude than point g 1 2 59'. This difference in magnitude is referred to as the bias 60.
  • sampler 20 can sample impulse 52 too late as depicted in FIG. 8. In that case peak or controlled sample point g 0 57" is not located at the peak of impulse 52. Consequently, timing sample points g. ⁇ 2 58" and g 1 59" are not equal in magnitude and sample point g. 1/2 58" is greater in magnitude than point g ⁇ 2 59", creating a bias 60.
  • the output of self-noise canceller 44 is provided to a first delay block 70, which provides a delay of one half of the impulse or symbol period T, and to summer 72.
  • the output of delay 70 is provided to a second, identical delay block 74 whose output is connected to the other input of summer 72.
  • the first input to summer 72 directly from self-noise canceller 44 is the sampled point after the peak on each impulse, e.g. point g 1 2 58, FIG. 6, and since there are two T/2 delays the other input to summer 72 is the sampled point before the peak sampled point, e.g. sample point g_ ⁇ /2 56, FIG. 6.
  • the procedure to start up the connection is for the modem to quickly estimate the channel response, i.e. the shape of the received pulses, as well as the initial timing offset. This is typically done with the help of training sequences, and various techniques to do this are well known in the art. These estimates can be used to jam the timing and self-noise canceller coefficients such that the user data transmission can be started as soon as possible.
  • a disadvantage of the timing error generator of FIG. 4 is that if the initial sampling phase is off from the stable point, the self-noise canceller coefficients will need to be re-estimated after the timing jam. This unnecessarily increases start-up time.
  • An improved timing error generator 42a is depicted in FIG. 9.
  • Timing error generator 42a is configured similarly to timing error generator 42, FIG. 4, however, it includes a few unique and important components, namely, multipliers 80 and 82 which multiply the signal from self-noise canceller 44 by p and the delayed signal by q, respectively, and computation blocks 81 and 83.
  • multipliers 80 and 82 which multiply the signal from self-noise canceller 44 by p and the delayed signal by q, respectively, and computation blocks 81 and 83.
  • the values p and q are calculated by computation blocks 81 and 83, respectively, based on the initial channel estimates.
  • a summer 90 which adds the bias 60 to the output of summer 72a could be utilized to accomplish the same function.
  • the initial sampling phase is too late for the timing error generator of FIG. 4.
  • a large timing adjustment would be needed before the timing loop converges to its stable point.
  • the self-noise canceller will need to be re-estimated due to the timing adjustment.
  • the timing error generator of FIG. 9 the timing error is close to zero, i.e. no timing adjustment is needed since the loop is already operating near its stable point.
  • a received PAM signal such as signal x(t) 50, FIG. 5, is a superposition of impulses g(t), such as impulses 52, 54 and 56, each of which is scaled by an information symbol a k and delayed in time by kT.
  • the PAM signal may be described mathematically as follows:
  • timing error signal The estimate of the timing function is called the timing error signal.
  • a n * a n is equal to one, although the self-noise canceller of the present invention works equally well for general cases.
  • Examples of timing error signals for the three timing functions in equations (3), (4), and (5) above are, respectively:
  • ⁇ n (Xn+1 /2 " Xn-1/2) * ⁇ n
  • ⁇ n p Xn+1 /2 &n " Xn-1 /2 * ⁇ n
  • the difference between the timing function f( ⁇ ) and the estimate of the timing function e n is non-zero. This difference is due to the self-noise or intersymbol interference introduced to the PAM signal 50.
  • self-noise canceller 44 is employed to significantly reduce the amount of self-noise in the timing error signal.
  • the X n+ 1 /2 * a n term must be examined. This term can be expanded as follows:
  • the first term, g 1 2 on the right hand side of equation (10) contributes to the timing function and the remaining terms contribute only to the self-noise.
  • the self-noise terms can be substantially removed by estimating the summation term and subtracting it from the received signal sample x n+ i /2 to form a self-noise canceled received signal Tx n+1/2 :
  • TXn+1 /2 Xn+1/2 " ⁇ H g k+1/2 * 3n-k
  • self-noise canceller 44 is a device which produces the self-noise canceled signal Tx n+1 2 .
  • Self-noise canceller 44 includes a channel estimator block 100 which produces estimates of the impulse waveform samples Hg k+1/2 . for example, timing sample estimates Hg 1 2 101 , Hg. 1/2 102, i.e. those which do not contribute to self-noise and self- noise sample estimates Hg 3 2 103, and Hg. 3 2 104, etc. which of course do contribute to self-noise.
  • Channel estimator block 100 is in this embodiment a least means square (LMS) estimator; however, any comparable estimation algorithm could be used.
  • LMS least means square
  • the decoder 24 output or decisions are provided to a series of cascaded delay blocks of which five, 106-110, are depicted.
  • the number of delay blocks used in a particular application depends on the spreading of the impulse. If more spreading is desired, more delay blocks are utilized.
  • the input to the first delay block 106, the digital output, and the outputs to the remaining delay blocks, the delayed digital outputs, are provided to a number of multipliers 112-119.
  • the other inputs to the multipliers come from the estimates of the impulse waveform samples from channel estimator block 100.
  • the products output from all of the multipliers, except 115 and 116, are the estimates of the self-noise terms and are provided to summer 120 which subtracts these self-noise terms from the received samples from delay 34 after the samples have been sampled down by two by sampler 122.
  • the self-noise canceled sample or signal Tx n+1 2 is output to timing error generator 42, FIG.3. That sample or signal is also supplied to summer 124,
  • FIG. 10 which receives at one of its other two inputs the product from multiplier 115 of sample Hg. 1/2 and the delayed a n term from the input of the center delay block 108 and at its other input the product from multiplier 116 of the sample Hg 1 2 and the delayed a n term from the output of the center delay block 108.
  • the output of summer 124 is provided to channel estimator block 100.
  • Self-noise canceller 44 does not remove from the samples the term Hg. 1 2 * a n . ⁇ which also contributes to self noise. However, when using the timing error signal of equation (7) which was used to implement self-noise canceller 44, it is unnecessary to remove this term. This is because at the stable point the term cancels during an averaging of the timing error signal which occurs in NCO 40.
  • the canceling effect is illustrated by the following:
  • g. 1/2 is approximately equal to g 1/2 and the term g. 1/2 * an * a n+1 cancels term g 1/2 * a n * a n ., when e n are averaged.
  • the present invention which utilizes self noise canceller 44 effectively decouples the timing recovery from the adaptation of the channel, in the sense that perturbations in the estimates (Hgk +1/2 ) do not change the stable point of the timing loop. This results in increased accuracy and fast tracking capability of the timing loop.
  • self noise canceller 44a uses the channel estimator 100a outputs (Hgk +1/2 ) to directly estimate the timing function by forming the timing error signal as follows:
  • the timing error signal could alternatively be formed as:
  • Channel estimator block 100a operates in the same manner as block 100, FIG. 10; however, instead of outputting the self-noise canceled received samples to timing error generator 42, FIG. 3, the channel estimates Hg 1 2 101 a and Hg. 1/2 102a of the timing sample points which are substantially free of self-noise, are summed by summer 124a and their difference is the timing error signal which is directly supplied to NCO 40.
  • the channel estimates Hg ⁇ /2 101a and Hg. ⁇ 2 102a along with all of the other channel estimates are multiplied by the decisions, a n , from decoder 24 by multipliers 112a-119a. These products are summed by summer 120a with the received samples sampled down by two by sampler 122a and the output is provided to channel estimator block 100a.
  • the self-noise canceling occurs within channel estimator block 100a.
  • Estimator block 100a utilizes more taps than necessary to compute the timing error signal and those extra taps serve to remove the self-noise and thus provide self-noise free estimates Hg ⁇ 2 and Hg. ⁇ 2 of the timing sample points.
  • NCO 40 One exemplary implementation of NCO 40 is shown in detail in FIG. 12.
  • the timing error signal from timing error generator 42 or directly from self-noise canceller 44a is provided to timing error averager 128 which averages a predetermined number of timing error signals.
  • the averaged timing error signal is then provided to both multipliers 130 and 132 which multiply the signal with filter parameters (a) and (b), respectively.
  • the output of multiplier 132 is provided to summer 134 which sums it with the output of summer 134 delayed by delay 136 for one period T.
  • the output of summer 134 is also provided to summer 138 which sums it with the output of multiplier 130 and the output of delay 140.
  • the output of delay 140 is also the control signal z n which is provided to sampler 20 over line 27, FIG.1. Control signal z n instructs the interpolator to adjust the sampling phase to sample the PAM signal either earlier or later and the extent of the phase adjustment.

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  • Computer Networks & Wireless Communication (AREA)
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Abstract

Un récepteur de données (18) échantillonne de manière périodique en des points d'échantillonage prédéfinis un signal analogique reçu, et produit à partir de ce dernier une sortie numérique. Ce récepteur renferme un circuit (26) adaptable de récupération du rythme et d'élimination du bruit propre, qui se compose: d'un éliminateur de bruit propre (44), qui réagit aux échantillons et à la sortie numérique, pour évaluer approximativement de manière adaptable la composante bruit propre des échantillons et pour éliminer la composante évaluée approximativement des échantillons de manière à produire des échantillons sensiblement exempts de bruit propre; d'un générateur d'erreur de base de temps (42) réagissant aux échantillons sans bruit propre et à la sortie numérique, pour générer un signal d'erreur de base de temps proportionnel à la déviation statistique par rapport aux points d'échantillonnage prédéfinis du récepteur de données; et d'un dispositif de commande (40) réagissant au signal d'erreur de base de temps, pour régler la phase d'échantillonnage du récepteur de données et éliminer les écarts statistiques.
PCT/US1997/016935 1996-09-24 1997-09-19 Dispositif, systeme et methode pour l'elimination adaptable du bruit propre et pour la recuperation decisionnelle du rythme Ceased WO1998013968A1 (fr)

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Cited By (2)

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US6909388B1 (en) 2004-06-23 2005-06-21 Microchip Technology Incorporated Fractal sequencing schemes for offset cancellation in sampled data acquisition systems
DE10302434B4 (de) * 2002-03-14 2007-10-04 Mediatek Inc. Verfahren zum Rückgewinnen eines digitalen Dateninhalts in einem Kommunikationssystem und Vorrichtung zur Durchführung dieses Verfahrens

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Publication number Priority date Publication date Assignee Title
US5276711A (en) * 1990-07-11 1994-01-04 U.S. Philips Corporation Receiver for a data signal which includes data symbols occurring at a given Baud rate
US5537419A (en) * 1991-06-27 1996-07-16 Hughes Electronics Receiver sample timing adjustment using channel impulse response
US5588025A (en) * 1995-03-15 1996-12-24 David Sarnoff Research Center, Inc. Single oscillator compressed digital information receiver
US5694437A (en) * 1995-10-10 1997-12-02 Motorola, Inc. Device and method for data signal detection in the presence of distortion and interference in communication systems

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276711A (en) * 1990-07-11 1994-01-04 U.S. Philips Corporation Receiver for a data signal which includes data symbols occurring at a given Baud rate
US5537419A (en) * 1991-06-27 1996-07-16 Hughes Electronics Receiver sample timing adjustment using channel impulse response
US5588025A (en) * 1995-03-15 1996-12-24 David Sarnoff Research Center, Inc. Single oscillator compressed digital information receiver
US5694437A (en) * 1995-10-10 1997-12-02 Motorola, Inc. Device and method for data signal detection in the presence of distortion and interference in communication systems

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10302434B4 (de) * 2002-03-14 2007-10-04 Mediatek Inc. Verfahren zum Rückgewinnen eines digitalen Dateninhalts in einem Kommunikationssystem und Vorrichtung zur Durchführung dieses Verfahrens
US6909388B1 (en) 2004-06-23 2005-06-21 Microchip Technology Incorporated Fractal sequencing schemes for offset cancellation in sampled data acquisition systems

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