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WO1998013861A1 - Oxyde de masquage pour regions source et drain formees a partir de sources solides de dopants - Google Patents

Oxyde de masquage pour regions source et drain formees a partir de sources solides de dopants Download PDF

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Publication number
WO1998013861A1
WO1998013861A1 PCT/US1997/012052 US9712052W WO9813861A1 WO 1998013861 A1 WO1998013861 A1 WO 1998013861A1 US 9712052 W US9712052 W US 9712052W WO 9813861 A1 WO9813861 A1 WO 9813861A1
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WO
WIPO (PCT)
Prior art keywords
layer
source
substrate
oxide layer
dopant
Prior art date
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Ceased
Application number
PCT/US1997/012052
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English (en)
Inventor
Ebrahim Andideh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to JP10515614A priority Critical patent/JP2001501037A/ja
Priority to IL12915197A priority patent/IL129151A0/xx
Priority to EP97933371A priority patent/EP0958596A1/fr
Priority to AU36571/97A priority patent/AU3657197A/en
Publication of WO1998013861A1 publication Critical patent/WO1998013861A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H01L21/2256—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides through the applied layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the invention relates to the field of forming self-aligned source and drain regions for field-effect transistors from solid dopant sources.
  • Screening layers have been used in connection with ion implantation to, for instance, protect the surface of the silicon during ion implantation. These are relatively thick layers not suited for use with a solid dopant source as described above.
  • An improved process for forming a semiconductor device on a silicon substrate where a dopant is diffused from a doped layer into the substrate to form source and drain regions is described.
  • a thin oxide screening layer is formed between the doped layer and the substrate. The dopant is diffused through the oxide layer into the substrate to form the source and drain regions.
  • the oxide layer comprises a silicon based oxide having a thickness of between 5A and lOOA. This layer can be used to modulate the dopant diffusion into the silicon substrate.
  • Figure 1 is a cross sectional elevation view of a section of a substrate showing an n-well isolated from a p-well. Polysilicon gates and a screening oxide layer in accordance with the present invention are also shown.
  • Figure 2 illustrates the substrate of Figure 1 after the formation of a first doped glass layer over the screening oxide layer.
  • Figure 3 illustrates the substrate of Figure 2 after a first photoresist layer has been masked and etched, and during an ion implantation step used to form the tip regions for the n-channel transistor.
  • Figure 4 illustrates the substrate of Figure 3 after the formation of a TEOS layer and a silicon nitride layer.
  • Figure 5 illustrates the substrate of Figure 4 after the silicon nitride layer has been anisotropically etched to form spacers and after the substrate has been covered with a second screening layer and a second doped glass layer.
  • Figure 6 illustrates the substrate of Figure 5 after the masking and patterning of a photoresist layer and during an ion implantation step used to form the main portion of the source and drain regions for the n-channel transistor.
  • Figure 7 illustrates the substrate of Figure 6 after diffusion of the boron dopant from the glass layers through the screening layers to form the source and drain extension regions for the p-channel transistor.
  • Figure 8 is an enlarged section of the substrate of Figure 7 generally taken at section line 8-8 after etching of the second glass layer and second screening layer.
  • Figure 9 is a graph used to illustrate the modulating effects on source and drain region sheet resistance from the screening oxide layer of the present invention.
  • a method and structure is described for forming low damage, shallow source and drain regions in a field-effect transistor where a solid state dopant source and screening layer are used.
  • numerous well-known steps such as masking and etching steps are not discussed in detail in order not to obscure the present invention.
  • specific details are set forth such as specific boron dopant concentrations in order to provide a thorough understanding of the present invention. It will be apparent that the present invention may be practiced without using these specific details.
  • While the present invention is not limited to any particular geometry, in one embodiment, it is used for the fabrication of transistors having a sub micron channel length that operate from 2.5 volts or less supply.
  • n-well 21 a section of a monocrystalline silicon substrate is illustrated having an n-well 21 and a region designated as a p-well.
  • n-well 21 a region designated as a p-well.
  • p-well a region designated as a p-well.
  • an n-well may be used for fabricating p-channel transistors with the n- channel transistors being formed directly in the substrate.
  • n and p-well of Figure 1 are isolated from one another by a recessed isolation region, specifically trench 10. Additionally, within the n-well 21 there are other isolation trenches 12 for isolating from one another p-channel transistors formed within the n-well. Likewise, there are isolation trenches 13 formed within the p-well to isolate n-channel transistors formed in the p-well from one another.
  • the isolation trenches may be formed using well-known technology. Other isolation technologies such as local oxidation of silicon (LOCOS) may be used instead of trenches
  • a gate insulative layer (such as a high quality, thermally grown oxide to insulate the gate from the substrate) is formed over the substrate. Following this, a polycrystalline silicon (polysilicon) layer is deposited and the gates for the field-effect transistors are fabricated using ordinary photolithographic and etching techniques. Two such gates insulated from the substrate are shown in Figure 1. Gate 11, formed above the n-well, as will be seen, is used for a p-channel transistor; the other gate 14, formed above the p-well, is used for an n-channel transistor. Numerous steps typically used before the fabrication of the gates are not illustrated, such as cleaning steps, ion implantation steps to adjust voltage threshold, etc.
  • a screening oxide layer in accordance with the present invention is formed over the entire substrate.
  • This layer may be for instance, an undoped plasma formed oxide layer based on silane chemistry (e.g., SjH4 + N2O) or tctraethyl orthosilicate (TEOS) based chemistry (e.g., TEOS + O2 or O3).
  • the undoped layer may also be formed with chemical vapor deposition (CVD) processes. Other chemistries which provide an undoped silicon-based oxide layer may be used.
  • the oxide layers described above are between 5A and IOOA in thickness. In one embodiment, this undoped oxide layer is formed in the same chamber as that used to form the subsequently deposited doped glass layer. The oxide layer may also be formed in a separate chamber.
  • the screening oxide layer protects the substrate from for instance, the highly doped boron glass layer subsequently formed for a solid dopant source for the p-channel transistors.
  • the screening oxide layer prevents the formation of a film or skin that cannot readily be removed that would otherwise be formed at the interface between the doped glass layer and the substrate. Additionally, as will be discussed the screening layer aids in modulating the junction depth and dopant concentration of the source and drain regions.
  • borosilicate glass (BSG) layer 16 as shown in Figure 2 is deposited over the entire substrate.
  • This layer which may be 10 ⁇ A-3(X)A thick, in one embodiment has a 2% concentration of a p-type conductivity dopant (boron).
  • Layer 16 is referred hereinafter sometimes as the 2% BSG layer.
  • TEOS or silane based chemistry may be used to deposit the 2% BSG layer at a temperature of 350-6O0°C.
  • the p-channel transistor is formed using the screening oxide of the present invention while the n-channel transistor is formed using well-known ion implantation.
  • the screening oxide of the present invention may also be used between an n-type solid dopant source and the substrate where the n-channel transistors are formed from such a dopant source.
  • Figure 3 illustrates the first of two ion implantation step used in the formation of the n-channel transistor.
  • a photoresist layer 17 is formed over the substrate 15. This layer is masked and developed with well-known techniques to reveal the substrate regions where the source and drains are formed for the n-channel transistors and additionally, regions where an n-type dopant is used for well tap 20. This is shown in Figure 3 where the photoresist members 17 protect predetermined areas of the substrate while leaving exposed other areas.
  • the exposed portions of glass layer 16 are etched in alignment with the photoresist members 17. This etching step uses a hydrogen fluoride (HF) based solution. As shown in Figure 3 the doped glass layer 16 and screening layer 9 has been etched away.
  • HF hydrogen fluoride
  • the substrate is now subjected to ion implantation of an arsenic dopant as shown by the arrows 18. This forms the regions 19 in alignment with the gate 14 and a region 20 between the trenches 12.
  • This arsenic doping implant is relatively light and is used for forming the tip regions of the source and drain regions for the n-channel transistor.
  • the main portions of the source and drain regions for this n-channel transistor are subsequently formed with the second ion implantation step.
  • a conformal layer 30 of undoped silicon dioxide is formed by low pressure chemical vapor deposition; other undoped LPCVD oxide films may be used.
  • This layer provides an etchant stop for the spacers formed for the n-channel transistor.
  • the oxide layer 30 may be 5 ⁇ A-30 ⁇ A thick.
  • a conformal layer 31 of silicon nitride is formed over the TEOS layer 30.
  • This silicon nitride layer is approximately 80 ⁇ A thick in one embodiment
  • Well-known anisotropic etching is used to etch the silicon nitride layer to form spacers 31 shown on opposite sides of gates 1 1 and 14 of Figure 5.
  • the TEOS layer acts as an etchant step to protect the silicon.
  • the TEOS and BSG regions not covered by the nitride spacers are also etched away. A wet or dry etchant may be used for this purpose.
  • a second screen oxide is now formed over the substrate.
  • This oxide is formed in the same manner as the first screening oxide that is, it is an undoped Sj ⁇ 2 having a thickness of 5A to lOOA as shown by layer 22 of Figure 5. If in the prior processing the layer 9 is not removed from the exposed portions of the substrate, then the second screening layer is unnecessary since the second glass layer, which is subsequently formed would be screened from the substrate by layer 9.
  • a second layer 35 of BSG is formed over the second screening oxide. This time, however, the layer has a 6% concentration of boron (6% BSG).
  • This layer in one embodiment is approximately 10 ⁇ A-60 ⁇ A thick and is deposited using a TEOS or silane based chemistries at a temperature of 350-600°C.
  • a relatively thin cap layer e.g., IOOA
  • IOOA undoped glass or silicon nitride
  • This undoped layer protects the 6% BSG from a subsequent photoresist layer formed over the glass and assures that dopant will not diffuse upward.
  • This layer also prevents moisture from the environment and other process steps from reacting with the boron dopant.
  • a photoresist layer 40 is deposited, exposed and developed to open generally the same areas that were exposed in Figure 3 for n-channel devices. Specifically, gate 12, the areas adjacent to gate 12 (source and drain regions) and region 20; the remainder of the substrate shown in Figure 6 is protected by the photoresist members 40.
  • cap layer over the glass layer 35 (if used) and the 6% BSG layer 35 are then etched in alignment with the photoresist members 40, this is done by HF based chemistry. Again while in Figure 6 layer 22 has been etched at this point in the processing at the regions unprotected by photoresist layer 40. This is not necessary since the ion implantation can occur through layer 22.
  • the second n-type ion implantation step is now used to implant the arsenic dopant into the regions of the substrate not protected by the photoresist layer 40, spacers 31, or gate 12.
  • the arrows 41 illustrate the implantation of this arsenic dopant.
  • This dopant is used to form the main N+ portions 45 of the source and drain regions for the n-channel transistors. Note that since the spacers 31 are in place, the dopant is implanted in alignment with the spacers and not in alignment with the gate.
  • a driving (heating) step is used.
  • the p-type dopant from the 2% BSG and 6% BSG layers is simultaneously diffused though the screening layer 9 and 22 into the substrate to form both the tip regions, main source and drain regions, and doping of the gate 11 for the p-channel transistor.
  • the tip region has a depth of 300-700A and the main portion of the p-type region has depth of 1000-2500A.
  • the p-type dopant from the BSG layers forms a well tap between the isolation trenches 13.
  • this drive step employs rapid thermal processing. Specifically, driving at 950°C to 1080°C for 10-30 seconds with ramping up to and down from this temperature at 70°C per second. A standard Halogen lamp band rapid thermal reactor is used.
  • glass layers 16 and 35, and the underlying screening layers to the extent remaining may remain in place for the remainder of the processing and may stay in the completed integrated circuit except where removed for contacts. That is, glass layer 35 may be removed to facilitate a subsequent selective TiSi or CoSi2 layer on gates 1 1 and 12 and regions 41 and 45.
  • the result of the processing described above is a source and drain region for the p-type transistor having a tip region 40 adjacent to the gate (from the dopant diffused into the substrate from the 2% BSG layer 16) and a more highly doped main portion of the source and drain regions 41 spaced apart from the gate (from the dopant diffused from the 6% BSG layer 35).
  • the p-type tip region has a dopant concentration of l-5xl0 ⁇ c "3 while the main portion of the source and drain region has a dopant concentration of 2-5x1 ⁇ 20cm ⁇ 3. This results directly from the 2% and 6% BSG.
  • Other concentrations of dopants in the glass may be used.
  • layer 16 may have a dopant concentration between 1% to 4% and layer 35 may have a dopant concentration between 5% to 12%.
  • FIG 8 a portion of the region 41 of Figure 7 is shown with overlying screening oxide layer 22 and the glass layer 35. An opening has been formed through these layers to allow contact with the underlying region 41. A conductive plug 50 is disposed in the opening permitting contact with the region 41.
  • the screening oxide when the screening oxide is not used, the boron doping forms a film at the interface between the layer 35 and the substrate. This dopant-rich thin layer may prevent salicide formation or cause gate to source/drain current leakage. It is chemically difficult to remove this thin skin from the wafer surface. (The salicide formation problem is detected generally by measuring the contact resistance.) This problem is cured with the screening oxide of the present invention. The thin screening oxide prevents the formation of the difficult-to-remove dopant-rich layer found in the prior art. Thus, with the present invention as shown in Figure 8, a salicide is readily formed at interface 51.
  • the screening layer may be used to control post diffusion substrate dopant concentration and junction depth.
  • Figure 8 where sheet resistance is plotted against screening oxide deposition time.
  • the data from Figure 8 was obtained using a TEOS +O3 +(He carrier) chemistry to form the screening oxide. Ignoring initialization times, the oxide forms at the rate of approximately 5-6A per second for the example shown. Thus, at 5 seconds there is approximately 25A of the screening oxide.
  • the thicker the screening oxide the greater of the sheet resistance of the source/drain region.
  • the screening oxide thickness can be used to control the characieristics of the source/drain region.
  • the uniformity as measured by 4 point probe test were acceptable with no significant difference for any of the data points.
  • a screening oxide has been disclosed for use in the fabrication cf source/drain regions where the regions are formed by diffusing a dopant through the screening oxide from a solid dopant source.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention porte sur un oxyde de masquage (9, 22) intervenant dans la formation des régions source et drain (40, 41) d'un transistor MOS pour lesquelles le dopant provient d'une source (16, 35) solide. L'oxyde de masquage (9, 22) (d'une épaisseur de 5 à 100 Å) est formé entre le substrat et par exemple un verre (16, 35) recouvrant qui fournit la source de dopant dopé au bore qui constitue la source de dopant de la régions source/ drain (40, 41). Le dopant diffuse à travers la couche d'oxyde de masquage (9, 22). L'oxyde de masquage (9, 22) empêche la formation sur le substrat d'un film fortement dopé ce qui par ailleurs empêche la formation de saliciures. L'oxyde de masquage (9, 22) peut de plus servir à moduler la profondeur et la concentration du dopant des régions source et drain (40, 41).
PCT/US1997/012052 1996-09-24 1997-07-10 Oxyde de masquage pour regions source et drain formees a partir de sources solides de dopants Ceased WO1998013861A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP10515614A JP2001501037A (ja) 1996-09-24 1997-07-10 固体ドーパント源から形成されるソース領域およびドレイン領域用の酸化物の遮蔽
IL12915197A IL129151A0 (en) 1996-09-24 1997-07-10 Screening oxide for source and drain regions formed from solid dopant source
EP97933371A EP0958596A1 (fr) 1996-09-24 1997-07-10 Oxyde de masquage pour regions source et drain formees a partir de sources solides de dopants
AU36571/97A AU3657197A (en) 1996-09-24 1997-07-10 Screening oxide for source and drain regions formed from solid dopant source

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US71677296A 1996-09-24 1996-09-24
US08/716,772 1996-09-24

Publications (1)

Publication Number Publication Date
WO1998013861A1 true WO1998013861A1 (fr) 1998-04-02

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PCT/US1997/012052 Ceased WO1998013861A1 (fr) 1996-09-24 1997-07-10 Oxyde de masquage pour regions source et drain formees a partir de sources solides de dopants

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EP (1) EP0958596A1 (fr)
JP (1) JP2001501037A (fr)
KR (1) KR20000048595A (fr)
AU (1) AU3657197A (fr)
IL (1) IL129151A0 (fr)
WO (1) WO1998013861A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12402397B2 (en) 2021-10-26 2025-08-26 Renesas Electronics Corporation Semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006072976A1 (fr) * 2005-01-05 2006-07-13 Saga University Procédé de fabrication d’élément semi-conducteur

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996168A (en) * 1987-11-07 1991-02-26 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing P type semiconductor device employing diffusion of boron glass
US5141895A (en) * 1991-01-11 1992-08-25 Motorola, Inc. Semiconductor device process using diffusant penetration and source layers for shallow regions
US5407847A (en) * 1991-05-03 1995-04-18 Motorola Inc. Method for fabricating a semiconductor device having a shallow doped region

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996168A (en) * 1987-11-07 1991-02-26 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing P type semiconductor device employing diffusion of boron glass
US5141895A (en) * 1991-01-11 1992-08-25 Motorola, Inc. Semiconductor device process using diffusant penetration and source layers for shallow regions
US5407847A (en) * 1991-05-03 1995-04-18 Motorola Inc. Method for fabricating a semiconductor device having a shallow doped region

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12402397B2 (en) 2021-10-26 2025-08-26 Renesas Electronics Corporation Semiconductor device

Also Published As

Publication number Publication date
AU3657197A (en) 1998-04-17
KR20000048595A (ko) 2000-07-25
JP2001501037A (ja) 2001-01-23
IL129151A0 (en) 2000-02-17
EP0958596A1 (fr) 1999-11-24

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