WO1998001962A1 - Low-noise, high rms switching power supply for broadband signal distribution system - Google Patents

Abstract

This invention discloses a power supply and inverters for a broadband signal distribution system in which electrical power is coupled with broadband signals and transmitted through a coaxial cable. The system includes a head-end for providing the broadband signals and a trunk for coupling the broadband signals to a plurality of distribution nodes, each of which are coupled to a distribution network of feeder lines for delivering broadband signals to a plurality of consumer sites. The distribution nodes further include an electrical switching power supply for the generation of electrical power having a slowly varying AC waveform. Preferably, the AC waveform is trapezoidal so the RMS value of power delivered is greater than that previously achieved with sinusoidal waveforms with the same peak voltage. Because a trapezoidal waveform has smoother transitions, the trapezoidal waveform results in reduced harmonics, thus less change of interference. Furthermore, compared to DC, an AC waveform results in lower probability of switch corrosion. The inverters of the power supply include a regulator for controlling a switching network of the power supply. Each regulator includes a processor, a feed forward circuit to efficiently regulate the voltage of the AC waveform, and a current overshoot circuit. The processor and current overshoot circuit enable the switching network to receive control signals from the feed forward circuit to reduce current overshoot on said inverter outputs. The inverters are coupled together through a synchronization line and polarity lines to control the timing for the output of the trapezoidal waveforms so that ramp up and ramp down portions of the waveform start at approximately the same time. The synchronization of the output waveforms reduce the likelihood of inducing noise in the broadband signals coupled with the AC power onto the feeder lines.

Description

LOW-NOISE, HIGH RMS SWITCHING POWER SUPPLY FOR BROADBAND SIGNAL DISTRIBUTION SYSTEM

BENEFIT OF EARLIER PROVISIONAL APPLICATION & CROSS-REFERENCE

This application claims the benefit of U.S. Provisional Application No. 60/021313 filed

July 8, 1996. The present application is related to copending application filed concurrently herewith, APPARATUS AND METHOD FOR OPTIMIZING POWER DISTRIBUTED IN A

BROADBAND SIGNAL SYSTEM, assigned to the assignee of the present patent application. The copending application is incorporated herein by this reference.

FIELD OF THE INVENTION

The present invention relates to power supplies and more particularly to switching power supplies for use in the field of broadband signal distribution systems.

BACKGROUND OF THE INVENTION A typical broadband system, such as a CATV system, has a head-end that supplies broadband signals over a distribution network to a plurality of consumers at remote sites. The head-end typically receives or generates broadband signals which are provided to distribution nodes over one or more trunk lines. From the distribution nodes, the broadband signals are typically distributed over coaxial cables, known as feeder lines, to a termination node. Between the distribution and termination nodes, consumers 'tap' a feeder line to receive the broadband signals at a remote site.

Tapping the feeder line and the impedance of the line itself attenuate the broadcast signals. To maintain the signals at a level where they may be tapped by subsequent consumers, active components, such as amplifiers, are provided along the feeder line. These active components may be powered by coupling them to power from an electric utility at a particular site, or the power may be supplied by the same the feeder line coaxial cable that supplies the broadband signal. At a consumer's site, a converter converts the broadband signals into a form that may be used to drive a television or the like. The converter typically is powered by the consumer's household circuits.

A number of innovations affect the delivery of broadband signals over a typical CATV system. One is the introduction of fiber optic cables for transmitting the broadband signals from the head-end to the distribution nodes. Fiber optic cables support higher bandwidths than previous trunk line cables for the transmission of data between the head-end and the distribution nodes. However, fiber optic cables cannot transmit power at the level required for operation of the active components of the distribution network. For that reason, power cannot be supplied from a large power supply at the head-end to the distribution nodes.

If an electrical power source is to be placed at each distribution node for powering components on the network, a number of factors must be considered. For one, if only one supply is to be provided, then all of the feeder lines emanating from the node must be supplied by the single supply. As a result, load changes on one feeder line can adversely affect the electrical power delivered to the other feeder lines. Additionally, reliance on a single power source prevents the feeder lines from being independent from one another. Further, the power and broadband signals are coupled to the feeder lines at the combiner. However, the coupling of multiple power supplies at a single distribution node can generate interference between feeder lines. Also, alternating power coupled to lines in proximity to one another can cause noise in the broadband signals.

Another innovation affecting the delivery of broadband signals through a CATV system is the advent of cable-ready televisions. These televisions do not require separate converters to display all the channels available through the CATV system. However, the distributor of the broadband signals (the system operator) typically does not want all of the channels to be accessible to all of the users. Instead, the subscribers to the system must pay for access to different channels. Accordingly, the CATV system operators prefer that a device be available at each subscriber's site for controlling access to the channels over the CATV system. While cable-ready TVs may be coupled to a CATV cable to provide access to the broadband services on the CATV system, they are not necessarily compatible with the signals used to control receipt of CATV channels. One way CATV operators can control access to the system is to install network interface units (NIUs), which typically are located on the outside of a subscriber's home to provide easy access by CATV system service personnel. Rather than relying on power from a consumer's circuit, broadband signal system operators would prefer to supply electrical power to the NIUs through the same coaxial cable that provides the broadband signal.

To be compatible with the data communicated over the coaxial cable, the supplied power must meet a number of criteria. For example, the power must be delivered so that it does not generate excessive noise on the broadcast channels carried by the coaxial cable. This can be achieved by providing DC power over the coaxial cable. However, DC power has some drawbacks. At the consumer site, a switch is provided to permit the subscriber to tap the feeder line. The contacts in this switch provide a conductive path from the central conductor of the coaxial cable to ground at the customer site. DC current through the conductive path in the switch can cause electrolysis and the metal on one contact can thereby migrate to the other contact. This migration of metal corrodes the switch. A second drawback with DC voltage is the risk of electrical shock. A person who contacts DC voltage is less likely to release it because of the steady current supply. These problems may encourage one to consider supplying the power with an AC waveform. However, prior art AC power supplies deliver power at frequencies that can generate electrical noise that interferes with the transmission of broadband signals over the cable.

What is needed is a way of efficiently delivering electrical power to active components in a broadband signal distribution network without corroding switches, without interfering with transmission of broadband signals, and while reducing the risk of electrical shock. It is to the provision of such that the present invention is primarily directed. SUMMARY OF THE INVENTION

The subject invention solves the above problems noted in the delivery of power through broadband systems by using a switching power supply that generates a slowly varying AC waveform. The inventive power supply includes a switching network for converting DC power to AC power, and a waveform regulator that controls the switching network to generate a slowly varying AC waveform. The preferred waveform is trapezoidal with a frequency of 1 to 10 Hz. The high-frequency components of a trapezoidal waveform are lower than that of a square waveform, thereby minimizing interference. Also, the power supply can closely control the frequency of the output waveform at a relatively low frequency. The trapezoidal waveform and its low frequency result in significantly reduced interference as compared with that generated by conventional AC switching power supplies.

The trapezoidal waveform has higher RMS (yielding greater power) than a sinusoidal waveform of equal maximum voltage. Thus, the required power output can be produced at a lower voltage, representing a reduced hazard of electrocution. The alternating power reduces electrolysis and the consequent switch corrosion. Thus, the power supply of the present invention is a safer and more reliable way to power active components in a broadband distribution system, especially those at a consumer's site, without interfering with the broadband signals transmitted over the system. A system operator can install the inventive power supply at distribution nodes in a broadband system to construct an efficiently powered broadband system. Such a system can utilize the increased capacity of fiber optic cables for coupling a head-end to distribution nodes, thus expanding the delivery of broadband signals to the distribution nodes, while providing efficient power to the system's active components on the feeder lines coupled to the nodes. Input power to the power supply can be provided from an electric utility, which power is converted by the waveform regulator of the subject invention to low frequency AC for delivery to consumer sites through the coaxial cable of a CATV system. The power supply can be supplemented with battery or generator back up, thereby providing auxilliary power in the event of a power outage, thereby enhancing the reliability of the power delivered by the distribution nodes.

Preferably, the waveform regulator of the inventive power supply preferably generates an AC trapezoidal waveform to deliver electric power at a RMS level that is significantly greater than power delivered at typical AC frequencies using sinusoidal waveforms. The resulting delivery of power to supply the amplifiers and the network interface units of a CATV system is very efficient and results in significant cost savings. The trapezoidal shape of the waveform reduces the high frequency components associated with a square wave at the step transitions (which can induce noise in the broadband signals). The AC power also reduces the chance of metal migration or electrolysis at the switch. Additionally, the slowly varying waveform generated by the present power supply reduces the risk of electrical shock to persons and induces less noise than AC power forms delivered at normal frequencies.

The waveform regulator of the present invention preferably includes a feed forward circuit and current overshoot circuit to prevent problems arising from fluctuations in the input supply. Preferably, an alternating current input from an electric utility is rectified to supply direct current to an inverter which in turn supplies power to a feeder line. A coupling switch couples the input supply to the output lines. The inverter regulates the output waveform shape and voltage. This switching control is performed by a processor which provides the desired output voltage value to a feed forward circuit.

The feed forward circuit compares the output voltage to the input voltage and generates signals to control the duration of the operation of the coupling switch. This way, the supply prevents the output voltage from following variations in the input voltage which otherwise can cause the output voltage to exceed its regulated range. Thus, if the output voltage exceeds its regulated maximum, the processor reduces the output voltage provided to the feed forward circuit, thereby the coupling switch is turned on for a shorter duration, thereby decreasing the output voltage. The output voltage provided to the feed forward circuit can correspond to the voltage to be output by the inverter or it can be a reference voltage used by the feed forward circuit for the comparison of output voltage to the input voltage.

In a similar manner, a current overshoot circuit monitors the inverter's current output. If the current magnitude exceeds a predetermined threshold, the overshoot current circuit turns off the coupling switch, thereby clipping the current. Thus, the current is maintained below the distribution system inductors' saturation level. Such saturation can cause current hum modulation, that is, noise induced in the tapped broadband signals at the tap point. Thus, the current overshoot circuit helps prevent current hum modulation. The power supply of the present invention includes multiple inverters. Preferably, each feeder line is powered by a separate inverter. Since the combiner couples the broadband signals and power for each feeder line in proximity to one another, the inverters are controlled to synchronize the output voltage waveform from each inverter to avoid inducing noise in the broadband signals. This synchronization is achieved by each inverter logically releasing a synchronization line, the last inverter releasing the line causes the logic state of the line to change. In response to this change, each inverter begins to change its output voltage in the same direction. This scheme causes the inverters to output voltage waveforms having approximately the same values at approximately the same time. Such synchronization reduces the likelihood of noise being induced in the broadband signals coupled to the feeder line. These and other advantages and features of the present invention will be readily ascertained from the detailed description and further reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS These and other features of the present invention will be more fully disclosed in the following detailed description of the drawings in which like numerals represent like elements and in which: FIG. 1 is a block diagram of a broadband system which uses a power supply incorporating the power supply of the present invention to deliver power to consumer sites;

FIG. 2 is a block diagram of a preferred embodiment of the power supply used in the broadband system of Fig. 1 ;

FIG. 3A is a schematic diagram depicting a trapezoidal waveform produced by the power supply used in the present invention;

FIG. 3B is a diagram of a portion of the waveform of FIG 3A as it approaches zero volts; FIG. 4 is a block diagram of the inverter of the power supply shown in FIG. 2;

FIG. 5 is a block diagram of a feed forward circuit used in the inverter of Fig. 4; FIG. 6 is a process flowchart depicting operation of the inverter of Fig. 4; FIG. 7 is a process flowchart depicting control of the voltage ramp up of a waveform produced by the inverter shown in Fig. 4; FIG. 8 is a process flowchart depicting control of the voltage ramp down of a waveform produced by the inverter of Fig. 4;

FIG. 9 is a process flowchart depicting control of the switching of the inverter shown in Fig. 4 in response to the waveform voltage crossing the zero volts level;

FIG. 10 is a process flowchart depicting monitoring of the crest voltage of the waveform produced by the inverter of Fig. 4;

FIG. 1 1 is a block diagram of an output current monitoring circuit used in the inverter of Fig. 4 to control current overshoot; and

FIG. 12 is an electrical schematic of a tap used in a network interface unit at a consumer site shown in Fig. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

An inventive broadband signal system that effectively delivers power to subscriber sites is shown in Fig. 1. The inventive system 10 includes a broadband signal source 12 which supplies broadband signals, such as video broadcast services, to one or more trunk lines or trunks 20. The broadcast services are transmitted over a trunk 20 which can be a fiber optic cable. Each trunk 20 is coupled to one or more fiber/coaxial distribution nodes 22 (only one shown for clarity). At node 22, the fiber optic cable is coupled to coaxial cable feeder lines 24 for distribution of the broadband signal and power to consumer sites 26. Each feeder line 24 ferminates in a termination block 18. Taps 16 divert a portion of the broadband signals to a consumer site 26. The diverted signals are coupled to a network interface unit (NIU) 28 which controls the signals that may be accessed by a consumer site 26. Amplifiers 14 maintain the broadband signals at an adequate level so subsequent sites 26 can tap the signals. System 10 can also be a communication system such as a telephone utility where the signal source 12 is a central office and the trunk and feed lines carry voice and data signals.

To deliver electrical power to operate amplifiers 14 and NIUs 28, a power supply 30 (Fig. 2) preferably is provided at nodes 22 to generate a slowly varying AC trapezoidal waveform. Power supply 30 can receive power from an electric utility, and convert the power to a low frequency AC. Delivering power at the low frequency AC reduces electrolysis at the NIU 28. The preferred power output is a low frequency trapezoidal waveform, preferably with a frequency of about 1 to 10 Hz, although frequencies of up to approximately 60 Hz may be used. The RMS power delivered by the preferred trapezoidal waveform to amplifiers 16 and NIUs 28 is greater than that typically delivered by sinusoidal AC waveforms at the same peak voltage, thus reducing operating costs for system 10. Power supply 30 can be further supplemented with battery backup and/or a generator, to supply power in the event of a power outage. Thus, the delivery of power from the distribution node 22 is made more reliable.

A preferred embodiment of power supply 30 is shown in FIG 2. Power supply 30 includes an AC distribution panel 32, input rectifiers 34, and power inverters 36. A fifth inverter 36R is a redundant inverter to replace one of the other inverters 36 if one becomes defective. AC distribution panel 32 delivers AC power, such as that supplied by electric utilities, to rectifiers 34. Rectifiers 34 convert the AC power to DC power and supply the rectified power to inverters 36 through leads 60. Combiner 40 couples the power output of each inverter 36 to the broadband signal from trunk transceiver 44, and transmits the combined signal and power through coaxial cables 24.

Instead of rectified power from rectifiers 34, or back-up power in case of electric utility power outage, battery 50 may supply DC power to rectifiers 34. Battery 50 supplies power to inverters 36 through leads 50A. A charger module 48 and motor generator 52 will further enhance the reliability of battery. Generator 52 may operate on natural gas, propane, or gasoline. Charger module 48 monitors the battery voltage and activates motor generator 52 if it senses a voltage drop below a predetermined threshold, thus maintaining battery 50 at or near capacity. Each of the inverters 36 supply a slowly varying AC, preferably trapezoidal, waveform, which is coupled through combiner 40 to the broadband signal, and distributed through coaxial cables 24 to the group of consumers coupled to a distribution node. Inverters 36 provide status information to a controller 46 which monitors the operation of the power supply 30 and reports the overall status of the power supply 30 to broadband signal source 12 (of Fig. 1). Status information is supplied to source 12 by controller 46 through trunk receiver 44 and trunk 20. Preferably, four inverters 36 are coupled to supply power to cables 24. A fifth inverter 36R is provided as a redundant inverter to replace one of the other inverters if one becomes defective. Controller 46 controls and monitors the inverters 36 and charger 48 through bus 46A. FIG. 3 A depicts the preferred trapezoidal waveform generated by power supply

30. The slew rate of the initial ramp up voltage is preferably fixed as described below. After reaching the predefined crest voltage, V_c, a timer is used to regulate the length of the crest voltage. As discussed more fully below, each inverter 36 (Fig. 2) indicates it is ready to ramp the output voltage down and after the last inverter so signals, the inverter ramps the output voltage down to zero at the same predetermined slew rate used to ramp up the output voltage. At the zero voltage, the inverters signal each other to reverse polarities so the output waveform goes negative and the waveform ramps up to a maximum negative voltage as described more fully below. Again, the crest voltage is maintained for a predetermined time, after which the inverters 36 synchronize the ramp down to zero volts of output voltage waveform. Thereafter, the cycle repeats.

The waveform of FIG. 3A demonstrates the high efficiency and symmetry of the delivered power. First, for a given peak voltage, the area under the trapezoidal waveform shown in FIG. 3A is larger than the area under a sinusoidal waveform with a comparable crest voltage. Therefore, the RMS value for the voltage and current supplied by inverter 36 is greater than an AC sinusoidal waveform. Second, the area under the positive and negative portions of the trapezoidal waveform are very nearly the same, reducing the possibility of metal migration or electrolysis at the switches as caused by a DC power. Third, the linear slope of the trapezoidal waveform at the transition points reduces high frequency components which may induce noise in the broadband signals. A square waveform has high frequency components at the transition points which may induce noise in the broadband signals. Thus, the trapezoidal waveform permits power supply 30 to provide power at a greater RMS level than sinusoidal waveforms without inducing the noise caused by a square waveform.

An overview of the inverter 36 is shown in Fig. 4. Inverter 36 includes a regulator 59 and a switching network 57. The switching network 57 is coupled to positive and negative DC input lines 60 and 62, and AC output lines 64 and 66. The input lines are coupled to the output lines through switches 68, 70, 72, and 74. The control of these switches is discussed in more detail below. Inductor 76, capacitor 78, and the capacitor/ resistor combination 80 and 82 filter the output voltage waveform.

Microprocessor 90 controls regulator 59 which regulates the switching of switching network 57 through a pulse width modulating (PWM) latch 92, a feed forward circuit 94, a pair of exclusive OR gates 96, 98, a pair of AND gates 100, 102, and overshoot circuit 104.

To prevent ripple in the input supply from appearing in the output voltage, microprocessor 90 and feed forward circuit 94 monitor the output voltage through voltage level shifter 125. Overshoot circuit 104 monitors the current output on line 64 and line 66 and interrupts the driving of switches 68 and 70 to reduce current overshoot in the output. All of the inverters 36 in power supply 30 are coupled together through the SYNC, POS, and NEG lines. Each of the microprocessors 90 in the inverters 36 can pull the SYNC, POS, or NEG lines low through the action of switches, 106, 108, 110, said action switched preferably being FETs. Additionally, the conditions of the POS, NEG, and SYNC lines may generate interrupts through latches 1 12 and 113.

Microprocessor 90 controls the waveform output of the present inventive power supply as follows: at the start of operation, microprocessor 90 asserts a logic high on the POSI line so that switch 72 is turned off and switch 74 is turned on. This couples output line 64 to positive input line 60 and couples output line 66 to negative input line 62. Microprocessor 90 then asserts a logic high on the SCFIRST line so the output of the feed forward circuit 94 first turns on switch 68, and then switch 70. By driving the GOPOS line high, microprocessor 90 pulls the POS line to a logic low, triggering the other inverters 36 to begin ramping up the output voltage in their corresponding inverters 36. Microprocessor 90 then clears the PWM latch 92 so the Q output of PWM latch 92 is input to feed forward circuit 94 enabling feed forward circuit 94 to receive digital values from microprocessor 90. The Q output provides microprocessor 90 with a signal for synchronizing its output of digital voltage values to feed forward circuit 94.

As explained below, feed forward circuit 94 changes the duration of the output signal supplied to gates 96 and 98. The output of feed forward circuit 94 has a period which corresponds to the clock period that drives the PWM latch 92. However, as microprocessor 90 changes either a reference voltage level or an output voltage level to the feed forward circuit 94, the switching signal output by feed forward circuit 94 for switch 68 becomes increasingly longer or shorter to vary the duration that the DC input lines 60 and 62 are coupled to output lines 64 and 66. During the ramp up portion of the waveform, microprocessor 90 continues to increase the output voltage level provided to feed forward circuit 94 so that input line 60 is coupled to output line 64 for increasingly longer duration. This causes the output voltage on line 64 to become increasingly positive. Microprocessor 90 maintains the output voltage level at the last value output for a predetermined duration to hold the output voltage at the crest voltage. The output voltage between 64 and 66 remains stable at the crest voltage as long as the output current does not exceed the limit set by microprocessor 90 in the overshoot circuit 104 and no ripple appears in the input voltage.

Upon expiration of the crest voltage time period, microprocessor 90 brings the GOSYNC line to a logic low to turn off FET 106 and release the SYNC line. Microprocessor 90 then sets a synchronization timer for a period of time to wait for the other inverters 36 in power supply 30 to release the SYNC line, causing all the inverters to begin the negative portion of the output waveform at approximately the same time. When all the inverters have released the SYNC line, the SYNC line goes to a logic high state and latches a signal through latch 112, which generates an interrupt to the microprocessor 90. In response to the interrupt, each microprocessor 90 in inverters 36 clears its respective PWM latch 92 so feed forward circuit 94 and microprocessor 90 are synchronized to ramp down the output voltage. Again, microprocessor 90 provides output voltage level values to feed forward circuit 94 to continue the signal driving switches 68 and 70 so switch 70 remains on for longer duration. This action couples output line 64 to negative DC input line 62 for increasingly longer duration so the output voltage line is decreased, at a controlled slew rate, to zero volts.

When microprocessor 90 outputs the zero output voltage level to feed forward circuit 94, it sets a zero crossing timer and brings the GOPOS line to FET 108 to a logic low which releases the POS line. When all of the inverters have released line 108, the POS line goes to a logic high and generates an interrupt to all the microprocessors 90 for the inverters 36.

If all the microprocessors 90 do not release the line before expiration of the timer, microprocessor 90 detects an error condition in the synchronization of the inverters and processes the error condition in a manner discussed in more detail below. If all the microprocessors released the POS line before expiration of the zero crossing timer, an interrupt is generated by latch 1 13 causing microprocessor 90 to change the logic level on the SCFIRST line and drive the GOSYNC output to FET 106 and the GONEG output to FET 110 to a logic high. Microprocessor 90 also asserts a logic level low on the POSI line, thereby turning on switch 72 and turning off switch 74. The operation of switches 72 and 74 couple output line 66 to input line 60 and output line 64 to input line 62, thus reversing the polarity of the output lines with respect to the input lines, and line 64 can go negative with respect to line 66, thereby producing an AC trapezoidal waveform from a DC input.

Next, microprocessor 90 performs the ramp up function discussed above with the exception that the reversal of the logic level on the SCFIRST line means that the output of the feed forward circuit 94 increases the time that switch 70 is turned on so that line 64 becomes increasingly negative with respect to line 66. When microprocessor 90 reaches its largest output voltage level to feed forward circuit 94, microprocessor 90 sets the crest timer again. At the expiration of the timer, microprocessor 90 releases the SYNC line so inverters 36 of the power supply 30 may resynchronize for the ramp down function. Provided all of the microprocessors release the SYNC line before the synchronization timer expires, the microprocessors of each inverter perform the ramp down function which increasingly reduces the time that switch 70 is turned on. This in turn makes output line 64 become less and less negative with respect to output line 66 until microprocessor 90 has output the zero reference voltage to the feed forward circuit 94 again. At that time, microprocessor 90 releases the GONEG output to FET 1 10 so all of the microprocessors may perform control actions to begin waveform ramp up at approximately the same time. By coordinating the output of the voltage waveforms through the SYNC, POS, and NEG lines, the inverters do not induce noise in the broadband signals caused by changing electromagnetic fields in proximity to where they are coupled to coaxial cables 24.

The system for providing this inventive switching control uses microprocessor 90 (of Fig. 4) and a feed fonvard circuit 94 (Fig. 5) to drive the switches that couple DC input power to the output lines of an inverter 36. As shown in Fig. 4, switches SA (72) and SB (74) control the polarity of the voltage output on lines 66 and 64. For example, during the positive portion of the output waveform, switch SB (74) is closed and switch SA (72) is opened to couple output line 64 to the negative potential of the DC power source. The microprocessor control of switches SC (68) and SD (70) control the positive potential of the DC power source to output line 64. During the negative voltage position of the waveform, switch SB (74) is opened and switch SA (72) is closed to couple the negative DC power potential to line 64. Microprocessor 90 controls switches SC (68) and SD (70), which in turn control the coupling of the negative potential of the DC power source to line 66 to change the voltage on line 66 with respect to the voltage on reference line 64.

In the preferred embodiment of the present invention, switches SA (72) and SB (74) are only controlled during the zero crossing portions of the waveform. That is, the status of switches SB (74) and SA (72) is only changed as the voltage of the output waveform approaches zero volts. Because switches SB (74) and SA (72) are changed only at the zero crossing point and switches SC (68) and SD (70) are not, switching losses are reduced from the prior art switching methods which change the state of all four switches during transitions of the output voltage waveform.

The advantages of the present invention are further enhanced by selectively controlling the status of the switches SC (68) and SD (70) to closely regulate the slew rate and crest voltage for the output waveform. Preferably, microprocessor 90 includes a program that cooperates with a feed forward circuit 94 to selectively control the SC (68) and SD (70) switches.

The feed fonvard circuit 94 is shown in Fig. 5. Feed forward circuit 94 includes a voltage to current converter 1 14, a FET 1 16, and a capacitor 118, all of which are coupled to the non-inverting input of a comparator 120. The inverting input of comparator 120 is coupled to the output of a digital-to-analog converter (DAC) 122. The DAC 122 receives its reference voltage input 126 from the output of DAC 124 and its digital voltage input from output line 128 of microprocessor 90. DAC 124 receives a reference voltage level from microprocessor 90 which it converts to an analog signal which is supplied to DAC 122. Changing the reference voltage level to DAC 124 causes the range for the output of DAC 122 to vary so the reference voltage level to the inverting input of comparator 120 may be varied without changing the output voltage level to DAC 122. The ^ output of latch 92 on line 123 (in Fig. 4) provides the signal to DAC 122 enabling it to receive digital values from microprocessor 90. The output of comparator 120 is coupled to XOR gates 96 and 98, and the AND gates 100 and 102, to drive the SC (68) and SD (70) switches.

Each inverter 36 in power supply 30 has a microprocessor 90 implementing the processes discussed below and a feed forward circuit 94 like the one shown in Fig. 5. In more detail, the input DC power on line 60 is input to voltage-to-current converter 1 14 of the feed forward circuit 94. The gate of FET 116 is driven by the clock that also drives

PWM latch 92. When FET 116 conducts, the current from converter 114 is grounded and when FET 116 is turned off, the current is differentiated by capacitor 1 18. Thus, these components produce a waveform that is a logic low for the first half of the clock period and which is a ramp to a voltage corresponding to the input voltage during the second half of the clock period. Microprocessor 90 through lines 128 to DAC 122 provides the output voltage level that corresponds to the output voltage to be supplied by inverter 36. During ramp up and ramp down that value is provided in synchronization with the change in the Q output of the PWM latch 92 on line 123 which enables DAC 122 for digital-to-analog conversion. The output of latch 92 occurs at the rising edge of the clock each clock period.

During the crest voltage output, microprocessor 90 computes the digital reference value to DAC 124 by comparing the voltage output on lines 64 and 66 by the inverter 36 to the preselected crest voltage that corresponds to the last output level provided to DAC 122. The inverter output voltage between 64 and 66 is converted to an AC signal that varies within the input range of internal A/D converters incorporated in microprocessor 90 by voltage level shifter 125. By reading the output of its internal A/D converters, microprocessor 90 determines the output voltage between lines 66 and 64, compares this value to the voltage level last output to DAC 122, and determines whether the inverter output voltage is within a predetermined range. If it is not, then microprocessor 90 uses the difference between the inverter and DAC voltages to adjust the reference voltage to DAC 124. For example, if the preselected crest output voltage is +90V and the actual output voltage is +88V, then microprocessor 90 increases the digital reference value input to DAC 124 by an amount which increases the analog signal output by DAC 124 which is used by DAC 122 as a reference voltage. The increase in the reference voltage for DAC 122 results in a corresponding increase in the output of the analog signal from DAC 122 which is output to comparator 120 as a reference signal. This, in turn, increases the time that switch SC is turned on to increase the output voltage.

Through lines 128 from an internally stored table during ramp up and ramp down microprocessor 90 provides the digital value input to DAC 122. The values in the table provide step increments from zero volts to a predetermined maximum voltage. The number of values corresponds to the number of steps required to achieve a preselected slew rate over a predetermined time interval. To ramp up the output waveform, the values are output to DAC 122, one per interval of time corresponding to the rise time divided by the number of values. In the preferred embodiment, forty-six values are output to DAC 122 with one value output each 16 microseconds. This corresponds to a slew rate of 736 microseconds. However, other slew rates, clock frequencies and numbers of samples may be used. For ramp down, the values are output in reverse order under the same timing constraint. Thus, the reference signal supplied by DAC 122 to comparator 120 increases during ramp up as the output voltage level to DAC 122 increases, may be changed during the crest voltage by altering the reference voltage level to DAC 124 to maintain the output voltage, and decreases during ramp down. The relationship between the reference signal on comparator 120 and the sawtooth waveform supplied to comparator 120 determines the output of comparator 120. Specifically, whether the signal from capacitor 118 is above or below the reference signal to comparator 120 determines whether comparator 120 produces a logic high or logic low value.

In more detail, when FET 1 16 is turned on during the first half of the clock period during a positive voltage ramp up, the signal to comparator 120 is below the first voltage output level provided to DAC 122 and the output of comparator 120 is a logic high. During the second half of the clock period when the signal ramps up, the signal rises above the level of the reference signal generated by DAC 122 and the output of comparator 120 goes low. The signal from comparator 120 is provided to XOR gates 96 and 98, which are also coupled to the SCFIRST signal. When SCFIRST line is a logic high during positive voltage ramp up, the output of XOR gate 96 is a logic high and the signal output from AND gate 100 is a logic high. Likewise, the output of XOR gate 98 is a logic low and the signal from AND gate 102 is a logic low. Thus, FET 68 is turned on and FET 70 is turned off for the first half of the clock period. When the output of comparator 120 changes state during the second half of the clock period, the outputs of gates 96 and 98 toggle, which toggle the outputs of gates 100 and 102 so that FET 68 is turned off and FET 70 is turned on. During positive ramp up this causes the output line 64 to follow input line 60. During positive ramp down, the operation of inverter 36 is the same except the output level values output to DAC 122 are decreasing during each clock cycle so FET 68 is turned on for increasingly shorter times.

When the output waveform is negative, the SCFIRST signal is brought low so that FET 70 is turned on for increasingly longer times during ramp up and increasingly shorter times during ramp down and vice versa for FET 68. Because the operation of FETs 72 and 74 is also reversed, as explained above, this causes output line 64 to become increasingly negative during ramp up and decreasingly negative during ramp down. Thus, the inverter of the present invention provides novel control of the switches 68, 70, 72, and 74, reducing switching losses and reliably controlling the waveform of the output voltage. Preferably, the stepwise values output to DAC 122 generate a linear slope so the resulting waveform is trapezoidal, although other waveform shapes may be possible.

The process for controlling the output waveform is shown in Figs. 6 through 10.

This control is primarily achieved through a main module that activates a ramp up module, a ramp down module and a crest module to regulate the output waveform. The ramp up and ramp down modules control the slew rate of the output waveform and the crest module controls the waveform crest output voltage.

Turning to Fig. 6, after initialization, the main module (shown in Fig. 6) enables interrupts (Step 150) and determines which module to execute. If waveform ramp up is needed (Step 152), then the ramp up module is executed (Step 158). If waveform ramp down is needed (Step 154), then the ramp down module is executed (Step 160). If the crest voltage has been reached (Step 156), the crest module is executed (Step 162) to maintain that voltage. If none of the conditions requires execution of a module, the main module resets a watch dog timer (Step 164) to indicate the inverter is still operational and the loop is repeated. The run crest module does not show a normal return to the main module as the preferred implementation uses stack manipulation to more -promptly terminate crest module processing, although other return processes may be used.

The ramp up subroutine is shown in Fig. 7. The ramp up module begins execution by disabling all interrupts (Step 170). A pointer is then set to the initial value of a voltage ramp up step table (Step 172). The process then executes a loop in which it clears pulse width modulation (PWM) latch 92 (Step 174), outputs a value from the voltage table to DAC 122 (Step 176), increments the table pointer (Step 178), and monitors the status of the pulse width modulation (PWM) latch until it is set by the rising edge of the clock (Step 184). When the latch is set, the microprocessor clears the latch (Step 174) and the output of latch 92 enables DAC 122 to receive a value from microprocessor 90. Microprocessor 90 then sends the next voltage value to the DAC 122 (Step 176) and increments the pointer (Step 178). The pulse width modulation latch is set by a clock having a frequency corresponding to the number of voltage values to be output over the rise time of the output waveform to achieve the predetermined slew rate, which in the preferred embodiment is 62.5 kHz. When the end of the voltage output table is reached (Step 180), the crest flag is set (Step 182) to indicate the crest module should execute and the ramp up module returns to the main module.

The ramp down module (Fig. 8) executes in much the same manner as the ramp up module, except in reverse. After disabling interrupts (Step 190), the module pulls the synchronization line (GOSYNC) to a logic low level (Step 192) which indicates to the power supply controller 46 that the output voltage is changing from the crest level. The module then sets a pointer to the end of the ramp up voltage step table (Step 194) and begins a loop in which the PWM latch is cleared (Step 196), the voltage value from the voltage output table is output to DAC 122 (Step 200) and the pointer is decremented (Step 202). The PWM latch is monitored (Step 206) to synchronize the output of the voltage values as explained above. Once the start of the table is reached (Step 204), the module releases the positive polarity POS and negative polarity NEG lines (Step 108) to indicate the output waveform is approaching zero and initiates a zero crossing timer (Step 210). Interrupts are then enabled (Step 212). During the period that the zero crossing timer is running, the microprocessor 90 should detect that the other microprocessors are ready to drive their respective outputs negative by receiving an interrupt when the POS and NEG lines go to a logic high. If it does not, the zero crossing timer generates an interrupt.

In response to an interrupt generated by the zero crossing timer expiring, microprocessor 90 clears a polarity status bit in a status word communicated to controller 46 and sets a flag to indicate the ramp up module is to be executed. Because the SA (72) and SB (74) switches are not switched, the inverter continues to output a waveform in the same polarity as the last waveform produced. Microprocessor 90 does this to continue the output of voltage waveforms even though the output waveform did not go through the zero voltage. Thus, the inverter continues to perform the ramp up, ramp down, and crest modules but the waveform does not switch polarities. That is, the inverter outputs only positive or only negative voltage waveforms thereafter. Although this is not the preferred mode of operation for the inverter, the inverter does continue to output some voltage which may be used to operate a device. Alternatively, the power supply controller 46, in response to the cleared polarity status bit, may terminate operation of the defective inverter 36 and switch-in redundant inverter 36R, if available.

Upon receiving an interrupt when the POS and NEG lines go positive, microprocessor 90 executes a zero crossing interrupt module which is shown in FIG. 9. In executing that module, microprocessor 90 clears the zero crossing timer (Step 220) since all the microprocessors are ready to change output voltage polarity. The microprocessor 90 toggles an SCFIRST bit to XOR gates 96 and 98, and a POSI line to switches 72 and 74. (Step 222). The POSI output reverses the status of switches SB (74) and SA (72) which changes the reference potential supplied to line 64. Changing the SCFIRST bit causes switches SD (70) and SC (68) to be operated in a manner discussed in more detail below. The process then disables all switches in the switching network by driving the ALLOFF line low (Step 224). The polarity lines (POS, NEG) on the system bus are then set to indicate the polarity of the next portion of the waveform (Step 226) and the zero crossing interrupt latch is cleared (Step 228). The switches in the switching network are then enabled by driving ALLOFF high (Step 230) and the ramp up flag is set (Step 240).

The above-described operation means that the first microprocessor to reach zero volts and release the polarity lines must wait for the other inverters to do likewise before it begins- to drive the output voltage to the next polarity. This may cause a "knee" in the output voltage waveform as is shown in FIG. 3B. However, because the inverters begin ramp down substantially simultaneously, this period is relatively short. To further ensure that this knee is short, program control preferably is directly transferred to the ramp up module rather than returning to the main module through typical return instruction processing (Step 242). This avoids further delay in driving the next portion of the output waveform, although control may be returned to the main module if such timing in the output waveform is not important.

The crest module is shown in FIG. 10. That process begins by microprocessor 90 putting the SYNC line to a logic low level (Step 250) to indicate the crest voltage has been reached. The module then sets a synchronization timer (Step 252) which corresponds to the length of time the crest voltage is to be maintained for the output waveform. Interrupts are then enabled (Step 254) and the communications interface with the power supply controller 46 is also enabled (Step 256). The crest module then scans its internal analog to digital converter channels (Step 258), to verify that the DC input voltage (Step 260), the battery backup voltage (Step 262), the temperature of the transformer, and the ambient air (Step 264) surrounding the inverter 36 are within operating parameters. If either voltage is below a threshold or either temperature exceeds a predetermined threshold, a shutdown module is executed (Step 266) to terminate operation of the inverter 36. If all operating parameters are within limits, processing continues by verifying that the output voltage is within operating parameters. The A/D channel voltage that corresponds to the output voltage is compared to an upper threshold (Step 268) and a lower threshold (Step 270). If the output voltage is outside these values, then the difference between the threshold and output voltage is computed. If the upper limit is violated, the difference is subtracted from the digital reference value output to DAC 124 and the updated value is output to DAC 124 (Step 272). If the output voltage is less than the lower limit, the difference is added to the digital reference value and output to DAC 124 (Step 274). Following verification of the output voltage, the polarity of the output wave is set (Step 276) and the watchdog timer reset (Step 278) to indicate the process is still active. Status bits in the inverter status word are then updated (Step 280) and the module continues to monitor the status of the inverter 36 until the synchronization line is released.

As described above, the preferred embodiment of the power supply includes a plurality of inverters 36, each of which outputs a voltage waveform. Preferably, the waveforms output by each inverter 36 are synchronized so the ramp up, ramp down, and crest functions all occur at substantially the same time. Otherwise, the fluctuating fields produced by asynchronous waveforms induce noise in the output of the neighboring inverters. To avoid this noise, each microprocessor 90 in the inverters 36 is coupled to the synchronization line. Each microprocessor releases the synchronization line at the end of the crest module execution and then monitors the line. The microprocessors detect a logic level shift in the synchronization line when the last microprocessor has released the line. At that time, all of the inverters may initiate the next ramp function to be performed and the resulting waveform from each of the inverters is thus synchronized with the others.

A circuit 300 for regulating current overshoot on the output current is shown in Fig. 11. Circuit 300 includes current sensor 302, a bipolar comparator 304 comprised of operational amplifiers 306, 308, and 310, and a DAC 312. Microprocessor 90 controls DAC 312 to supply a reference signal to amplifiers 306 and 310 which are configured as comparators. Current sensor 302 monitors the output line 66 and generates a signal corresponding to the current of the output power. It is well known that as an output voltage waveform reaches a crest voltage (either negative or positive), the output current may overshoot. To limit current overshoot, circuit 300 controls switches SA (68) and SB (70). This control is regulated by microprocessor 90 which supplies a reference signal to the non-inverting input of amplifier 306 and to the inverting input of amplifier 310 through amplifier 308. Amplifier 308 operates as an inverter to produce a negative reference signal. If the signal from sensor 302 is positive and greater than the reference signal to amplifier 306, the output of amplifier 306 changes state. If the signal from sensor 302 is negative and greater, i.e., greater negative value, than the negative reference signal supplied to amplifier 310, the state of the output for amplifier 310 changes. A change in the state of the output of either amplifier 306 or 310 disables switches SC (68) and SD (70) to disrupt the connection between input and output power, thereby reducing the voltage of the output waveform and clipping the current overshoot. Although this alters the slew rate and output voltage slightly, the change is minimal and tolerated in the typical applications.

By substantially reducing the current overshoot, the power supply of the present invention reduces current hum modulation in broadband signal distribution systems such as CATV systems. In those types of systems, a tap is provided for each junction at a consumer site. Such a tap 320 is schematically shown in Fig. 12. As shown in that figure, an inductor 322, appropriately valued to be an RF choke, couples power from feeder line 24 around the broadband signal tap point. Broadband signals are tapped through capacitors 328, 330, transformer 332 and circuit network 324. Specifically, transformers 332 and 336 tap the broadband signals to the tap point 326.

The electrical power provided on feeder 24 may be tapped to power an NIU or other device at a subscriber site through inductor 342 which is very large relative to inductor 322. This relative sizing of inductors 322 and 342 provides a divider network that taps a portion of the electrical power from feeder line 24. This power may be coupled to the central conductor of a coaxial cable to the subscriber site along with the broadband signals from tap point 326. Alternatively, the broadband signals may be coupled to a twisted pair of wires which are wrapped around the sheath between the central conductor for a coaxial cable and the ground shield. When the overshoot current condition occurs, the increased current reduces the inductance of inductor 322 , consequently, the electric power frequency components may induce noise into the broadband signal tap point 326. By reducing current overshoot at the power supply, there is less likelihood that current levels are reached which lower the inductance of the inductor 322 to a level that induces current hum modulation in the broadband signals tapped from the cable.

The above discussion has disclosed a novel power supply and method for controlling the switches of a switching power supply to generate a slowly varying AC trapezoidal waveform. Such a power supply may be used to construct a broadband signal transmission system that efficiently powers amplifiers and network interface units to render the system capable of being interfaced with fiber optic cables and cable-ready televisions.

While the invention has been described in connection with a preferred embodiment, it is not intended to limit the scope of the invention to the particular form set forth, but, on the contrary, it is intended to cover such alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.

Claims

CLAIMSI claim:

1. An inverter for a power supply that provides power to be distributed through a broadband signal distribution system, said inverter comprising: a switching network for converting input DC power to output AC power; and a regulator for controlling said switching network so that said output AC power is a slowly varying AC waveform that can be coupled with broadband signals and transmitted through a coaxial cable for distribution in the broadband signal distribution system.

2. The inverter of claim 1 , wherein said regulator further comprises: a feed forward circuit for generating a signal to control said slowly varying output AC waveform from said switching network; and a processor for controlling said feed forward circuit, wherein said processor provides a digital voltage value to said feed forward circuit to control said signal generated by said feed forward circuit.

3. The inverter of claim 2, wherein said digital voltage value from said processor comprises an output voltage value and a reference voltage value.

4. The inverter of claim 2, wherein said feed forward circuit further comprises a comparator for comparing a signal corresponding to an input voltage of said input DC power, to a first reference signal corresponding to said digital voltage value, and for generating said generated signal for driving said switching network.

5. The inverter of claim 4, said feed forward circuit further comprising: a first digital-to-analog converter for converting a reference voltage value from said processor to generate an analog reference signal; a second digital-to-analog converter for receiving said analog reference signal from said first digital-to-analog converter, and for receiving a digital output voltage value from said processor, wherein said second digital-to-analog converter generates said first reference signal for said comparator; and a voltage-to-current converter for receiving and converting -an input voltage value into said generated input voltage signal and for supplying said input voltage signal to said comparator.

6. The inverter of claim 5 wherein said processor provides said digital output voltage value to said first digital-to-analog converter from a table of output voltage values, and wherein said processor outputs each said digital output voltage value to said feed fonvard circuit in synchronization with a signal enabling said second digital-to- analog converter.

7. The inverter of claim 6 wherein said enabling signal is a periodic signal for causing an output voltage level for said power supply to be trapezoidal.

8. The inverter of claim 2, wherein said switching network comprises four controllable switches, a first pair of said switches for controlling a polarity for said slowly varying AC waveform and a second pair of said switches for controlling a voltage level for said slowly varying AC waveform; and wherein said generated signal from said feed fonvard circuit drives said second pair of switches controlling said voltage level by selectively opening and closing one each of said second pair of switches according to the polarity of said output AC waveform.

9. The inverter of claim 8, wherein said processor controls said first pair of switches controlling said polarity so that said polarity is switched at a zero voltage crossing of said slowly varying AC waveform.

10. The inverter of claim 1 further comprising: a current sensor for generating a current signal indicative of a current magnitude of said output AC power; and an overshoot circuit coupled to said current sensor, said overshoot circuit for comparing said current signal to a current limit and for generating an overshoot signal to control said switching network by decoupling said input DC from said output AC if said current signal is greater than said current limit.

11. The inverter of claim 10 further comprising: a processor for providing said current limit to said overshoot circuit to allow said current limit to be varied.

12. A power supply comprising: a plurality of inverters comprising a switching network for converting input DC power to output AC power; and a regulator for controlling said switching network so that said output AC power is a slowly varying AC waveform that can be coupled with broadband signals and transmitted through a coaxial cable for distribution in the broadband signal distribution system, said regulator comprising a feed forward circuit for generating a signal to control said slowly varying output AC waveform from said switching network, and a processor for controlling said feed forward circuit, wherein said processor provides a digital voltage value to said feed fonvard circuit to control said signal generated by said feed fonvard circuit; wherein each of said regulators in said inverters is coupled to a synchronization line so that said slowly varying output AC waveforms of each said inverter are synchronized within a predetermined number of clock periods of said synchronization line.

13. The power supply of claim 12 wherein said processor of each said regulator is coupled to said synchronization line so that the last processor releasing said synchronization line triggers said processors in said regulators to begin changing in said output voltage level of said power supply.

14. A power supply for supplying power to a plurality of feeder lines in a broadband signal distribution system, the feeder lines each connected to a plurality of coaxial cables for transmission of power and the broadband signal, said power supply comprising: a plurality of inverters for converting input DC power to output AC power, said output AC power having a slowly varying AC waveform; and, a synchronization line coupling said plurality of inverters for synchronization of the start of a transition of said output AC waveform in said plurality of inverters to reduce switching induced noise in the broadband signal transmitted by the coaxial cables.

15. The power supply of claim 14, wherein said output AC waveform comprises a trapezoidal waveform having a ramp up, a ramp down, and a crest portion and wherein said inverters signal a start of said ramp down portion by logically releasing said synchronization line.

16. The power supply of claim 15 further comprising: a switching network; a negative polarity line to which said plurality of inverters are coupled, and wherein said inverters signal a negative ramp up portion for said output AC waveform through said negative polarity line; a positive polarity line to which said plurality of inverters are coupled, and wherein said inverters signal a positive ramp up portion for said output AC waveform through said positive polarity line; wherein said inverters signal through said synchronization line a ramp down transition; and wherein said inverters signal through said negative and positive polarity lines a ramp up transition to synchronize said trapezoidal waveforms by controlling said switching network in response to the last inverter releasing said synchronization, positive polarity, and negative polarity lines.

17. The inverter of claim 1 wherein said slowly varying AC waveform has a frequency within the range of 1Hz to 60Hz.

18. The inverter of claim 2 wherein said slowly varying AC waveform has a frequency within the range of 1Hz to 60Hz.

19. The power supply of claim 14 wherein said slowly varying AC waveform has a frequency within the range of 1 Hz to 60 Hz.

20. The inverter of claim 1 wherein said slowly varying AC waveform has a frequency within the range of 1Hz to 10Hz.

21. The inverter of claim 2 wherein said slowly varying AC waveform has a frequency within the range of 1Hz to 10Hz.

22. The power supply of claim 14 wherein said slowly varying AC waveform has a frequency within the range of 1Hz to 10Hz.