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WO1998042009A1 - Process for producing semiconductor integrated circuit device - Google Patents

Process for producing semiconductor integrated circuit device Download PDF

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Publication number
WO1998042009A1
WO1998042009A1 PCT/JP1997/000810 JP9700810W WO9842009A1 WO 1998042009 A1 WO1998042009 A1 WO 1998042009A1 JP 9700810 W JP9700810 W JP 9700810W WO 9842009 A1 WO9842009 A1 WO 9842009A1
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WO
WIPO (PCT)
Prior art keywords
integrated circuit
circuit device
manufacturing
semiconductor integrated
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP1997/000810
Other languages
French (fr)
Japanese (ja)
Inventor
Shinji Nishihara
Shuji Ikeda
Naotaka Hashimoto
Hiroshi Momiji
Hiromi Abe
Shinichi Fukada
Masayuki Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to AU19405/97A priority Critical patent/AU1940597A/en
Priority to PCT/JP1997/000810 priority patent/WO1998042009A1/en
Priority to US09/380,735 priority patent/US6693001B2/en
Priority to CNB971820252A priority patent/CN1146959C/en
Priority to KR1019997008290A priority patent/KR100563503B1/en
Priority to KR10-2004-7007841A priority patent/KR20040053359A/en
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority claimed from CNB971820252A external-priority patent/CN1146959C/en
Publication of WO1998042009A1 publication Critical patent/WO1998042009A1/en
Anticipated expiration legal-status Critical
Priority to US11/006,702 priority patent/US7214577B2/en
Priority to US11/783,187 priority patent/US7314830B2/en
Priority to US11/950,152 priority patent/US7553766B2/en
Priority to US12/492,276 priority patent/US8034715B2/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a manufacturing technology of a semiconductor integrated circuit device, and particularly to a technology effective when applied to a salicide (Salicide; self-aligned silicide) process using a Co (cobalt) film formed by a sputtering method. It is about. Background art
  • refractory metal (silicide) films for electrodes and wiring are formed on a semiconductor wafer by sputtering a target made by sintering a refractory metal (silicide) powder in argon. You.
  • Japanese Unexamined Patent Publications Nos. 6-192,974, 6-192,799 and 7-34886 describe impurities, particularly Ni (nickel) and Fe ( It discloses a technique for producing high-purity Co with a purity of 99.999% (5N) or more by reducing the content of iron) by electrolytic refining. These high-purity Cos are applied to the production of Co targets for forming Co films used for electrodes and wiring (electrodes, gates, wiring, elements, protective films) of semiconductor devices. You.
  • Japanese Patent Application Laid-Open No. Hei 5-137700 discloses a method of manufacturing a high melting point metal silicide target for sputtering that can suppress generation of particles that cause disconnection or short circuit of electrodes and wiring.
  • the high melting point metal include W, Mo (molybdenum), Ta (tantalum), Ti, Co, and Cr (chromium).
  • the refractory metal silicide film can be formed by using the refractory metal silicide target as described above or by reacting the refractory metal film with silicon.
  • Japanese Patent Application Laid-Open No. 7-321069 uses a composite metal target composed of 20 atom% of a ferromagnetic material such as Co and 80 atom% of a paramagnetic material such as Ti.
  • a magnetron 'sputtering method formed a Co-Ti film on the entire surface of the semiconductor substrate on which the metal oxide semiconductor field effect transistor (MFETSFET) was formed.
  • MFETSFET metal oxide semiconductor field effect transistor
  • the present inventors have studied the introduction of a salicide process for forming a low-resistance high-melting-point metal silicide layer on a polycrystalline silicon gate and on a source and a drain as a measure for increasing the speed of a MOS FET.
  • the high melting point metal material Co was selected, which can provide a low resistance silicide of about 15 ⁇ cm.
  • the threshold voltage As a countermeasure, a dual gate in which the gate electrode of a p-channel MOSFET is made of p-type polycrystalline silicon to be a surface channel type, and the gate electrode of an n-channel MOSFET is made of n-type polycrystalline silicon and is a surface channel type The introduction of a CMOS structure was considered.
  • the above-mentioned salicide method for forming a silicide layer on a polycrystalline silicon gate is problematic in the connection method between the p-type polycrystalline silicon gate and the n-type polycrystalline silicon gate. This problem can be solved by combining this with a process.
  • the process for forming the Co silicide layer on the polycrystalline silicon gate and the source and drain of the MOS FET is as follows.
  • a Co film is deposited on a semiconductor substrate on which a MOS FET is formed by a sputtering method using a Co target. Then, heat treatment allows Co and Si to react with each other. A Co silicide layer is formed on the surface (first heat treatment).
  • the Co silicide obtained at this time is monosilicide (CoSi) having a relatively high resistance of 50 to 60 ⁇ cm.
  • the substrate is again heat-treated to cause the monosilicide to undergo a phase transition to low-resistance disilicide (CoSi 2 ) (second heat treatment).
  • the present inventor performed the first heat treatment on the Co film formed using a 99.9% pure Co target, and found that the obtained Co monosilicide (Co Si) layer
  • the film thickness was highly dependent on the temperature change of the heat treatment. Specifically, a phenomenon was observed in which the higher the heat treatment temperature, the thicker the film thickness, and the lower the heat treatment temperature, the thinner the film thickness, and it was difficult to control the film thickness stably. It is considered that such a variation in the film thickness is mainly caused by silicidation of some of the impurity transition metals such as Fe and Ni contained in the Co target.
  • the thickness of the monosilicide layer is reduced by setting the first heat treatment temperature lower to avoid an increase in junction leakage current, the resistance of the silicide layer increases. Further, when the heat treatment temperature is low, the progress of the silicidation reaction is slowed, so that the resistance of the side layer is further increased. Furthermore, as the thickness of the Co silicide layer becomes thinner, its heat resistance decreases. Therefore, a heat treatment step after OS FET formation (for example, P (phosphorus) for gettering a metal such as Na (sodium)). A process of depositing a doped silicon oxide film on top of the MOS FET and then crystallizing the silicon oxide film at a high temperature) causes the co-silicide crystal grains to aggregate (agglomeration), resulting in abnormal resistance. It may increase.
  • OS FET formation for example, P (phosphorus) for gettering a metal such as Na (sodium
  • a method for manufacturing a semiconductor integrated circuit device includes the following steps (a) to (d).
  • the method of manufacturing a semiconductor integrated circuit device when forming a CoSi 2 layer on the surface of silicon by the reaction of Co and Si, has at least a small first heat treatment temperature dependency and a film thickness.
  • the sheet resistance of the Co Si 2 layer should be 10 ⁇ / port or less. It is.
  • the high-purity Co target used in the present invention has a Co purity of at least 99.99% and a Fe or Ni content of 10 ppm or less, or a Fe and Ni content of 50 ppm or less. It is. More preferably, the purity of Co is 99.99% or more, and the content of Fe and Ni is 10 ppm or less. Use with a purity of 99.999%.
  • the term “wafer” refers to a single or multiple single-crystal regions (here, mainly silicon) after at least a certain step of manufacturing a semiconductor integrated circuit device mainly in a surface region thereof. )
  • the “semiconductor integrated circuit device” includes not only a device formed on a normal single crystal wafer but also a device formed on another substrate such as a TFT liquid crystal.
  • a method for manufacturing a semiconductor integrated circuit device includes the following steps:
  • the Co target has a Co purity of 99.99% or more and a Fe or Ni content of 10 ppm or less.
  • the Co purity power S of the Co target is 99.99% or more, and the contents of Fe and Ni are 50 ppm or less.
  • the Co target has a Co purity of 99.99% or more and Fe and Ni contents of 10 ppm or less.
  • the Co target has a Co purity of 99.999%.
  • the temperature of the first heat treatment is 475 : C to 525 ° C.
  • the temperature of the second heat treatment is 650 ° C. to 800 ° C. C.
  • the Co film has a thickness of 18 to 60 bodies.
  • a sheet resistance of the Co silicide layer after performing the second heat treatment is 10 ⁇ / port or less.
  • a junction depth of the source and the drain is 0.3 ⁇ m or less.
  • a method of manufacturing a semiconductor integrated circuit device of the present invention includes the following steps;
  • the operating power supply voltage of the MOSFET is 2 V or less.
  • the Co target has a Co purity of 99.99% or more and a Fe or Ni content of 10 ppm or less.
  • the Co target has a Co purity of 99.99% or more, and a content of Fe and Ni is 50 ppm or less.
  • the Co target has a Co purity of 99.99% or more, and a content of Fe and Ni is 10 ppra or less.
  • the Co target has a Co purity of 99.999%.
  • the method for manufacturing a semiconductor integrated circuit device of the present invention includes the following steps:
  • the silicon oxide film doped with the impurity is a PSG film.
  • the temperature of the third heat treatment is 700 ° C to 800 ° C.
  • An object of the present invention is to provide a salicide process capable of forming a Co silicide layer having low resistance and low junction leakage current.
  • FIG. 9 to FIG. 12 are cross-sectional views of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
  • 8 is a graph showing the relationship between the heat treatment at 750 eC for 30 minutes for activating the impurity and the leakage current of the source and drain formed by this impurity
  • Fig. 10 is the sputtering used for depositing the Co film.
  • Schematic diagram of the chamber of the device Fig. 11 is a perspective view of the Co target
  • Fig. 14 is an n-channel MOS FET and p-channel type with Co silicide layers formed on the gate electrode, source and drain surfaces.
  • Enlarged view of MOS FET Figure 15 shows sheet resistance of Co silicide layer and first heat treatment temperature 6 is a graph showing a relationship with the graph.
  • This embodiment is applied to a dual-gate CMOS process in which the design rule is 0.25 ⁇ m and the operating power supply voltage is 2 V, but the present invention is limited by this embodiment. Of course, it is not.
  • a CMO SFET with a dual-gate structure To form a CMO SFET with a dual-gate structure, first, as shown in Fig. 1, the surface of a semiconductor substrate 1 made of p-type single-crystal silicon having a specific resistance of about 10 ⁇ era is thermally oxidized to form a film. After the silicon oxide film 2 on the thigh is formed, a silicon nitride film 3 having a thickness of 100 nm is deposited on the silicon oxide film 2 by a CVD method. Next, the silicon nitride film 3 is patterned by dry etching using a photoresist as a mask to remove the silicon nitride film 3 in the element isolation region.
  • the surface thereof is flattened by the CMP method, and the silicon oxide film 5 is The element isolation groove 4 is formed by leaving the trench.
  • a heat treatment of 100 Ot: is performed to densify the silicon oxide film 5 inside the element isolation trench 4, and then the silicon nitride film 3 is removed by wet etching using hot phosphoric acid.
  • an n-type well 6 n and a p-type well 6 p are formed on the semiconductor substrate 1.
  • an impurity for forming an n-type well is ion-implanted into the semiconductor substrate 1 using a photoresist in which a region for forming a p-channel type MOSFET is opened as a mask.
  • an impurity for adjusting the value voltage is ion-implanted.
  • an impurity for forming an n-type well for example, P (phosphorus) is used, and ion implantation is performed at an energy of 360 keV and a dose of 1.5 ⁇ 10 13 / cm 2 .
  • the impurity for adjusting the threshold voltage for example, P is used, and ions are implanted at an energy of 40: keV and a dose of 2 ⁇ 10 I2 / cm 2 .
  • an impurity for forming a p-type well in the semiconductor substrate 1 is ion-implanted in the semiconductor substrate 1 using the photoresist in which an n-channel M ⁇ SFET formation region is opened as a mask.
  • an impurity for adjusting the threshold voltage of the n-channel MOSFET is ion-implanted.
  • impurity for adjusting the threshold voltage for example, boron fluoride (BF 2 ) is used, and ion implantation is performed at an energy of 40 keV and a dose of 2 ⁇ 10 / c ni 2 .
  • the semiconductor substrate 1 is heat-treated at 950 for 1 minute to activate the impurities, thereby forming the n-type well 6n and the p-type well 6p.
  • the semiconductor substrate 1 was thermally oxidized to form a 4 nm-thick gate oxide film 7 on the surface of each of the active regions of the n-type well 6 n and the p-type well 6 p. Thereafter, a 250-nm-thick polycrystalline silicon film 8 is deposited on the semiconductor substrate 1 by the CVD method, and a silicon oxide film 9 is deposited on the polycrystalline silicon film 8 by the CVD method. Neither n-type impurities nor p-type impurities are doped into this polycrystalline silicon film 8.
  • the gate electrode of the n-channel MOSFET is formed on the p-type well 6 p.
  • 8 n is formed, and a gate electrode 8 p of p-channel type MOSFET is formed on the n-type well.
  • the gate electrode 8 n and the gate electrode 8 p are formed with a gout length of 0.25 ⁇ m.
  • the photoresist and the gate electrode 8 n are used as masks, and the p-type well 6 p has an energy of 20 keV, a dose of 3.0 X 10 "/ cm 2 and an n-type impurity (arsenic (A
  • the semiconductor substrate 1 is heat-treated at 100 ° C.
  • n-type well 6 n on both sides of the gate electrode 8 p is p-doped.
  • -Type semiconductor region 10 is formed, on both sides of gate electrode 8 n
  • An n-type semiconductor region 11 is formed in the p-type well 6 p of the semiconductor device.
  • a side wall spacer 12 having a thickness in the gate length direction of 0.1 / m is formed on the side walls of the gate electrodes 8 n and 8 p.
  • the sidewall spacers 12 are formed by anisotropically etching a silicon oxide film deposited on the semiconductor substrate 1 by a CVD method by a reactive ion etching method. When this etching is performed, the silicon oxide film 9 above the gate electrodes 8n and 8p is also etched to expose the surfaces of the gate electrodes 8n and 8p.
  • p-type impurities (B) are ion-implanted into the n-type well 6 n and the gate electrode 7 at an energy of 20 keV and a dose of 1.0 ⁇ 10 ′′ / cm 2.
  • p-type impurity (B) energy 5 ke V, a dose -. 2.
  • the semiconductor substrate By activity the 1 000 ° C, 1 0 seconds heat treatment to the impurities, Gate electrode to form a p f-type semiconductor region 1 3 to n-type Ueru 6 n 8 Change the conductivity type of p to p-type. Also, an n + -type semiconductor region 14 is formed in the p-type well 6 p and the conductivity type of the gate electrode 8 n is made n-type.
  • the p ⁇ type semiconductor region 13 and the n + type semiconductor region 14 are formed at a junction depth of 2 to 0.1 ⁇ m, respectively.
  • the semiconductor substrate 1 Prior to the heat treatment (1000, 10 seconds), the semiconductor substrate 1 is heat-treated at 750 ° C. for 30 minutes to reduce the ( ⁇ ⁇ / ⁇ ) junction leakage of the n + type semiconductor region 14 as shown in FIG. It can be reduced. This is because the point defect introduced into the semiconductor substrate 1 at the time of ion implantation is recovered by this heat treatment.
  • first heat treatment for 750 30 minutes is performed immediately after ion implantation for forming the type semiconductor region 14, and then ion implantation for forming the ⁇ ′-type semiconductor region 13.
  • a 15 nm-thick Co film 16 is deposited on the semiconductor substrate 1 by sputtering using a Co target, and a 10- to 15-nm-thick oxidation prevention film is formed on the Co film 16.
  • Film 17 is deposited.
  • the antioxidant film 17 uses, for example, TiNs deposited by a sputtering method. Same.
  • the thickness of the film 16 is preferably in the range of 18 to 60 employment. When the film thickness is less than 18 nm, it is difficult to reduce the sheet resistance of the Co silicide layer to] .0 ⁇ / port or less, and when the film thickness is more than 60 plates, the source and drain junction leakage currents increase.
  • FIG. 10 is a schematic view of a chamber of a sputtering apparatus used for depositing the Co film 16.
  • the inside of the chamber 100 is evacuated to a vacuum. During film formation, Ar gas is introduced and the pressure is maintained at about several mTorr.
  • a Co target 1.03 held by a sputter electrode 102 is arranged to face the semiconductor substrate 1.
  • the sputter power supply 104 connected to the Co target 103 is activated to start a steady discharge, the negative high voltage applied to the Co target 103 causes the C Plasma 105 is formed in the gap between 3 and semiconductor substrate 1.
  • FIG. 11 is a perspective view of the C 0 target 103.
  • the Co target 103 used in the present embodiment has a Co purity of at least 99.9% or more and a Fe or Ni content of] .0 ppm or less, or Fe and Ni. Ni content is 50 ppm or less. More preferably, those having a Co purity of 99.9% or more and Fe and Ni contents of 10 ppm or less, more preferably those having a Co purity of 99.999%. use.
  • Such a high-purity Co target 103 is prepared by sintering the raw material Co powder, which has been refined by using an electrolysis method or the like until the above-mentioned Co purity is obtained, by hot pressing, for example, into a disk shape. Manufactured by mechanical processing.
  • a first heat treatment for reacting Co with Si is performed.
  • a CoSi layer 16a is formed on each surface of the p + type semiconductor region 13, the n + type semiconductor region 14, and the gate electrodes 8n, 8P.
  • the first heat treatment is performed for about 30 seconds in a nitrogen atmosphere at a substrate temperature of 525: C or lower using a rapid thermal annealing (RTA) apparatus.
  • RTA rapid thermal annealing
  • the substrate temperature is preferably set to at least 475 or more.
  • FIG. 13 by performing the second heat treatment, the CoSi layer 16 a undergoes a phase transition to the CoSi 2 layer 16 b.
  • the second heat treatment is performed in a nitrogen atmosphere at a substrate temperature of 650 to 800 C for about 0.1 minute using an RTA apparatus.
  • C o S i 2 layer 16 n channel-type was formed b MOSFET and enlarged view of a p-channel type MOSFET to the respective surfaces of the source and drain, 1 5
  • C o S i 2 layers 16 is a graph showing the relationship between the sheet resistance of 16b and the first heat treatment temperature.
  • a high-purity product (target B) having a Co purity of 99.998% and a low-purity product (target A) having a 99.9% purity were used as the Co target.
  • Table 1 shows the impurity species and their contents in Targets 8 and B. Table 1 (Unit: Weight pm
  • the CoSi; layer 16b obtained from the high-purity target B having a purity of 99.998% has a small first heat treatment temperature dependence of the CoSi layer 16a, Since the temperature becomes almost uniform in this temperature range, a low sheet resistance of about 4 ⁇ / port was obtained throughout this temperature range.
  • the heat treatment temperature when the heat treatment temperature was low, the sheet resistance of the CoSi 2 layer obtained from the target A having a purity of 99.9% was significantly increased because the thickness of the Co film was small. Further, in order to obtain the same sheet resistance as the CoSi 2 layer obtained from the high-purity target B, the first heat treatment temperature had to be increased to 60 O'C.
  • the purity of the Co is 99.9.
  • the content of Fe and Ni is 9% or more. Since a Co silicide layer 16b with low junction leakage current can be obtained with a resistor, high-speed, high-performance, and low-power consumption devices using a fine CMO SFET with a gate length of 0.25 ⁇ m can be obtained. Can be promoted.
  • a 100-nm-thick silicon oxide film 18 is deposited on the semiconductor substrate 1 by a normal pressure CVD method, and then a thickness of 300 to 50 nm is formed by a plasma CVD method.
  • a 0-nm silicon oxide film 19 is deposited, the silicon oxide film] .9 is polished by a chemical mechanical polishing (CMP) method to flatten the surface.
  • CMP chemical mechanical polishing
  • the water in the PSG film 20 is removed.
  • Heat treatment (sintering) is performed in the temperature range of 700 to 800 ° C.
  • the film thickness of the CoSi 2 layer 16b can be sufficiently ensured, the aggregation of the CoSi 2 layer 16b is suppressed even when high-temperature sintering is performed. Therefore, it is possible to prevent an increase in the sheet resistance of the Co Si 2 layer 16 b, and Process margin can be improved.
  • FIG. 1 As shown in 7, PSG film 2 0 by a photo registry to mask, oxidation silicon film 1 9, by etching the .1 8, p ⁇ type semiconductor region 1 3 and After forming a connection hole 21 on each of the type semiconductor regions 14, a first layer wiring 22 is formed on the PSG film 20.
  • a thin first TiN film is deposited on top of the PSG film 20 by CVD, a thick W film is deposited on top of it, and the W film is etched back. And leave it inside the connection hole 2 1.
  • the second TN film, the A1 film and the second film are formed using a photoresist as a mask.
  • a first interlayer insulating film 23 is formed on the first layer wiring 22 and the surface thereof is planarized by a chemical mechanical polishing method.
  • a connection hole 24 is formed in the film 23.
  • a second-layer wiring 25 is formed on the first interlayer insulating film 23, so that the second-layer wiring 25 and the first-layer wiring 22 are electrically connected.
  • the first interlayer insulating film 23 is made of a silicon oxide film deposited by a plasma CVD method, and the second layer wiring 25 is made of the same material as the first layer wiring 22.
  • a second inter-layer insulating film 26 is formed on the second layer wiring 25 in the same manner as described above, and the surface flatness and the connection holes 27 are formed. After that, a third-layer wiring 28 is formed on the second interlayer insulating film 26.
  • a third interlayer insulating film 29 is formed on the third layer wiring 25, and after the surface is flattened and the connection holes 30 are formed, the third interlayer insulating film 29 is formed.
  • a fourth-layer wiring 31 is formed on the film 29, and a fourth interlayer insulating film 32 is formed on the fourth-layer wiring 31. The surface is flattened and the connection hole 33 is formed.
  • the fifth layer wiring 34 is formed on the fourth interlayer insulating film 32, whereby the semiconductor integrated circuit device of the present embodiment is almost completed.
  • the manufacturing method of the present invention using a high-purity Co target is, for example, an M ⁇ SFET. It can be applied to the case where only the source and drain surfaces are to be silicified with Co. Industrial applicability
  • the controllability of the thickness of the Co silicide layer is improved, and a Co silicide layer having low resistance and low junction leakage current is obtained. Therefore, it is suitable to be applied to a salicide process using a Co target.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
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Abstract

A Co film is deposited on a major surface of a wafer by a sputtering method which employs a high purity Co target which has a Co purity of not less that 99.99 %, preferably 99.999 %, and Fe and Ni contents not larger than 10 ppm. The deposited Co film is turned to a Co silicide film which is in ohmic contact with the gate electrode, source and drain of a MOSFET with low resistances and causes little leak current.

Description

明 細 書 半導体集積回路装置の製造方法 技術分野  Description Method of manufacturing semiconductor integrated circuit device

本発明は、 半導体集積回路装置の製造技術に関し、 特に、 スパッタリング法に よって成膜した C o (コバルト） 膜を使用したサリサイド（Sal i cide ; self alig ned silicide)プロセスに適用して有効な技術に関するものである。 背景技術  The present invention relates to a manufacturing technology of a semiconductor integrated circuit device, and particularly to a technology effective when applied to a salicide (Salicide; self-aligned silicide) process using a Co (cobalt) film formed by a sputtering method. It is about. Background art

従来、 S i (シリコン） 基板上に形成される半導体集積回路の電極、 配線材料 には、 主として多結晶シリコンや A 1 (ァノレミニゥム） が使用されてきた。 しか し、 近年の半導体素子の微細化に伴い、 新たな電極、 配線材料として、 S iより も低抵抗で、 A 1よりもエレクトロマイグレーション耐性が高い特長を備えた W (タングステン） 、 T i (チタン） 、 コバルトなどの高融点金属やそれらのシリ サイド化合物の導入が進められている。  Conventionally, polycrystalline silicon and A 1 (anoremium) have been mainly used as electrodes and wiring materials for semiconductor integrated circuits formed on Si (silicon) substrates. However, with the recent miniaturization of semiconductor devices, W (tungsten) and T i (with the features of lower resistance than Si and higher electromigration resistance than A 1 as new electrodes and wiring materials have been developed. Introduction of refractory metals such as titanium and cobalt and silicide compounds thereof are being promoted.

これらの電極、 配線用高融点金属 （シリサイド） 膜は、 高融点金属 （シリサイ ド） の粉末を焼結して作製したターゲットをアルゴン中でスパッタすることによ つて、 半導体ウェハ上に成膜される。  These refractory metal (silicide) films for electrodes and wiring are formed on a semiconductor wafer by sputtering a target made by sintering a refractory metal (silicide) powder in argon. You.

特開平 6— 1 9 2 9 7 4号公報、 特開平 6 - 1 9 2 9 7 9号公報および特開平 7— 3 4 8 6号公報は、 不純物、 特に N i (ニッケル） と F e (鉄） の含有量を 低減した純度 9 9 . 9 9 9 % ( 5 N)以上の高純度 C oを電解精製法により製造す る技術を開示している。 これらの高純度 C oは、半導体デバイスの電極、配線（電 極、 ゲート、 配線、 素子、 保護膜） に使用される C o膜を成膜するための C oタ —ゲットの製造に適用される。  Japanese Unexamined Patent Publications Nos. 6-192,974, 6-192,799 and 7-34886 describe impurities, particularly Ni (nickel) and Fe ( It discloses a technique for producing high-purity Co with a purity of 99.999% (5N) or more by reducing the content of iron) by electrolytic refining. These high-purity Cos are applied to the production of Co targets for forming Co films used for electrodes and wiring (electrodes, gates, wiring, elements, protective films) of semiconductor devices. You.

特開平 5— 1 3 7 0号公報は、 電極、 配線の断線や短絡などを引き起こす原因 となるパーティクルの発生を抑制できるスパッタリング用高融点金属シリサイ ド ターゲットの製造方法を開示している。 高融点金属としては、 W、 M o (モリブ デン） 、 T a (タンタル） 、 T i、 C o、 C r (クロム） が例示されている。 高融点金属シリサイド膜は、 上記のような高融点金属シリサイドのターゲット を使用して形成するほか、 高融点金属膜とシリコンとを反応させることによって 形成することも可能である。 Japanese Patent Application Laid-Open No. Hei 5-137700 discloses a method of manufacturing a high melting point metal silicide target for sputtering that can suppress generation of particles that cause disconnection or short circuit of electrodes and wiring. Examples of the high melting point metal include W, Mo (molybdenum), Ta (tantalum), Ti, Co, and Cr (chromium). The refractory metal silicide film can be formed by using the refractory metal silicide target as described above or by reacting the refractory metal film with silicon.

特開平 7— 3 2 1 0 6 9号公報は、 C oなどの強磁性体材料 2 0 atom%と、 T iなどの常磁性体材料 8 0 atom%とで構成される複合金属ターゲットを用いた マグネトロン 'スパッタリング法により、 M〇 S F E T (Metal Oxide Semicondu ctor Field Effect Transi stor)を形成した半導体基板全面に C o— T i膜を形 成し、 熱処理によつて多結晶シリコンゲート上およびソース、 ドレイン上に C o シリサイドー T iシリサイド混合層を形成した後、 上記混合層の未反応部分をェ ツチングで除去し、 次いで再度熱処理を行って混合層を低抵抗化する、 いわゆる サリサイドプロセスを開示している。 発明の開示  Japanese Patent Application Laid-Open No. 7-321069 uses a composite metal target composed of 20 atom% of a ferromagnetic material such as Co and 80 atom% of a paramagnetic material such as Ti. A magnetron 'sputtering method formed a Co-Ti film on the entire surface of the semiconductor substrate on which the metal oxide semiconductor field effect transistor (MFETSFET) was formed. After forming a Co silicide-Ti silicide mixed layer on the drain, an unreacted portion of the mixed layer is removed by etching, and then a heat treatment is performed again to lower the resistance of the mixed layer. ing. Disclosure of the invention

ところで、 0. 2 5 m以下といったディープ♦サブミクロンの ^計ルールで製 造される微細な MO S F E Tを使った大規模半導体デバイスの高速化、高性能化、 低消費電力化を推進しょうとする場合には、 配線遅延の低減対策と並んで MO S F E T単体の高速化対策が不可欠である。 これは、 MO S F E Tを微細化してい くとソース、 ドレインの抵抗が増大し、 これがトランジスタの高速動作を阻害す る大きな要因となるからである。 特に、 2 V以下の低電圧でトランジスタを駆動 する低消費電力デバイスの場合は、 MO S F E T単体の高速化対策が重要な課題 となる。  By the way, we want to promote high-speed, high-performance, and low power consumption of large-scale semiconductor devices using fine MOS SFETs manufactured with a deep ♦ sub-micron meter rule of 0.25 m or less. In such cases, measures to increase the speed of the MOS FET alone are indispensable along with measures to reduce wiring delay. This is because as the size of the MOSFET decreases, the resistance of the source and drain increases, which is a major factor that hinders high-speed operation of the transistor. In particular, in the case of low power consumption devices that drive transistors at a low voltage of 2 V or less, measures to increase the speed of the MOS FET alone are an important issue.

また、 MO S F E Tを 2 V以下の低電圧で駆動させる場合には、 従来の pチヤ ネル型 MO S F E Tのように、 ゲート電極を n型の多結晶シリコンで構成する埋 込みチャネル型構造では、 しきい値電圧 （V th) を制御することが困難になるた め、 その対策も必要となる。  In addition, when driving a MOS FET at a low voltage of 2 V or less, a buried channel structure in which the gate electrode is made of n-type polycrystalline silicon, as in a conventional p-channel type MOS SFET, has a problem. Since it becomes difficult to control the threshold voltage (V th), measures must be taken.

本発明者らは、 MO S F E Tの高速化対策として、 多結晶シリコンゲート上お よびソース、 ドレイン上に低抵抗の高融点金属シリサイ ド層を形成するサリサイ ドプロセスの導入を検討した。高融点金属材料としては、 1 5 μ Ω cm程度の低抵 抗シリサイドが得られる C oを選択した。 一方、 MO S F E Tのしきい値電圧制 御対策として、 pチヤネル型 M O S F E Tのゲート電極を p型多結晶シリコンで 構成して表面チヤネル型とし、 nチヤネル型 M O S F E Tのゲート電極を n型多 結晶シリコンで構成して表面チャネル型とするデュアルゲート CMO S構造の導 入を検討した。 このデュアルゲート C MO S構造を導入する場合には、 p型多結 晶シリコンゲートと n型多結晶シリコンゲートとの接続方法が問題となる力 多 結晶シリコンゲート上にシリサイド層を形成する上記サリサイ ドプロセスと組み 合わせることでこの問題は解決できる。 The present inventors have studied the introduction of a salicide process for forming a low-resistance high-melting-point metal silicide layer on a polycrystalline silicon gate and on a source and a drain as a measure for increasing the speed of a MOS FET. As the high melting point metal material, Co was selected, which can provide a low resistance silicide of about 15 μΩcm. On the other hand, the threshold voltage As a countermeasure, a dual gate in which the gate electrode of a p-channel MOSFET is made of p-type polycrystalline silicon to be a surface channel type, and the gate electrode of an n-channel MOSFET is made of n-type polycrystalline silicon and is a surface channel type The introduction of a CMOS structure was considered. In introducing this dual-gate CMOS structure, the above-mentioned salicide method for forming a silicide layer on a polycrystalline silicon gate is problematic in the connection method between the p-type polycrystalline silicon gate and the n-type polycrystalline silicon gate. This problem can be solved by combining this with a process.

MO S F E Tの多結晶シリコンゲート上およぴソース、 ドレイン上に C oシリ サイド層を形成するプロセスは、 以下の通りである。  The process for forming the Co silicide layer on the polycrystalline silicon gate and the source and drain of the MOS FET is as follows.

まず、 MO S F E Tを形成した半導体基板上に、 C oターゲットを用いたスバ ッタリング法で C o膜を堆積した後、 熱処理によって C oと S i とを反応させ、 ゲート、 ソースおよびドレインのそれぞれの表面に C oシリサイ ド層を形成する (第 1熱処理） 。 このとき得られる C oシリサイドは、 5 0〜 6 0 μ Ω cmと比較 的高抵抗のモノシリサイド （C o S i ) である。 次に、 未反応の C o膜をゥエツ トエッチングで除去した後、 もう一度基板を熱処理して上記モノシリサイドを低 抵抗のジシリサイ ド （C o S i 2) に相転移させる （第 2熱処理） 。 First, a Co film is deposited on a semiconductor substrate on which a MOS FET is formed by a sputtering method using a Co target.Then, heat treatment allows Co and Si to react with each other. A Co silicide layer is formed on the surface (first heat treatment). The Co silicide obtained at this time is monosilicide (CoSi) having a relatively high resistance of 50 to 60 µΩcm. Next, after the unreacted Co film is removed by wet etching, the substrate is again heat-treated to cause the monosilicide to undergo a phase transition to low-resistance disilicide (CoSi 2 ) (second heat treatment).

ところ力 本発明者が純度 9 9 . 9 %の C oターゲットを使って成膜した C o膜 に第 1の熱処理を施したところ、 得られた C oモノシリサイ ド （C o S i ) 層の 膜厚は、 熱処理の温度変化に対して高い依存性を示した。 具体的には、 熱処理温 度が高いほど膜厚が厚く、 低いほど薄くなるといった現象が見られ、 膜厚を安定 に制御することが困難であった。このような膜厚のばらつきが生じる主な原因は、 C oターゲット中に含まれる F eや N iなどの不純物遷移金属の一部がシリサイ ド化するためと考えられる。  However, the present inventor performed the first heat treatment on the Co film formed using a 99.9% pure Co target, and found that the obtained Co monosilicide (Co Si) layer The film thickness was highly dependent on the temperature change of the heat treatment. Specifically, a phenomenon was observed in which the higher the heat treatment temperature, the thicker the film thickness, and the lower the heat treatment temperature, the thinner the film thickness, and it was difficult to control the film thickness stably. It is considered that such a variation in the film thickness is mainly caused by silicidation of some of the impurity transition metals such as Fe and Ni contained in the Co target.

上記の検討結果から、 低抵抗の C oシリサイド層を得るためには、 第 1熱処理 温度を高く設定してモノシリサイド層の膜厚を十分に確保する必要がある。 しか し、 モノシリサイ ド層の膜厚を厚くすると、 ソース、 ドレインの p n接合が 0 . 3 μ mよりも浅くなる 0. 2 5 μ mMO Sデバイスでは、接合リーク電流が増大し てしまう。 この接合リーク電流の増大は、 基板中に侵入した C oと S i との反応 によって生じた過剰な格子間 S iが集合、 成長することによって生じると考えら れる。 From the above study results, in order to obtain a low-resistance Co silicide layer, it is necessary to set the first heat treatment temperature high and ensure a sufficient thickness of the monosilicide layer. However, when the thickness of the monosilicide layer is increased, the junction leakage current increases in a 0.25 μm MOS device in which the pn junction of the source and drain becomes shallower than 0.3 μm. This increase in junction leakage current is thought to be caused by the aggregation and growth of excess interstitial Si caused by the reaction between Co and Si that have penetrated the substrate. It is.

また、 第 1熱処理温度を高くすると、 ソース、 ドレインの端部において不所望 なシリサイ ド化反応が起こり易くなるために、 シリサイ ド層がフィールド絶縁膜 上やゲート側壁絶縁膜上に延びる、 いわゆる 「はい上がり」 が生じる結果、 微細 な MOSFETでは、 ソース、 ドレインとゲート間や、 隣り合った MOSFET のソース、 ドレイン同士で短絡が発生する。 特に、 デュアルゲート CMOSに適 用した場合には、 pチャネル型 MO S F E Tのゲート電極を構成する p型多結晶 シリコン中の不純物である B (ホウ素） がゲート酸化膜中に拡散し易くなるため に、 トランジスタの電気特性が変動するとレ、う問題も生じる。  In addition, when the first heat treatment temperature is increased, an undesired silicidation reaction is likely to occur at the end of the source and the drain, so that the silicide layer extends on the field insulating film and the gate sidewall insulating film. As a result of “rising up”, in a fine MOSFET, a short circuit occurs between the source and drain and the gate, and between the source and drain of adjacent MOSFETs. In particular, when applied to a dual-gate CMOS, B (boron), which is an impurity in the p-type polycrystalline silicon that forms the gate electrode of the p-channel MOSFET, is likely to diffuse into the gate oxide film. If the electrical characteristics of the transistor fluctuate, a problem may occur.

他方、 接合リーク電流の増大を回避するために第 1熱処理温度を低めに設定し てモノシリサイ ド層の膜厚を薄くした場合は、 シリサイ ド層の抵抗が増： まう。 また、 熱処理温度が低いとシリサイ ド化反応の進行も遅くなるので、 サイド層の抵抗が一層増大する。 さらに、 C oシリサイド層の膜厚が薄くなると その耐熱性が低下するために、 OS F E T形成後の熱処理工程（例えば N a (ナ トリウム） などの金属をゲッタリングするために P (リン） をドープした酸化シ リコン膜を MOS FETの上部に堆積し、 次いでこの酸化シリコン膜を高温でシ ンタリングする工程） で C oシリサイドの結晶粒が凝集する現象 （アグロメレー シヨン） が起こって抵抗が異常に増大する虞れがある。  On the other hand, if the thickness of the monosilicide layer is reduced by setting the first heat treatment temperature lower to avoid an increase in junction leakage current, the resistance of the silicide layer increases. Further, when the heat treatment temperature is low, the progress of the silicidation reaction is slowed, so that the resistance of the side layer is further increased. Furthermore, as the thickness of the Co silicide layer becomes thinner, its heat resistance decreases. Therefore, a heat treatment step after OS FET formation (for example, P (phosphorus) for gettering a metal such as Na (sodium)). A process of depositing a doped silicon oxide film on top of the MOS FET and then crystallizing the silicon oxide film at a high temperature) causes the co-silicide crystal grains to aggregate (agglomeration), resulting in abnormal resistance. It may increase.

そこで、 本発明による半導体集積回路装置の製造方法は、 以下の工程 （a) 〜 (d) を含んでいる。  Therefore, a method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps (a) to (d).

( a ) ウェハの主面に MO S F E Tを形成する工程、  (a) a process of forming MO SFE T on the main surface of the wafer,

(b) 高純度の C oターゲットを用いたスパッタリング法によって、 前記ウェハ の主面上の少なくとも前記 MOS FETのゲート電極、 ソースおよびドレインの それぞれの上部を含む領域に C o膜を堆積する工程、  (b) depositing a Co film on a main surface of the wafer by sputtering using a high-purity Co target at least in a region including an upper portion of each of a gate electrode and a source and a drain of the MOS FET;

(c)前記ウェハに第 1の熱処理を施して C oと S i とを反応させることにより、 前記 MO S F ETのゲート電極、 ソースおよびドレインのそれぞれの表面に C o シリサイド層を形成する工程、  (c) forming a Co silicide layer on each surface of the gate electrode, the source and the drain of the MOSFET by subjecting the wafer to a first heat treatment so that Co and Si react with each other;

(d) 前記 Co膜の未反応部分を除去した後、 前記ウェハに第 2の熱処理を施し て前記 C oシリサイド層を低抵抗化する工程。 また、 本発明による半導体集積回路装置の製造方法は、 Coと S i との反応に よってシリコンの表面に C o S i 2層を形成するに際し、 少なくとも第 1熱処理 温度依存性が小さく、 膜厚制御性が向上した C o S i層が得られる高純度 C oタ ーゲットを用いて C o膜を堆積することにより、 C o S i 2層のシート抵抗を 1 0 Ω /口以下とするものである。 (d) a step of performing a second heat treatment on the wafer after removing an unreacted portion of the Co film to lower the resistance of the Co silicide layer. Further, the method of manufacturing a semiconductor integrated circuit device according to the present invention, when forming a CoSi 2 layer on the surface of silicon by the reaction of Co and Si, has at least a small first heat treatment temperature dependency and a film thickness. By depositing a Co film using a high-purity Co target that provides a Co Si layer with improved controllability, the sheet resistance of the Co Si 2 layer should be 10 Ω / port or less. It is.

本発明で使用する高純度 C oターゲットは、少なくとも C o純度が 99.99% 以上で、 F eまたは N iの含有量が 1 0 p pm以下、 あるいは F eおよび N iの 含有量が 50 p p m以下である。 より好ましくは、 C o純度が 99.99 %以上で、 F eおよび N iの含有量が 10 p p m以下のもの、 さらに好ましくは C。純度が 99.999%のものを使用する。  The high-purity Co target used in the present invention has a Co purity of at least 99.99% and a Fe or Ni content of 10 ppm or less, or a Fe and Ni content of 50 ppm or less. It is. More preferably, the purity of Co is 99.99% or more, and the content of Fe and Ni is 10 ppm or less. Use with a purity of 99.999%.

本発明において 「ウェハ」 とは、 主にその表面領域に半導体集積回路装置を作 り込む少なくとも一定の工程の後には、 少なくとも一部が単一のまたは複数の単 結晶領域 （ここでは主にシリコン） からなる板状物をいう。 また、 本発明におい て 「半導体集積回路装置」 とは、 通常の単結晶ウェハ上に作られたものの他、 T FT液晶などのような他の基板上に作られたものも含むものとする。  In the present invention, the term “wafer” refers to a single or multiple single-crystal regions (here, mainly silicon) after at least a certain step of manufacturing a semiconductor integrated circuit device mainly in a surface region thereof. ) A plate-like object consisting of Further, in the present invention, the “semiconductor integrated circuit device” includes not only a device formed on a normal single crystal wafer but also a device formed on another substrate such as a TFT liquid crystal.

その他、 本願に記載された発明の概要を項分けして説明すれば以下の通りであ る。  In addition, the summary of the invention described in the present application will be described as follows, divided into sections.

(1) 本発明の半導体集積回路装置の製造方法は、 以下の工程を含む；  (1) A method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps:

(a) ウェハの主面に M〇S FETを形成する工程、  (a) forming a M〇S FET on the main surface of the wafer,

(b) 高純度の C oターゲットを用いたスパッタリング法によって、 前記ウェハ の主面上の少なくとも前記 MO S F ETのゲート電極、 ソースおよびドレインの それぞれの上部を含む領域に C o膜を堆積する工程、  (b) depositing a Co film on a main surface of the wafer by sputtering using a high-purity Co target at least in a region including the upper portions of the gate electrode, the source, and the drain of the MOSFET. ,

( c )前記ウェハに第 1.の熱処理を施して C oと S i とを反応させることにより、 前記 MOS FETのゲート電極、 ソースおよびドレインのそれぞれの表面に C o シリサイド層を形成する工程、  (c) forming a Co silicide layer on each surface of the gate electrode, source and drain of the MOS FET by subjecting the wafer to a first heat treatment to react Co and Si;

(d) 前記 C o膜の未反応部分を除去した後、 前記ウェハに第 2の熱処理を施し て前記 C oシリサイ ド層を低抵抗化する工程。  (d) a step of performing a second heat treatment on the wafer after removing an unreacted portion of the Co film to lower the resistance of the Co silicide layer.

(2) 本発明の半導体集積回路装置の製造方法は、 前記 Coターゲットの C o純 度が 99.99 %以上であり、 F eまたは N iの含有量が 10 ϋ p m以下である。 ( 3 ) 本発明の半導体集積回路装置の製造方法は、 前記 C oターゲットの C o純 度力 S 99.99 %以上であり、 F eおよび N iの含有量が 50 p p m以下である。 (2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the Co target has a Co purity of 99.99% or more and a Fe or Ni content of 10 ppm or less. (3) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the Co purity power S of the Co target is 99.99% or more, and the contents of Fe and Ni are 50 ppm or less.

(4) 本発明の半導体集積回路装置の製造方法は、 前記 C oターゲットの C o純 度が 99.99 %以上であり、 F eおよび N iの含有量が 1 0 p p m以下である。  (4) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the Co target has a Co purity of 99.99% or more and Fe and Ni contents of 10 ppm or less.

(5) 本発明の半導体集積回路装置の製造方法は、 前記 Coターゲットの Co純 度が 99.999%である。  (5) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the Co target has a Co purity of 99.999%.

(6) 本発明の半導体集積回路装置の製造方法は、 前記第 1の熱処理の温度が 4 75:C〜525°Cである。 (6) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the temperature of the first heat treatment is 475 : C to 525 ° C.

(7) 本発明の半導体集積回路装置の製造方法は、 前記第 2の熱処理の温度が 6 50°C〜800。Cである。  (7) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the temperature of the second heat treatment is 650 ° C. to 800 ° C. C.

(8) 本発明の半導体集積回路装置の製造方法は、 前記 C o膜の膜厚が 1 8〜6 0體である ώ (8) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the Co film has a thickness of 18 to 60 bodies.

(9) 本発明の半導体集積回路装置の製造方法は、 前記第 2の熱処理を施した後 の前記 C οシリサイド層のシート抵抗が 1 0 Ω/口以下である。  (9) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, a sheet resistance of the Co silicide layer after performing the second heat treatment is 10 Ω / port or less.

(10) 本発明の半導体集積回路装置の製造方法は、 前記ソース、 ドレインの接 合深さが 0.3 μ m以下である。  (10) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, a junction depth of the source and the drain is 0.3 μm or less.

(1 1) 本発明の半導体集積回路装置の製造方法は、 以下の工程を含む； (11) A method of manufacturing a semiconductor integrated circuit device of the present invention includes the following steps;

(a) ゲート絶縁膜を形成したウェハの主面上に多結晶シリコン膜および第 1絶 縁膜を堆積した後、 前記第 1絶縁膜および前記多結晶シリコン膜をパターユング することにより、 前記ウェハの第 1領域に第 1ゲート電極パターンを形成し、 第 2領域に第 2ゲート電極パターンを形成する工程、 (a) depositing a polycrystalline silicon film and a first insulating film on a main surface of a wafer on which a gate insulating film is formed, and then patterning the first insulating film and the polycrystalline silicon film to form the wafer; Forming a first gate electrode pattern in a first region of the first region, and forming a second gate electrode pattern in a second region of the first region,

(b) 前記ウェハの第 1領域に第 1導電型の不純物をイオン打ち込みして、 前記 第 1ゲート電極パターンの両側の前記ウェハに低不純物濃度の第 1導電型半導体 領域を形成し、 前記ウェハの第 2領域に第 2導電型の不純物をイオン打ち込みし て、 前記第 2ゲート電極パターンの両側の前記ウェハに低不純物濃度の第 2導電 型半導体領域を形成する工程、  (b) ion-implanting a first conductivity type impurity into a first region of the wafer to form a low impurity concentration first conductivity type semiconductor region on the wafer on both sides of the first gate electrode pattern; Ion-implanting a second conductivity type impurity into the second region to form a low impurity concentration second conductivity type semiconductor region on the wafer on both sides of the second gate electrode pattern;

(c) 前記ウェハの主面上に堆積した第 2絶縁膜をパターニングして、 前記第 1 およぴ第 2ゲート電極パターンのそれぞれの側壁にサイ ドウォールスべ一サを形 成すると共に、 前記第 1およぴ第 2ゲート電極パターンのそれぞれの前記第 1絶 縁膜を除去することにより、 前記多結晶シリコン膜の表面を露出させる工程、(c) patterning a second insulating film deposited on the main surface of the wafer to form side wall sensors on respective side walls of the first and second gate electrode patterns; The first and second gate electrode patterns, respectively. Exposing the surface of the polycrystalline silicon film by removing the edge film;

(d) 前記ウェハの第 1領域に第 1導電型の不純物をイオン打ち込みして、 前記 第 1ゲ一卜電極パターンの前記多結晶シリコン膜で第 1導電型の第 1ゲート電極 を形成すると共に、 前記第 1ゲート電極の両側の前記ウェハに高不純物濃度の第 1導電型半導体領域を形成し、 前記ウェハの第 2領域に第 2導電型の不純物をィ オン打ち込みして、 前記第 2ゲート電極パターンの前記多結晶シリコン膜で第 2 導電型の第 2ゲート電極を形成すると共に、 前記第 2ゲート電極の両側の前記ゥ ェハに高不純物濃度の第 2導電型半導体領域を形成する工程、 (d) ion-implanting a first conductivity type impurity into a first region of the wafer to form a first conductivity type first gate electrode with the polycrystalline silicon film of the first gate electrode pattern; Forming a first conductive type semiconductor region having a high impurity concentration on the wafer on both sides of the first gate electrode, and ion-implanting a second conductive type impurity into a second region of the wafer; Forming a second conductivity type second gate electrode from the polycrystalline silicon film of the electrode pattern, and forming a high impurity concentration second conductivity type semiconductor region on the wafer on both sides of the second gate electrode; ,

(e) 高純度の C oターゲットを用いたスパッタリング法によって、 前記ウェハ の主面上に C o膜を堆積する工程、  (e) depositing a Co film on the main surface of the wafer by a sputtering method using a high-purity Co target,

(f )前記ウェハに第 1の熱処理を施して Coと S i とを反応させることにより、 前記第 1および第 2ゲート電極の表面と、 前記高不純物濃度の第 1および第 2導 電型半導体領域の表面とに C oシリサイド層を形成する工程、  (f) subjecting the wafer to a first heat treatment to cause Co and Si to react with each other, so that the surfaces of the first and second gate electrodes and the first and second conductive semiconductors having a high impurity concentration; Forming a Co silicide layer on the surface of the region,

(g) 前記 Co膜の未反応部分を除去した後、 前記ウェハに第 2の熱処理を施し て前記 C oシリサイド層を低抵抗化する工程。  (g) a step of performing a second heat treatment on the wafer after removing an unreacted portion of the Co film to lower the resistance of the Co silicide layer.

(1 2) 本発明の半導体集積回路装置の製造方法は、 前記 MOSFETの動作電 源電圧は、 2 V以下である。  (12) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the operating power supply voltage of the MOSFET is 2 V or less.

(1 3) 本発明の半導体集積回路装置の製造方法は、 前記 Coターゲットの C o 純度が 99.99 %以上であり、 F eまたは N iの含有量が 10 p p m以下である。  (13) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the Co target has a Co purity of 99.99% or more and a Fe or Ni content of 10 ppm or less.

(14) 本発明の半導体集積回路装置の製造方法は、 前記 C oターゲットの C o 純度が 99.99 %以上であり、 F eおよび N iの含有量が 50 p p m以下である。  (14) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the Co target has a Co purity of 99.99% or more, and a content of Fe and Ni is 50 ppm or less.

(1 5) 本発明の半導体集積回路装置の製造方法は、 前記 C oターゲットの C o 純度が 99.99 %以上であり、 F eおよび N iの含有量が 1 0 p p ra以下である。  (15) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the Co target has a Co purity of 99.99% or more, and a content of Fe and Ni is 10 ppra or less.

(16) 本発明の半導体集積回路装置の製造方法は、 前記 C oターゲットの C o 純度が 99.999 %である。  (16) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the Co target has a Co purity of 99.999%.

(1 7) 本発明の半導体集積回路装置の製造方法は、 以下の工程を含む； (17) The method for manufacturing a semiconductor integrated circuit device of the present invention includes the following steps:

(a) ウェハの主面に M〇 S F ETを形成した後、 前記 MO S F ETのゲート電 極、 ソースおょぴドレインのそれぞれの表面を露出させる工程、 ( a ) forming M〇 SF ET on the main surface of the wafer, and then exposing the respective surfaces of the gate electrode and the source / drain of the MO SF ET;

(b) 高純度の C oターゲットを用いたスパッタリング法によって、 前記 M〇S F E Tのゲート電極、 ソースおよびドレインのそれぞれの表面を含む前記ゥ の主面上に C o膜を堆積する工程、 ， (b) The above-mentioned M に よ っ て S by sputtering method using a high-purity Co target. Depositing a Co film on the main surface of the gate including the respective surfaces of the gate electrode, source and drain of the FET;

(c)前記ウェハに第 1の熱処理を施して Coと S i とを反応させることにより、 前記 MOS FETのゲート電極、 ソースおよびドレインのそれぞれの表面に、 主 として C oモノシリサイドからなる C oシリサイド層を形成する工程、  (c) By subjecting the wafer to a first heat treatment to cause Co and Si to react with each other, the surface of each of the gate electrode, source, and drain of the MOS FET is mainly composed of Co monosilicide. Forming a silicide layer,

(d) 前記 C o膜の未反応部分を除去した後、 第 2の熱処理を施して前記 C oシ リサイド層を主として C oジシリサイドからなる C oシリサイ ド層に相転移させ る工程、  (d) after removing unreacted portions of the Co film, performing a second heat treatment to phase-transform the Co silicide layer into a Co silicide layer mainly composed of Co disilicide,

( e ) 前記 M O S F E Tの上部に金属不純物をゲッタリングするための不純物を をドープした酸化シリコン膜を堆積した後、 前記酸化シリコン膜に第 3の熱処理 を施す工程。  (e) depositing a silicon oxide film doped with an impurity for gettering metal impurities on the MOSFET, and then subjecting the silicon oxide film to a third heat treatment.

(1 8) 本発明の半導体集積回路装置の製造方法は、 前記不純物をド一ブした酸 化シリコン膜が P S G膜である。  (18) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the silicon oxide film doped with the impurity is a PSG film.

(1 9) 本発明の半導体集積回路装置の製造方法は、 前記第 3の熱処理の温度が 700 °C〜 800 Cである。  (19) In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the temperature of the third heat treatment is 700 ° C to 800 ° C.

本発明の目的は、 低抵抗で、 かつ接合リーク電流の少ない C oシリサイド層を 形成することのできるサリサイドプロセスを提供することにある。  An object of the present invention is to provide a salicide process capable of forming a Co silicide layer having low resistance and low junction leakage current.

本発明の前記ならびにその他の目的と新規な特徴は、 明細書の記述および添付 図面から明らかになるであろう。 図面の簡単な説明  The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings. BRIEF DESCRIPTION OF THE FIGURES

図 1〜図 7、 図 9、 図 1 2、 図 1 3、 図 16〜図 20は、 本発明の実施の形態 である半導体集積回路装置の製造方法を示す半導体基板の要部断面図、 図 8は、 不純物を活性化するための 750 eC、 30分の熱処理とこの不純物により形成さ れるソース、 ドレインのリーク電流の関係を示すグラフ、 図 10は、 C o膜の堆 積に用いるスパッタリング装置のチャンバの概略図、 図 1 1は、 C oターゲット の斜視図、 図 14は、 ゲート電極、 ソースおよびドレインのそれぞれの表面に C oシリサイド層を形成した nチャネル型 MOS FETおよび pチャネル型 MOS FETの拡大図、 図 1 5は、 C oシリサイド層のシート抵抗と第 1の熱処理温度 との関係を示すグラフである。 発明を実施するための最良の形態 1 to 7, FIG. 9, FIG. 12, FIG. 13, FIG. 16 to FIG. 20 are cross-sectional views of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. 8 is a graph showing the relationship between the heat treatment at 750 eC for 30 minutes for activating the impurity and the leakage current of the source and drain formed by this impurity, and Fig. 10 is the sputtering used for depositing the Co film. Schematic diagram of the chamber of the device, Fig. 11 is a perspective view of the Co target, and Fig. 14 is an n-channel MOS FET and p-channel type with Co silicide layers formed on the gate electrode, source and drain surfaces. Enlarged view of MOS FET, Figure 15 shows sheet resistance of Co silicide layer and first heat treatment temperature 6 is a graph showing a relationship with the graph. BEST MODE FOR CARRYING OUT THE INVENTION

本発明をより詳述するために、 添付の図面に従ってこれを説明する。 なお、 実 施の形態を説明するための全図において、 同一機能を有するものは同一符号を付 け、 その繰り返しの説明は省略する。  The present invention will be described in more detail with reference to the accompanying drawings in order to explain it in more detail. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted.

本実施の形態は、設計ルールが 0. 2 5 μ mで動作電源電圧が 2 Vのデュアルゲ ート CMO Sプロセスに適用したものであるが、 本発明がこの実施の形態によつ て限定されるものでないことは勿論である。  This embodiment is applied to a dual-gate CMOS process in which the design rule is 0.25 μm and the operating power supply voltage is 2 V, but the present invention is limited by this embodiment. Of course, it is not.

デュアルゲート構造の C MO S F E Tを形成するには、まず図 1に示すように、 比抵抗が 1 0 Ω era程度の p—型単結晶シリコンからなる半導体基板 1の表面を熱 酸化して膜厚 1 0 腿の酸化シリコン膜 2を形成した後、この酸化シリコン膜 2上 に C V D法で膜厚 1 0 0 nmの窒化シリコン膜 3を堆積する。次に、 フォトレジス トをマスクにしたドライエッチングで窒化シリコン膜 3をパターエングして、 素 子分離領域の窒化シリコン膜 3を除去する。  To form a CMO SFET with a dual-gate structure, first, as shown in Fig. 1, the surface of a semiconductor substrate 1 made of p-type single-crystal silicon having a specific resistance of about 10 Ω era is thermally oxidized to form a film. After the silicon oxide film 2 on the thigh is formed, a silicon nitride film 3 having a thickness of 100 nm is deposited on the silicon oxide film 2 by a CVD method. Next, the silicon nitride film 3 is patterned by dry etching using a photoresist as a mask to remove the silicon nitride film 3 in the element isolation region.

次に、 図 2に示すように、 上記窒化シリコン膜 3をマスクにして酸化シリコン 膜 2と半導体基板 1とをェツチングすることにより、 素子分離領域の半導体基板 1に深さ 3 5 0 ηπιの溝 4 aを形成する。  Next, as shown in FIG. 2, by etching the silicon oxide film 2 and the semiconductor substrate 1 using the silicon nitride film 3 as a mask, a trench having a depth of 350 nm ηπι is formed in the semiconductor substrate 1 in the element isolation region. Form 4a.

次に、 図 3に示すように、 半導体基板.1.上に C V D法で酸化シリコン膜 5を堆 積した後、 CM P法でその表面を平坦化して溝 4 aの内部に酸化シリコン膜 5を 残すことにより、 素子分離溝 4を形成する。 続いて、 1 0 0 O t:の熱処理を施し て素子分離溝 4の内部の酸化シリコン膜 5をデンシフアイした後、 熱リン酸を用 いたゥエツトエッチングで窒化シリコン膜 3を除去する。  Next, as shown in FIG. 3, after depositing a silicon oxide film 5 on the semiconductor substrate 1 by the CVD method, the surface thereof is flattened by the CMP method, and the silicon oxide film 5 is The element isolation groove 4 is formed by leaving the trench. Subsequently, a heat treatment of 100 Ot: is performed to densify the silicon oxide film 5 inside the element isolation trench 4, and then the silicon nitride film 3 is removed by wet etching using hot phosphoric acid.

次に、 図 4に示すように、 半導体基板 1に n型ゥエル 6 nおよび p型ゥエル 6 pを形成する。 まず、 pチャネル型 MO S F E Tの形成領域を開孔したフォトレ ジストをマスクにして半導体基板 1に n型ゥエルを形成するための不純物をィォ ン打ち込みし、 さらに pチヤネル型 M〇 S F E Tのしきレ、値電圧を調整するため の不純物をイオン打ち込みする。 n型ゥエル形成用の不純物は、例えば P (リン） を使用し、 エネルギー = 3 6 0 k e V、 ドーズ量 = 1 . 5 X 1 0 l3/cm2でイオン打 ち込みする。 また、 しきい値電圧調整用の不純物は、 例えば Pを使用し、 ェネル ギ一 = 4 0 :k e V、 ドーズ量 = 2 X 1 0 I2/cm2でイオン打ち込みする。 次に、 上 記フォトレジストを除去した後、 nチャネル型 M〇 S F E Tの形成領域を開孔し たフォ トレジストをマスクにして半導体基板 1に p型ゥエルを形成するための不 純物をイオン打ち込みし、 さらに nチャネル型 MO S F ETのしきい値電圧を調 整するための不純物をイオン打ち込みする。 p型ゥエル形成用の不純物は、 例え ば B (ホゥ素） を使用し、 エネルギ一 = 2 0 0 k e V、 ドーズ量 = 1. 0 X 1 0 1 3ん m2でイオン打ち込みする。 また、 しきい値電圧調整用の不純物は、 例えばフッ 化ホウ素 （B F 2)を使用し、 エネルギー = 40 k e V、 ドーズ量 = 2 X 1 0 /c ni2でィオン打ち込みする。 その後、 半導体基板 1を 9 5 0でで 1分間熱処理して 上記不純物を活性化することにより、 n型ゥエル 6 nおよび p型ゥエル 6 pを形 成する。 Next, as shown in FIG. 4, an n-type well 6 n and a p-type well 6 p are formed on the semiconductor substrate 1. First, an impurity for forming an n-type well is ion-implanted into the semiconductor substrate 1 using a photoresist in which a region for forming a p-channel type MOSFET is opened as a mask. Then, an impurity for adjusting the value voltage is ion-implanted. As an impurity for forming an n-type well, for example, P (phosphorus) is used, and ion implantation is performed at an energy of 360 keV and a dose of 1.5 × 10 13 / cm 2 . Insert As the impurity for adjusting the threshold voltage, for example, P is used, and ions are implanted at an energy of 40: keV and a dose of 2 × 10 I2 / cm 2 . Next, after removing the photoresist, an impurity for forming a p-type well in the semiconductor substrate 1 is ion-implanted in the semiconductor substrate 1 using the photoresist in which an n-channel M〇SFET formation region is opened as a mask. Then, an impurity for adjusting the threshold voltage of the n-channel MOSFET is ion-implanted. impurity for p-type Ueru formation uses B (Houmoto) For example, ion implantation with an energy 0 0 ke V, a dose = 1. 0 X 1 0 1 3 I m 2. As the impurity for adjusting the threshold voltage, for example, boron fluoride (BF 2 ) is used, and ion implantation is performed at an energy of 40 keV and a dose of 2 × 10 / c ni 2 . Thereafter, the semiconductor substrate 1 is heat-treated at 950 for 1 minute to activate the impurities, thereby forming the n-type well 6n and the p-type well 6p.

次に、 図 5に示すように、 半導体基板 1を熱酸化して n型ゥエル 6 n、 p型ゥ エル 6 pのそれぞれの活性領域の表面に膜厚 4 nm のゲート酸化膜 7を形成した 後、半導体基板 1上に CVD法で膜厚 2 5 0 nmの多結晶シリコン膜 8を堆積し、 さらに、 この多結晶シリコン膜 8上に CVD法で酸化シリコン膜 9を堆積する。 この多結晶シリコン膜 8には n型不純物も p型不純物もドーブしない。  Next, as shown in FIG. 5, the semiconductor substrate 1 was thermally oxidized to form a 4 nm-thick gate oxide film 7 on the surface of each of the active regions of the n-type well 6 n and the p-type well 6 p. Thereafter, a 250-nm-thick polycrystalline silicon film 8 is deposited on the semiconductor substrate 1 by the CVD method, and a silicon oxide film 9 is deposited on the polycrystalline silicon film 8 by the CVD method. Neither n-type impurities nor p-type impurities are doped into this polycrystalline silicon film 8.

次に、 図 6に示すように、 フォトレジストをマスクにして酸化シリコン膜 9お よび多結晶シリコン膜 8をエッチングすることにより、 p型ゥエル 6 p上に nチ ャネル型 MO S F ETのゲート電極 8 nを形成し、 n型ゥエル上に pチャネル型 MO S F ETのゲート電極 8 pを形成する。 ゲート電極 8 nおよぴゲート電極 8 pは、 グート長 =0. 2 5 μ mで形成する。  Next, as shown in FIG. 6, by etching the silicon oxide film 9 and the polycrystalline silicon film 8 using the photoresist as a mask, the gate electrode of the n-channel MOSFET is formed on the p-type well 6 p. 8 n is formed, and a gate electrode 8 p of p-channel type MOSFET is formed on the n-type well. The gate electrode 8 n and the gate electrode 8 p are formed with a gout length of 0.25 μm.

次に、 フォトレジストおよびゲート電極 8 pをマスクにして n型ゥエル 6 nに p型不純物 （B F ?) をエネルギー = 2 0 k e V、 ドーズ量： = 7. 0 X 1 0 13ん1112 でイオン打ち込みした後、 フォトレジストおよびゲート電極 8 nをマスクにして p型ゥエル 6 pにエネルギー = 2 0 k e V、 ドーズ量 = 3. 0 X 1 0 "/cm2で n型 不純物 （ヒ素 （A s ) ) をイオン打ち込みする。 続いて、 半導体基板 1を 1 0 0 0 C、 1 0秒間熱処理して上記不純物を活性化することにより、 ゲート電極 8 p の両側の n型ゥエル 6 nに p -型半導体領域 1 0を形成し、ゲート電極 8 nの両側 の p型ゥエル 6 pに n—型半導体領域 1 1を形成する。 Next, using the photoresist and the gate electrode 8 p as a mask, an n-type well 6 n is doped with a p-type impurity (BF ? ) At an energy of 20 keV and a dose of = 7.0 X 10 13 11 12 After the ion implantation, the photoresist and the gate electrode 8 n are used as masks, and the p-type well 6 p has an energy of 20 keV, a dose of 3.0 X 10 "/ cm 2 and an n-type impurity (arsenic (A Then, the semiconductor substrate 1 is heat-treated at 100 ° C. for 10 seconds to activate the above impurities, so that the n-type well 6 n on both sides of the gate electrode 8 p is p-doped. -Type semiconductor region 10 is formed, on both sides of gate electrode 8 n An n-type semiconductor region 11 is formed in the p-type well 6 p of the semiconductor device.

次に、 図 7に示すように、 ゲート電極 8 n、 8 pの側壁にゲート長方向の膜厚 が 0. 1 / mのサイドウ -ールスべーサ.1 2を形成する。サイドウォールスぺーサ 12は、 半導体基板 1上に CVD法で堆積した酸ィ匕シリコン膜を反応性イオンェ ツチング法で異方的にエッチングして形成する。 このエッチングを行うとき、 ゲ 一ト電極 8 n、 8 pの上部の酸化シリコン膜 9も同時にエッチングしてゲート電 極 8 n、 8 pの表面を露出させる。  Next, as shown in FIG. 7, a side wall spacer 12 having a thickness in the gate length direction of 0.1 / m is formed on the side walls of the gate electrodes 8 n and 8 p. The sidewall spacers 12 are formed by anisotropically etching a silicon oxide film deposited on the semiconductor substrate 1 by a CVD method by a reactive ion etching method. When this etching is performed, the silicon oxide film 9 above the gate electrodes 8n and 8p is also etched to expose the surfaces of the gate electrodes 8n and 8p.

次に、 フォ トレジストをマスクにして n型ゥエル 6 nおよびゲート電極 7 に p型不純物 （B) をエネルギー = 2 0 k e V、 ドーズ量 = 1. 0 X 1 0 "/cm2でィ オン打ち込みした後、 再度 p型不純物 （B) をエネルギー =5 k e V、 ドーズ量 - 2. 0 X 1 0 ん m2でイオン打ち込みする。 次に、 フォトレジストをマスクにし て p型ゥエル 6 pおよぴゲート電極 8 nに n型不純物 ( P ) をエネルギー =40 k e V、 ドーズ量 = 2. 0 X 1 0 "/cm2でイオン打ち込みした後、 n型不純物 （A s ) をエネルギー = 60 k e V、 ドーズ量 = 3.0 X 1 0 15ん m2でイオン打ち込み する。 続いて、 半導体基板].を 1 000°C、 1 0秒間熱処理して上記不純物を活 性化することにより、 n型ゥエル 6 nに pf型半導体領域 1 3を形成すると共にゲ ート電極 8 pの導電型を p型にする。 また、 p型ゥエル 6 pに n+型半導体領域 1 4を形成すると共にゲート電極 8 nの導電型を n型にする。 p ÷型半導体領域 1 3 および n+型半導体領域 1 4は、 それぞれ 2〜0. 1 μ mの接合深さで形成する,:. なお、上記 n型不純物および p型不純物を活性化するための熱処理（ 1000 、 10秒） に先だって、半導体基板 1を 750°C、 30分間熱処理することにより、 図 8に示すように、 n+型半導体領域 1 4の （ητ/ρ) 接合リークを低減するこ とができる。 これは、 イオン打ち込みの際に半導体基板 1に導入された点欠陥が この熱処理で回復するためである。 この場合、 Ρ型半導体領域 1 3も同様の効果 が期待できるが、 p+型半導体領域 1 3の不純物 （B) は拡散速度が大きいため、 この程度の温度の熱処理でもある程度拡散してしまう。 それを防ぐために、 まず 型半導体領域 14を形成するためのイオン打ち込みを行った直後に 750 ：、 30分の熱処理を行い、次に、 ρ '型半導体領域 1 3を形成するためのイオン打ち 込みを行った後に 1 000°C、 1 0秒の熱処理を行ってもよい c 次に、 p +型半導体領域 1 3、 n ÷型半導体領域 1 4のそれぞれの表面のゲート 酸化膜 7をフッ酸 （H F ) を用いたウエットエッチングで除去した後、 図 9に示 すように、 C oターゲットを用いたスパッタリング法で半導体基板 1上に膜厚 1 5 nmの C o膜 1 6を堆積し、 さらに C o膜 1 6上に膜厚 1 0〜1 5 nmの酸化防 止膜 1 7を堆積する。 酸化防止膜 1 7は、 例えばスパッタリング法で堆積した T i NS莫を使用する。 じ。膜1 6の膜厚は、 1 8〜6 0 雇の範囲とすることが好ま しい。膜厚が 1 8 nm以下では C oシリサイド層のシート抵抗を ]. 0 Ω /口以下に 低減することが困難になり、 6 0皿以上ではソース、 ドレインの接合リーク電流 が大きくなる。 Next, using a photoresist as a mask, p-type impurities (B) are ion-implanted into the n-type well 6 n and the gate electrode 7 at an energy of 20 keV and a dose of 1.0 × 10 ″ / cm 2. after again p-type impurity (B) energy = 5 ke V, a dose -. 2. ion implantation at 0 X 1 0 m 2 Next, Oyo p-type Ueru 6 p using the photoresist as a mask Pi gate electrode 8 n to n-type impurity (P) energy = 40 ke V, after ion implantation at a dose amount = 2. 0 X 1 0 "/ cm 2, n -type impurity (a s) of energy = 60 ke V, ion implantation at a dose amount = 3.0 X 1 0 15 m 2. Subsequently, the semiconductor substrate. By activity the 1 000 ° C, 1 0 seconds heat treatment to the impurities, Gate electrode to form a p f-type semiconductor region 1 3 to n-type Ueru 6 n 8 Change the conductivity type of p to p-type. Also, an n + -type semiconductor region 14 is formed in the p-type well 6 p and the conductivity type of the gate electrode 8 n is made n-type. The p ÷ type semiconductor region 13 and the n + type semiconductor region 14 are formed at a junction depth of 2 to 0.1 μm, respectively. In order to activate the n-type impurity and the p-type impurity, Prior to the heat treatment (1000, 10 seconds), the semiconductor substrate 1 is heat-treated at 750 ° C. for 30 minutes to reduce the (η τ / ρ) junction leakage of the n + type semiconductor region 14 as shown in FIG. It can be reduced. This is because the point defect introduced into the semiconductor substrate 1 at the time of ion implantation is recovered by this heat treatment. In this case, the same effect can be expected in the Ρ-type semiconductor region 13, but the impurity (B) in the p + -type semiconductor region 13 has a high diffusion rate, and therefore, the heat treatment at such a temperature causes some diffusion. To prevent this, first heat treatment for 750: 30 minutes is performed immediately after ion implantation for forming the type semiconductor region 14, and then ion implantation for forming the ρ′-type semiconductor region 13. an optionally subjected to a heat treatment of 1 000 ° C, 1 0 seconds after c Then, after removing by wet etching using p + -type semiconductor region 1 3, n ÷ type semiconductor region 1 4 hydrofluoric acid gate oxide film 7 of each surface (HF), as shown in Figure 9 Then, a 15 nm-thick Co film 16 is deposited on the semiconductor substrate 1 by sputtering using a Co target, and a 10- to 15-nm-thick oxidation prevention film is formed on the Co film 16. Film 17 is deposited. The antioxidant film 17 uses, for example, TiNs deposited by a sputtering method. Same. The thickness of the film 16 is preferably in the range of 18 to 60 employment. When the film thickness is less than 18 nm, it is difficult to reduce the sheet resistance of the Co silicide layer to] .0 Ω / port or less, and when the film thickness is more than 60 plates, the source and drain junction leakage currents increase.

図 1 0は、 上記 C o膜 1 6の堆積に用いるスパッタリング装置のチャンバの概 略図である。 このチャンバ 1 0 0は、 その内部が真空排気されるようになってお り、 成膜時には A rガスが導入されて圧力が数 mTorr程度に維持される。 半導体 基板 1 (ウェハ） を載置するホルダ 1 0 1の上方には、 スパッタ電極 1 0 2に保 持された C oターゲット 1. 0 3が半導体基板 1に対向して配置されており、 この C oターゲット 1 0 3に接続されたスパッタ電源 1 0 4が作動して定常放電が開 始されると、 C oターゲット 1 0 3に印加された負の高電圧によって、 C oター ゲット 1 0 3と半導体基板 1との隙間にプラズマ 1 0 5が形成される。 そして、 このプラズマ 1 0 5から C oターゲット 1 0 3に向かって加速された A rイオン が C oターゲット 1 0 3の表面を衝撃すると、 ターゲット構成材料 （C o ) が分 子 （原子） レベルで飛散して半導体基板 1の表面に C o膜 1 6が堆積する。 図 1 1は、 上記 C 0ターゲット 1 0 3の斜視図である。 本実施の形態で使用す る C oターゲット 1 0 3は、少なくとも C o純度が 9 9 . 9 9 %以上で、 F eまた は N iの含有量が ]. 0 p p m以下、 あるいは F eおよび N iの含有量が 5 0 p p m以下である。 より好ましくは、 C o純度が 9 9 . 9 9 %以上で、 F eおよび N i の含有量が 1 0 p p m以下のもの、さらに好ましくは C o純度が 9 9 . 9 9 9 %の ものを使用する。 このような高純度の C oターゲット 1 0 3は、 電解法などを用 いて上記の C o純度が得られるまで精製した原料 C o粉末をホットプレスにより 焼結体とし、 これを例えば円盤状に機械加ェすることにより製造する。  FIG. 10 is a schematic view of a chamber of a sputtering apparatus used for depositing the Co film 16. The inside of the chamber 100 is evacuated to a vacuum. During film formation, Ar gas is introduced and the pressure is maintained at about several mTorr. Above the holder 101 on which the semiconductor substrate 1 (wafer) is placed, a Co target 1.03 held by a sputter electrode 102 is arranged to face the semiconductor substrate 1. When the sputter power supply 104 connected to the Co target 103 is activated to start a steady discharge, the negative high voltage applied to the Co target 103 causes the C Plasma 105 is formed in the gap between 3 and semiconductor substrate 1. When Ar ions accelerated from the plasma 105 toward the Co target 103 bombard the surface of the Co target 103, the target constituent material (Co) is at the molecular (atomic) level. And the Co film 16 is deposited on the surface of the semiconductor substrate 1. FIG. 11 is a perspective view of the C 0 target 103. The Co target 103 used in the present embodiment has a Co purity of at least 99.9% or more and a Fe or Ni content of] .0 ppm or less, or Fe and Ni. Ni content is 50 ppm or less. More preferably, those having a Co purity of 99.9% or more and Fe and Ni contents of 10 ppm or less, more preferably those having a Co purity of 99.999%. use. Such a high-purity Co target 103 is prepared by sintering the raw material Co powder, which has been refined by using an electrolysis method or the like until the above-mentioned Co purity is obtained, by hot pressing, for example, into a disk shape. Manufactured by mechanical processing.

次に、 図 1 2に示すように、 C oと S i とを反応させるための第 1の熱処理を 行うことにより、 p +型半導体領域 1 3、 n +型半導体領域 14、 ゲート電極 8 n、 8 Pのそれぞれの表面に C o S i層 16 aを形成する。第 1の熱処理は、 R T A (R apid Thermal Anneal)装置を用い、 窒素雰囲気中、 基板温度を 525 :C以下に設 定して 30秒程度行う。 ただし、 熱処理温度が低すぎるとシリサイド化反応の進 行が阻害されるため、 基板温度は少なくとも 475 以上に設定することが好ま しい。 Next, as shown in FIG. 12, a first heat treatment for reacting Co with Si is performed. As a result, a CoSi layer 16a is formed on each surface of the p + type semiconductor region 13, the n + type semiconductor region 14, and the gate electrodes 8n, 8P. The first heat treatment is performed for about 30 seconds in a nitrogen atmosphere at a substrate temperature of 525: C or lower using a rapid thermal annealing (RTA) apparatus. However, if the heat treatment temperature is too low, the progress of the silicidation reaction is hindered, so the substrate temperature is preferably set to at least 475 or more.

次に、 NH 4OH + H 202水溶液、続いて HC 1 + H 2◦ 2水溶液を用いたゥェ ットエッチングによって、 酸化防止膜 1 7および未反応の C o膜 16を除去した 後、 図 1 3に示すように、 第 2の熱処理を行うことにより、 C o S i層 16 aを C o S i 2層 1 6 bに相転移させる。 第 2の熱処理は、 RTA装置を用い、 窒素 雰囲気中、 基板温度を 650〜800 Cに設定して .1分程度行う。 Then, NH 4 OH + H 2 0 2 solution, followed by © E Tsu bets etching using HC 1 + H 2 ◦ 2 aqueous solution, after removal of the C o film 16 of barrier layer 1 7 and unreacted oxide, FIG. As shown in 13, by performing the second heat treatment, the CoSi layer 16 a undergoes a phase transition to the CoSi 2 layer 16 b. The second heat treatment is performed in a nitrogen atmosphere at a substrate temperature of 650 to 800 C for about 0.1 minute using an RTA apparatus.

図 14は、 ゲート電極、 ソースおよびドレインのそれぞれの表面に C o S i 2 層 16 bを形成した nチヤネル型 M O S F E Tおよび pチヤネル型 M O S F E T の拡大図、 図 1 5は、 C o S i 2層 1 6 bのシート抵抗と第 ]の熱処理温度との 関係を示すグラフである。 C oターゲットは、 C o純度が 99. 998%の高純度 品 （ターゲット B) と、 99.9%の低純度品 （ターゲット A) とを使用した。 タ ーゲット八、 Bに含まれる不純物種とその含有量を表 1に示す。 表 1 (単位：重量 pm 14, the gate electrode, C o S i 2 layer 16 n channel-type was formed b MOSFET and enlarged view of a p-channel type MOSFET to the respective surfaces of the source and drain, 1 5, C o S i 2 layers 16 is a graph showing the relationship between the sheet resistance of 16b and the first heat treatment temperature. As the Co target, a high-purity product (target B) having a Co purity of 99.998% and a low-purity product (target A) having a 99.9% purity were used. Table 1 shows the impurity species and their contents in Targets 8 and B. Table 1 (Unit: Weight pm

Figure imgf000015_0001
図示のように、純度 99. 998%の高純度ターゲット Bから得られた C o S i ;層 1 6 bは、 C o S i層 16 aの第 1熱処理温度依存性が小さく、 500〜 60 の温度範囲でほぼ均一になるために、 この温度範囲全域で約 4 Ω /口前後の 低いシート抵抗が得られた。
Figure imgf000015_0001
As shown in the figure, the CoSi; layer 16b obtained from the high-purity target B having a purity of 99.998% has a small first heat treatment temperature dependence of the CoSi layer 16a, Since the temperature becomes almost uniform in this temperature range, a low sheet resistance of about 4 Ω / port was obtained throughout this temperature range.

これにより、 第 1熱処理温度を低く設定してもシート抵抗の低い C o S i 2層 1 6 bが得られた。 また、 熱処理温度の低温化によってシリサイ ド化反応の速度 が小さくなり、 熱処理時間による膜厚制御性が向上するために、 C o S i 2層 1 6 bの膜厚を接合リーク電流が増加しない範囲に設定することが容易になった。 さらに、 熱処理温度の低温化によって、 C o S i 2層]. 6 bのはい上がりを防止 することができた。 As a result, a Co Si 2 layer 16b having a low sheet resistance was obtained even when the first heat treatment temperature was set low. In addition, the lowering of the heat treatment temperature decreases the speed of the silicidation reaction and improves the controllability of the film thickness by the heat treatment time, so that the junction leakage current does not increase in the thickness of the CoSi 2 layer 16b. It became easy to set the range. Furthermore, by lowering the heat treatment temperature, the rise of the Co Si 2 layer]. 6b could be prevented.

他方、 純度 9 9 . 9 %のターゲット Aから得られた C o S i 2層は、 熱処理温度 が低いときには C o膜の膜厚が薄くなるためにシート抵抗が著しく増大した。 ま た、 高純度ターゲット Bから得られた C o S i 2層と同等のシート抵抗を得るた めには、 第 1熱処理温度を 6 0 O 'Cまで高くしなければならなかった。 On the other hand, when the heat treatment temperature was low, the sheet resistance of the CoSi 2 layer obtained from the target A having a purity of 99.9% was significantly increased because the thickness of the Co film was small. Further, in order to obtain the same sheet resistance as the CoSi 2 layer obtained from the high-purity target B, the first heat treatment temperature had to be increased to 60 O'C.

このように、 スパッタリング法で堆積した C o膜をシリサイド化して、 MO S F E Tのゲート電極、 ソースおよびドレインのそれぞれの表面に C o S i 2層を 形成するに際し、 C o純度が 9 9 . 9 9 %以上で、 F eおよび N iの含有量が 1 0 p p m以下、より好ましくは C o純度が 9 9 . 9 9 9 %の高純度 C oターゲットを 用いる本実施の形態によれば、 低抵抗で接合リーク電流の少ない C oシリサイド 層 1 6 bが得られるので、ゲート長が 0. 2 5 μ mの微細な CMO S F E Tを使つ たデバイスの高速化、 高性能化、 低消費電力化を推進することができる。 Thus, when the Co film deposited by the sputtering method is silicided to form a CoSi 2 layer on each of the surface of the gate electrode, the source and the drain of the MOS FET, the purity of the Co is 99.9. According to the present embodiment using a high-purity Co target with a content of Fe and Ni of 10 ppm or less, more preferably a Co purity of 99.999%, the content of Fe and Ni is 9% or more. Since a Co silicide layer 16b with low junction leakage current can be obtained with a resistor, high-speed, high-performance, and low-power consumption devices using a fine CMO SFET with a gate length of 0.25 μm can be obtained. Can be promoted.

次に、 図 1 6に示すように、 半導体基板 1上に常圧 C V D法で膜厚 1 0 0 nm の酸化シリコン膜 1 8を堆積し、 さらにプラズマ C V D法で膜厚 3 0 0〜 5 0 0 nmの酸化シリコン膜 1 9を堆積した後、化学的機械研磨（Chemical Mechanical P olishing ; CM P ) 法で酸化シリコン膜]. 9を研磨してその表面を平坦化する。 続いて、 モノシラン +酸素 +フォスフィンをソースガスに用いた C V D法で酸化 シリコン膜 1 9上に膜厚 2 0 0 nmの P S G膜 2 0を堆積した後、 P S G膜 2 0中 の水分を除去するための熱処理 （シンタリング） を 7 0 0〜8 0 0 °Cの温度範囲 で行う。 本実施の形態では、 C o S i 2層 1 6 bの膜厚を十分に確保することが できるので、 高温のシンタリングを行った場合でも C o S i 2層 1 6 bの凝集が 抑制されるので、 C o S i 2層 1 6 bのシート抵抗の増大を防止できると共に、 プロセスマージンを向上できる。 Next, as shown in FIG. 16, a 100-nm-thick silicon oxide film 18 is deposited on the semiconductor substrate 1 by a normal pressure CVD method, and then a thickness of 300 to 50 nm is formed by a plasma CVD method. After a 0-nm silicon oxide film 19 is deposited, the silicon oxide film] .9 is polished by a chemical mechanical polishing (CMP) method to flatten the surface. Subsequently, after depositing a 200 nm-thick PSG film 20 on the silicon oxide film 19 by a CVD method using monosilane + oxygen + phosphine as a source gas, the water in the PSG film 20 is removed. Heat treatment (sintering) is performed in the temperature range of 700 to 800 ° C. In the present embodiment, since the film thickness of the CoSi 2 layer 16b can be sufficiently ensured, the aggregation of the CoSi 2 layer 16b is suppressed even when high-temperature sintering is performed. Therefore, it is possible to prevent an increase in the sheet resistance of the Co Si 2 layer 16 b, and Process margin can be improved.

次に、 図 1. 7に示すように、 フォトレジス トをマスクにして P S G膜 2 0、 酸 化シリコン膜 1 9、 .1 8をエッチングすることにより、 p ÷型半導体領域 1 3およ び 型半導体領域 1 4のそれぞれの上部に接続孔 2 1を形成した後、 P S G膜 2 0の上部に第 1層配線 2 2を形成する。 第 1層配線 2 2を形成するには、 P S G 膜 2 0の上部に C V D法で第 1の T i N膜を薄く堆積し、 その上部に W膜を厚く 堆積した後、 W膜をエッチバックして接続孔 2 1.の内部に残す。 続いて、 第 1の T i N膜上にスパッタリング法で A 1膜および第 2の T i N膜を堆積した後、 フ ォトレジストをマスクにして第 2の T i N膜、 A 1膜および第 1の T i N膜をバ ターニングする。 . Next, FIG. 1. As shown in 7, PSG film 2 0 by a photo registry to mask, oxidation silicon film 1 9, by etching the .1 8, p ÷ type semiconductor region 1 3 and After forming a connection hole 21 on each of the type semiconductor regions 14, a first layer wiring 22 is formed on the PSG film 20. To form the first layer wiring 22, a thin first TiN film is deposited on top of the PSG film 20 by CVD, a thick W film is deposited on top of it, and the W film is etched back. And leave it inside the connection hole 2 1. Subsequently, after depositing an A1 film and a second TN film on the first TN film by a sputtering method, the second TN film, the A1 film and the second film are formed using a photoresist as a mask. Pattern 1 TiN film. .

次に、 図 1 8に示すように、 第 1層配線 2 2の上部に第 1層間絶縁膜 2 3を形 成し、 化学的機械研磨法でその表面を平坦化した後、 第 1層間絶縁膜 2 3に接続 孔 2 4を形成する。 続いて、 第 1層間絶縁膜 2 3の上部に第 2層配線 2 5を形成 することにより、 第 2層配線 2 5と第 1層配線 2 2とを電気的に接続する。 第 1 層間絶縁膜 2 3は、 プラズマ C V D法で堆積した酸化シリコン膜で構成し、 第 2 層配線 2 5は、 第 1層配線 2 2と同じ材料で構成する。  Next, as shown in FIG. 18, a first interlayer insulating film 23 is formed on the first layer wiring 22 and the surface thereof is planarized by a chemical mechanical polishing method. A connection hole 24 is formed in the film 23. Subsequently, a second-layer wiring 25 is formed on the first interlayer insulating film 23, so that the second-layer wiring 25 and the first-layer wiring 22 are electrically connected. The first interlayer insulating film 23 is made of a silicon oxide film deposited by a plasma CVD method, and the second layer wiring 25 is made of the same material as the first layer wiring 22.

次に、 図 1 9に示すように、 上記と同様にして第 2層配線 2 5の上部に第 2層 間絶縁膜 2 6を形成し、 表面の平坦ィヒおよび接続孔 2 7の形成を行った後、 第 2 層間絶縁膜 2 6の上部に第 3層配線 2 8を形成する。  Next, as shown in FIG. 19, a second inter-layer insulating film 26 is formed on the second layer wiring 25 in the same manner as described above, and the surface flatness and the connection holes 27 are formed. After that, a third-layer wiring 28 is formed on the second interlayer insulating film 26.

その後、 図 2 0に示すように、 第 3層配線 2 5の上部に第 3層間絶縁膜 2 9を 形成し、 表面の平坦化および接続孔 3 0の形成を行った後、 第 3層間絶縁膜 2 9 の上部に第 4層配線 3 1を形成し、 さらに第 4層配線 3 1の上部に第 4層間絶縁 膜 3 2を形成し、 表面の平坦化および接続孔 3 3の形成を行った後、 第 4層間絶 縁膜 3 2の上部に第 5層配線 3 4を形成することにより、 本実施の形態の半導体 集積回路装置がほぼ完成する。  Thereafter, as shown in FIG. 20, a third interlayer insulating film 29 is formed on the third layer wiring 25, and after the surface is flattened and the connection holes 30 are formed, the third interlayer insulating film 29 is formed. A fourth-layer wiring 31 is formed on the film 29, and a fourth interlayer insulating film 32 is formed on the fourth-layer wiring 31. The surface is flattened and the connection hole 33 is formed. After that, the fifth layer wiring 34 is formed on the fourth interlayer insulating film 32, whereby the semiconductor integrated circuit device of the present embodiment is almost completed.

以上、 本発明者によってなされた発明を実施の形態に基づき具体的に説明した 力 本発明は前記実施の形態に限定されるものではなく、 その要旨を逸脱しない 範囲で種々変更可能であることはいうまでもない。  As described above, the invention made by the inventor has been specifically described based on the embodiments. The present invention is not limited to the above-described embodiments, and may be variously modified without departing from the gist thereof. Needless to say.

高純度 C oターゲットを使用する本発明の製造方法は、 例えば M〇 S F E Tの ソース、 ドレインの表面のみを C oシリサイド化する場合にも適用することがで さる。 産業上の利用可能性 The manufacturing method of the present invention using a high-purity Co target is, for example, an M〇SFET. It can be applied to the case where only the source and drain surfaces are to be silicified with Co. Industrial applicability

以上のように、 本発明の半導体集積回路装置の製造方法によれば、 C oシリサ イド層の膜厚制御性が向上し、 低抵抗で、 かつ接合リーク電流の少ない C oシリ サイド層が得られるので、 C oターゲットを用いたサリサイドプロセスに適用し て好適なものである。  As described above, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, the controllability of the thickness of the Co silicide layer is improved, and a Co silicide layer having low resistance and low junction leakage current is obtained. Therefore, it is suitable to be applied to a salicide process using a Co target.

Claims

請 求 の 範 囲 The scope of the claims 1. 以下の工程を含むことを特徴とする半導体集積回路装置の製造方法； (a) ウェハの主面に MO S FETを形成する工程、 1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a MOS FET on a main surface of a wafer; (b) 高純度の C oターゲットを用いたスパッタリング法によって、 前記ウェハ の主面上の少なくとも前記 MOS FETのゲート電極、 ソースおよびドレインの それぞれの上部を含む領域に C o膜を堆積する工程、  (b) depositing a Co film on a main surface of the wafer by sputtering using a high-purity Co target at least in a region including an upper portion of each of a gate electrode and a source and a drain of the MOS FET; (c)前記ウェハに第 1の熱処理を施して C oと S i とを反応させることにより、 前記 MO S F E Tのゲート電極、 ソースおよびドレインのそれぞれの表面に C o シリサイド層を形成する工程、  (c) performing a first heat treatment on the wafer to cause Co and Si to react, thereby forming a Co silicide layer on each surface of the gate electrode, source, and drain of the MOS FET. (d) 前記 C o膜の未反応部分を除去した後、 前記ウェハに第 2の熱処理を施し て前記 C oシリサイド層を低抵抗化する工程。  (d) a step of performing a second heat treatment on the wafer after removing an unreacted portion of the Co film to lower the resistance of the Co silicide layer. 2. 請求項 1記載の半導体集積回路装置の製造方法であって、 前記 C oターゲッ トの C o純度は 99. 99 %以上であり、 F eまたは N iの含有量は 1 0 p p m以 下であることを特徴とする半導体集積回路装置の製造方法。  2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the Co target has a Co purity of 99.99% or more, and a Fe or Ni content of 10 ppm or less. A method of manufacturing a semiconductor integrated circuit device. 3. 請求項 1記載の半導体集積回路装置の製造方法であって、 前記 Coターゲッ トの C o純度は 99.99 %以上であり、 F eおよび N iの含有量は 50 p p m以 下であることを特徴とする半導体集積回路装置の製造方法。  3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the Co target has a Co purity of 99.99% or more and Fe and Ni contents of 50 ppm or less. A method for manufacturing a semiconductor integrated circuit device. 4. 請求項 1記載の半導体集積回路装置の製造方法であって、 前記 C oターゲッ トの C o純度は 99.99 %以上であり、 F eおよび N iの含有量は 10 p p m以 下であることを特徴とする半導体集積回路装置の製造方法。 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the Co target has a Co purity of 99.99% or more and Fe and Ni contents of 10 ppm or less. A method for manufacturing a semiconductor integrated circuit device, comprising: 5. 請求項 1記載の半導体集積回路装置の製造方法であって、 前記 Coターゲッ トの C o純度は、 99. 999%であることを特徴とする半導体集積回路装置の製 造方法。  5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the Co target has a Co purity of 99.999%. 6. 請求項 1記載の半導体集積回路装置の製造方法であって、 前記第 1の熱処理 の温度は、 475°C〜525 Cであることを特徴とする半導体集積回路装置の製 造方法。  6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the temperature of the first heat treatment is 475 ° C. to 525 ° C. 7. 請求項 1記載の半導体集積回路装置の製造方法であって、 前記第 2の熱処理 の温度は、 65 Ot：〜 800eCであることを特徴とする半導体集積回路装置の製 造方法。 7. A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the temperature of the second heat treatment is, 65 Ot: manufacturing the semiconductor integrated circuit device which is a ~ 800 e C Construction method. 8 . 請求項 1記載の半導体集積回路装置の製造方法であって、 前記 C o膜の膜厚 は、 1 8〜 6 0 nmであることを特徴とする半導体集積回路装置の製造方法,:. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the thickness of the Co film is 18 to 60 nm. 9 . 請求項 1記載の半導体集積回路装置の製造方法であって、 前記第 2の熱処理 を施した後の前記 C oシリサイ ド層のシート抵抗は、 1 0 Ω Ζ口以下であること を特徴とする半導体集積回路装置の製造方法。 9. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein a sheet resistance of the Co silicide layer after performing the second heat treatment is equal to or less than 10 Ω square. Of manufacturing a semiconductor integrated circuit device. 1 0 . 請求項 1記載の半導体集積回路装置の製造方法であって、 前記ソース、 ド レインの接合深さは、 0. 3 μ m以下であることを特徴とする半導体集積回路装置 の製造方法。  10. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein a junction depth of the source and the drain is 0.3 μm or less. . 1 1 . 以下の工程を含むことを特徴とする半導体集積回路装置の製造方法； 11. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps: ( a ) ゲート絶縁膜を形成したウェハの主面上に多結晶シリコン膜および第 1絶 縁膜を堆積した後、 前記第 1絶縁膜および前記多結晶シリコン膜をバターニング することにより、 前記ウェハの第 1領域に第 1ゲート電極パターンを形成し、 第 2領域に第 2ゲート電極バターンを形成する工程、 (a) depositing a polycrystalline silicon film and a first insulating film on a main surface of a wafer on which a gate insulating film is formed, and then patterning the first insulating film and the polycrystalline silicon film to form the wafer; Forming a first gate electrode pattern in a first region of the first region, and forming a second gate electrode pattern in a second region of the first region; ( b ) 前記ウェハの第】領域に第 1導電型の不純物をイオン打ち込みして、 前記 第 1ゲート電極パターンの両側の前記ウェハに低不純物濃度の第 1導電型半導体 領域を形成し、 前記ウェハの第 2領域に第 2導電型の不純物をイオン打ち込みし て、 前記第 2ゲート電極パターンの両側の前記ウェハに低不純物濃度の第 2導電 型半導体領域を形成する工程、  (b) ion-implanting a first conductivity type impurity into the first region of the wafer to form a low impurity concentration first conductivity type semiconductor region on the wafer on both sides of the first gate electrode pattern; Ion-implanting a second conductivity type impurity into the second region to form a low impurity concentration second conductivity type semiconductor region on the wafer on both sides of the second gate electrode pattern; ( c ) 前記ウェハの主面上に堆積した第 2絶縁膜をパターニングして、 前記第 1 およぴ第 2ゲート電極パターンのそれぞれの側壁にサイドウォールスべ一サを形 成すると共に、 前記第 1および第 2ゲート電極パターンのそれぞれの前記第 1絶 縁膜を除去することにより、 前記多結晶シリコン膜の表面を露出させる工程、 ( d ) 前記ウェハの第 1領域に第 1導電型の不純物をイオン打ち込みして、 前記 第 1ゲート電極パターンの前記多結晶シリコン膜で第 1導電型の第 1ゲート電極 を形成すると共に、 前記第 1ゲート電極の両側の前記ウェハに高不純物濃度の第 1導電型半導体領域を形成し、 前記ウェハの第 2領域に第 2導電型の不純物をィ オン打ち込みして、 前記第 2ゲート電極パターンの前記多結晶シリコン膜で第 2 導電型の第 2ゲート電極を形成すると共に、 前記第 2ゲート電極の両側の前記ゥ 二高不純物濃度の第 2導電型半導体領域を形成する工程、 (c) patterning a second insulating film deposited on the main surface of the wafer to form sidewall spacers on respective side walls of the first and second gate electrode patterns; Exposing the surface of the polycrystalline silicon film by removing the first insulating film of each of the first and second gate electrode patterns; (d) forming a first conductive type on the first region of the wafer; An impurity is ion-implanted to form a first gate electrode of a first conductivity type with the polycrystalline silicon film of the first gate electrode pattern, and a high impurity concentration first gate electrode is formed on both sides of the first gate electrode. A first conductivity type semiconductor region is formed, and a second conductivity type impurity is ion implanted into a second region of the wafer, and a second conductivity type second gate is formed by the polycrystalline silicon film of the second gate electrode pattern. Shape electrode While, the © of both sides of the second gate electrode Forming a second conductivity type semiconductor region having a high impurity concentration, (e) 高純度の C oターゲットを用いたスパッタリング法によって、 前記ゥ- の主面上に C. o膜を堆積する工程、  (e) a step of depositing a C.o film on the main surface of ゥ-by a sputtering method using a high-purity Co target, (Π前記ウェハに第 1の熱処理を施して Coと S i とを反応させる二とにより、 前記第 1および第 2ゲート電極の表面と、 前記高不純物濃度の第 1および第 2導 電型半導体領域の表面とに C oシリサイ ド層を形成する工程、  (ΠBy subjecting the wafer to a first heat treatment to react Co and Si with each other, the surface of the first and second gate electrodes and the first and second conductive semiconductors having a high impurity concentration Forming a Co silicide layer with the surface of the region, (g) 前記 Co膜の未反応部分を除去した後、 前記ウェハに第 2の熱処理を施し て前記 C oシリサイド層を低抵抗化する工程。  (g) a step of performing a second heat treatment on the wafer after removing an unreacted portion of the Co film to lower the resistance of the Co silicide layer. 1 2. 請求項 1 1記載の半導体集積回路装置の製造方法であって、 前記 MOSF E Tの動作電源電圧は、 2 V以下であることを特徴とする半導体集積回路装置の 製造方法。  12. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein an operating power supply voltage of the MOSFET is 2 V or less. 1 3. 請求項 1 1記載の半導体集積回路装置の製造方法であって、 前記 C oター ゲッ トの C o純度は 99.99 %以上であり、 F eまたは N iの含有量は 10 p p m以下であることを特徴とする半導体集積回路装置の製造方法。  13. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the Co target has a Co purity of 99.99% or more, and a Fe or Ni content of 10 ppm or less. A method for manufacturing a semiconductor integrated circuit device. 14. 請求項 1 1記載の半導体集積回路装置の製造方法であって、 前記 C oター ゲットの C o純度は 99. 99 %以上であり、 F eおよび N iの含有量は 50 p p m以下であることを特徴とする半導体集積回路装置の製造方法。  14. The method for manufacturing a semiconductor integrated circuit device according to claim 11, wherein the Co target has a Co purity of 99.99% or more and Fe and Ni contents of 50 ppm or less. A method for manufacturing a semiconductor integrated circuit device. 1 5. 請求項 1 1記載の半導体集積回路装置の製造方法であって、 前記 C oター ゲットの C o純度は 99.99 %以上であり、 F eおよび N iの含有量は 10 p p m以下であることを特徴とする半導体集積回路装置の製造方法。  1 5. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the Co target has a Co purity of 99.99% or more, and a content of Fe and Ni is 10 ppm or less. A method for manufacturing a semiconductor integrated circuit device. 1 6. 請求項 1 1記載の半導体集積回路装置の製造方法であって、 前記 C oター ゲットの C 0純度は、 99.999%であることを特徴とする半導体集積回路装置 の製造方法。  16. The method for manufacturing a semiconductor integrated circuit device according to claim 11, wherein the Co target has a C0 purity of 99.999%. 1 7. 以下の工程を含むことを特徴とする半導体集積回路装置の製造方法； (a ) ウェハの主面に M〇S FETを形成した後、 前記 MO S F E Tのゲート電 極、 ソースおよびドレインのそれぞれの表面を露出させる工程、  1 7. A method of manufacturing a semiconductor integrated circuit device, comprising the following steps; (a) forming an M〇S FET on a main surface of a wafer, and then forming a gate electrode, a source, and a drain of the MOS FET; The process of exposing each surface, (b) 高純度の C oターゲットを用いたスパッタリング法によって、 前記 MOS FETのグート電極、 ソースおよびドレインのそれぞれの表面を含む前記ウェハ の主面上に C o膜を堆積する工程、 ( c )前記ウェハに第 1の熱処理を施して C oと S i とを反応させることにより、 前記 MO S F ETのゲート電極、 ソースおよびドレインのそれぞれの表面に、 主 として Coモノシリサイ ドからなる Coシリサイド層を形成する工程、 (b) depositing a Co film on the main surface of the wafer including the respective surfaces of the good electrode, source and drain of the MOS FET by a sputtering method using a high-purity Co target; ( c ) By subjecting the wafer to a first heat treatment to cause Co and Si to react with each other, the surface of the gate electrode, the source and the drain of the MOSFET is made of Co mainly composed of Co monosilicide. Forming a silicide layer, (d) 前記 Co膜の未反応部分を除去した後、 第 2の熱処理を施して前記 Coシ リサイド層を主として C oジシリサイドからなる C oシリサイド層に相転移させ る工程、  (d) after removing the unreacted portion of the Co film, performing a second heat treatment to phase-transform the Co silicide layer into a Co silicide layer mainly composed of Co disilicide; (e) 前記 MO S FETの上部に金属不純物をゲッタリングするための不純物を をドープした酸化シリコン膜を堆積した後、 前記酸化シリコン膜に第 3の熱処理 を施す工程。  (e) depositing a silicon oxide film doped with an impurity for gettering metal impurities on the MOS FET, and then subjecting the silicon oxide film to a third heat treatment. 1 8. 請求項 1 7記載の半導体集積回路装置の製造方法であって、 前記不純物を ドープした酸化シリコン膜は、 PSG膜であることを特徴とする半導体集積回路 装置の製造方法。  18. The method for manufacturing a semiconductor integrated circuit device according to claim 17, wherein the silicon oxide film doped with the impurity is a PSG film. 1 . 請求項 1 7記載の半導体集積回路装置の製造方法であって、 前記第 3の熱 処理の温度は、 700 °C〜 800 °Cであることを特徴とする半導体集積回路装置 の製造方法。  18. The method for manufacturing a semiconductor integrated circuit device according to claim 17, wherein a temperature of the third heat treatment is 700 ° C. to 800 ° C. .
PCT/JP1997/000810 1997-03-14 1997-03-14 Process for producing semiconductor integrated circuit device Ceased WO1998042009A1 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
KR10-2004-7007841A KR20040053359A (en) 1997-03-14 1997-03-14 Process for producing semiconductor integrated circuit device
PCT/JP1997/000810 WO1998042009A1 (en) 1997-03-14 1997-03-14 Process for producing semiconductor integrated circuit device
US09/380,735 US6693001B2 (en) 1997-03-14 1997-03-14 Process for producing semiconductor integrated circuit device
CNB971820252A CN1146959C (en) 1997-03-14 1997-03-14 Method for manufacturing semiconductor integrated circuit device
KR1019997008290A KR100563503B1 (en) 1997-03-14 1997-03-14 Manufacturing Method of Semiconductor Integrated Circuit Device
AU19405/97A AU1940597A (en) 1997-03-14 1997-03-14 Process for producing semiconductor integrated circuit device
US11/006,702 US7214577B2 (en) 1997-03-14 2004-12-08 Method of fabricating semiconductor integrated circuit device
US11/783,187 US7314830B2 (en) 1997-03-14 2007-04-06 Method of fabricating semiconductor integrated circuit device with 99.99 wt% cobalt
US11/950,152 US7553766B2 (en) 1997-03-14 2007-12-04 Method of fabricating semiconductor integrated circuit device
US12/492,276 US8034715B2 (en) 1997-03-14 2009-06-26 Method of fabricating semiconductor integrated circuit device

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PCT/JP1997/000810 WO1998042009A1 (en) 1997-03-14 1997-03-14 Process for producing semiconductor integrated circuit device
CNB971820252A CN1146959C (en) 1997-03-14 1997-03-14 Method for manufacturing semiconductor integrated circuit device

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US10/721,902 Continuation US6858484B2 (en) 1997-03-14 2003-11-26 Method of fabricating semiconductor integrated circuit device

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JPH073486A (en) * 1993-06-15 1995-01-06 Japan Energy Corp High-purity cobalt and method for producing the same
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JP2002043564A (en) * 2000-07-21 2002-02-08 Mitsubishi Electric Corp Method of manufacturing salicide transistor, semiconductor memory device and semiconductor device
US7078758B2 (en) 2003-02-21 2006-07-18 Renesas Technology Corp. Semiconductor device having memory and logic devices with reduced resistance and leakage current
US7329575B2 (en) 2003-02-21 2008-02-12 Renesas Technology Corp. Semiconductor device and semiconductor device manufacturing method
US7919799B2 (en) 2003-02-21 2011-04-05 Renesas Electronics Corporation Semiconductor device and semiconductor device manufacturing method
US8058679B2 (en) 2003-02-21 2011-11-15 Renesas Electronics Corporation Semiconductor device and semiconductor device manufacturing method
US8492813B2 (en) 2003-02-21 2013-07-23 Renesas Electronics Corporation Semiconductor device and semiconductor device manufacturing method
US8647944B2 (en) 2003-02-21 2014-02-11 Renesas Electronics Corporation Semiconductor device and semiconductor device manufacturing method

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