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WO1997039591A1 - Dispositif de stockage en memoire d'informations desentrelacees - Google Patents

Dispositif de stockage en memoire d'informations desentrelacees Download PDF

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Publication number
WO1997039591A1
WO1997039591A1 PCT/US1997/004759 US9704759W WO9739591A1 WO 1997039591 A1 WO1997039591 A1 WO 1997039591A1 US 9704759 W US9704759 W US 9704759W WO 9739591 A1 WO9739591 A1 WO 9739591A1
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WIPO (PCT)
Prior art keywords
codeword
memory
message
selective call
coupled
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PCT/US1997/004759
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English (en)
Inventor
Paul H. Kelley
Oscar Vela
Mark Servilio
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Motorola Solutions Inc
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Motorola Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/02—Terminal devices
    • H04W88/022—Selective call receivers
    • H04W88/025—Selective call decoders
    • H04W88/026—Selective call decoders using digital address codes

Definitions

  • This invention relates in general to selective call receivers, and more particularly to a memory and time efficient device for use in conjunction with a selective call receiver, to store received, de-interleaved selective call messaging codewords .
  • a state of the art paging system might use the FLEXTM protocol, a high speed selective call signaling protocol by Motorola, Inc., to convey messages from an originator to a destination device, such as a conventional paging receiver or the like.
  • FLEXTM protocol a high speed selective call signaling protocol by Motorola, Inc.
  • a destination device such as a conventional paging receiver or the like.
  • conventional design methodologies to implement the conventional paging receiver mentioned above, the demands of high speed operation will significantly shorten battery life and increase the product cost due to higher circuit operating speed and complexity requirements. Consequently, alternative means must be developed to accommodate the next generation of high speed signaling devices, while meeting both performance and cost goals.
  • ASICs application specific integrated circuits
  • custom integrated circuits as hardware decoders
  • an information storage device that includes a memory for storing a codeword recovered from a plurality of de-interleaved information blocks.
  • the codeword is stored in a first memory region within the memory.
  • a codeword identifier examines the codeword and assigns a corresponding type identifier to the codeword.
  • a memory controller then stores the type identifier in a second memory region within the memory corresponding with the codeword.
  • FIG. 1 is an electrical block diagram of a data transmission system for use in accordance with the preferred embodiment of the present invention.
  • FIG. 2 is an electrical block diagram of a terminal for processing and transmitting message information in accordance with the preferred embodiment of the present invention.
  • FIGS. 3-5 are timing diagrams illustrating the transmission format of the signaling protocol utilized in accordance with the preferred embodiment of the present invention.
  • FIGS. 6 and 7 are timing diagrams illustrating the synchronization signals utilized in accordance with the preferred embodiment of the present invention.
  • FIG. 8 is an electrical block diagram of a selective call receiver in accordance with the preferred embodiment of the present invention.
  • FIG. 9 is a memory register diagram of a non-optimal four phase structure for storing non-optimal type identifiers associated with address, control and data codewords.
  • FIG. 10 is a memory register diagram of a single phase in a four phase structure, illustrating the preferred embodiment for storing one bit type identifiers denoting codewords belonging to the vector field and the message field in a first region within the memory.
  • FIG. 11 is a memory register diagram of FIG. 10, illustrating the unique offset relationship between vector codewords and address codewords maintained in the preferred embodiment of the present invention.
  • FIG. 12 shows the first memory register diagram from FIG. 10, and a second memory register diagram showing storage of a first bit of a type identifier denoting codewords belonging to the vector field in a first region within the memory and storage of a second bit of the type identifier in second memory region within the memory corresponding with the codeword.
  • FIG. 13 shows an organization structure for an optimally configured memory for use in the de-interleaved information memory storage device in accordance with the preferred embodiment of the present invention. Description of a Preferred Embodiment
  • an electrical block diagram illustrates a data transmission system 100, such as a paging system, for use in accordance with the preferred embodiment of the present invention.
  • a data transmission system 100 messages originating either from a phone, as in a system providing numeric data transmission, or from a message entry device, such as an alphanumeric data terminal, are routed through the public switched telephone network (PSTN) to a paging terminal 102 which processes the numeric or alphanumeric message information for transmission by one or more transmitters 104 provided within the system.
  • PSTN public switched telephone network
  • the transmitters 104 preferably simulcast transmit the message information to selective call receivers 106.
  • an electrical block diagram illustrates the paging terminal 102 utilized for processing and controlling the transmission of the message information in accordance with the preferred embodiment of the present invention.
  • Short messages such as tone-only and numeric messages which can be readily entered using a Touch-ToneTM telephone are coupled to the paging terminal 102 through a telephone interface 202 in a manner well known in the art.
  • Longer messages such as alphanumeric messages which require the use of a data entry device are coupled to the paging terminal 102 through a modem 206 using any of a number of well known modem transmission protocols .
  • a controller 204 handles the processing of the message.
  • the controller 204 is preferably a microcomputer, such as a MC680xO or equivalent, which is manufactured by Motorola Inc., and which runs various pre ⁇ programmed routines for controlling such terminal operations as voice prompts to direct the caller to enter the message, or the handshaking protocol to enable reception of messages from a data entry device.
  • the controller 204 references information stored in the subscriber database 208 to determine how the message being received is to be processed.
  • the subscriber data base 208 includes, but is not limited to such information as addresses assigned to the selective call receiver, message type associated with the address, and information related to the status of the selective call receiver, such as active or inactive for failure to pay the bill.
  • a data entry terminal 240 is provided which couples to the controller 204, and which is used for such purposes as entry, updating and deleting of information stored in the subscriber data base 208, for monitoring system performance, and for obtaining such information as billing information.
  • the subscriber database 208 also includes such information as to what transmission frame and to what transmission phase the selective call receiver is assigned, as will be described in further detail below.
  • the received message is stored in an active page file 210 which stores the messages in queues according to the transmission phase assigned to the selective call receiver.
  • four phase queues are provided in the active page file 210.
  • the active page file 210 is preferably a dual port, first in first out random access memory, although it will be appreciated that other random access memory devices, such as hard disk drives, can be utilized as well.
  • Periodically the message information stored in each of the phase queues is recovered from the active page file 210 under control of controller 204 using timing information such as provided by a real time clock 214, or other suitable timing source.
  • the recovered message information from each phase queue is sorted by frame number and is then organized by address, message information, and any other information required for transmission (all of which is referred to as message related information), and then batched into frames based upon message size by frame batching controller 212.
  • the batched frame information for each phase queue is coupled to frame message buffers 216 which temporarily store the batched frame information until a time for further processing and transmission. Frames are batched in numeric sequence, so that while a current frame is being transmitted, the next frame to be transmitted is in the frame message buffer 216, and the next frame thereafter is being retrieved and batched. At the appropriate time, the batched frame information stored in the frame message buffer 216 is transferred to the frame encoder 218, again maintaining the phase queue relationship.
  • the frame encoder 218 encodes the address and message information into address and message codewords required for transmission, as will be described below.
  • the encoded address and message codewords are ordered into blocks and then coupled to a block interleaver 220 which interleaves preferably eight codewords at a time to form interleaved information blocks for transmission in a manner well known in the art.
  • the interleaved codewords contained in the interleaved information blocks produced by each block interleaver 220 are then serially transferred to a phase multiplexer 221, which multiplexes the message information on a bit by bit basis into a serial data stream by transmission phase.
  • the controller 204 next enables a frame sync generator 222 which generates the synchronization code which is transmitted at the start of each frame transmission.
  • the synchronization code is multiplexed with address and message information under the control of controller 204 by serial data splicer 224, and generates therefrom a message stream which is properly formatted for transmission.
  • the message stream is next coupled to a transmitter controller 226, which under the control of controller 204 transmits the message stream over a distribution channel 228.
  • the distribution channel 228 may be any of a number of well known distribution channel types, such as wire line, an RF or microwave distribution channel, or a satellite distribution link.
  • the distributed message stream is transferred to one or more transmitter stations 104, depending upon the size of the communication system.
  • the message stream is first transferred into a dual port buffer 230 which temporarily stores the message stream prior to transmission.
  • the message stream is recovered from the dual port buffer 230 and coupled to the input of preferably a 4-level FSK modulator 234.
  • the modulated message stream is then coupled to the transmitter 236 for transmission via antenna 238.
  • the timing diagrams illustrate the transmission format of the signaling protocol utilized in accordance with the preferred embodiment of the present invention.
  • the signaling protocol enables message transmission to selective call receivers, such as pagers, assigned to one or more of 128 frames which are labeled frame 0 through frame 127.
  • selective call receivers such as pagers
  • the actual number of frames provided within the signaling protocol can be greater or less than described above.
  • the greater the number of frames utilized the greater the battery life that may be provided to the selective call receivers operating within the system.
  • the fewer the number of frames utilized the more often messages can be queued and delivered to the selective call receivers assigned to any particular frame, thereby reducing the latency, or time required to deliver messages.
  • FIG. 128 frames which are labeled frame 0 through frame 127.
  • each block of message information comprises preferably eight address, control or data codewords which are labeled word 0 through word 7 for each phase. Consequently, each phase in a frame allows the transmission of up to eighty-eight address, control and data codewords.
  • the address, control and data codewords preferably comprise two sets, a set first relating to a vector field comprising a short address vector, a long address vector, a first message word, and a null word, and a second set relating to a message field comprising a message word and a null word.
  • the address, control, and data or message codewords are preferably 31,21 BCH codewords with an added thirty-second even parity bit which provides an extra bit of distance to the codeword set. It will be appreciated that other codewords, such as a 23,12 Golay codeword could be utilized as well. Unlike the well known POCSAG signaling protocol which provides address and data codewords which utilize the first codeword bit to define the codeword type, as either address or data, no such distinction is provided for the address and data codewords in the signaling protocol utilized with the preferred embodiment of the present invention. Rather, address and data codewords are defined by their position within the individual frames.
  • FIGS. 6 and 7 are timing diagrams illustrating the synchronization code utilized in accordance with the preferred embodiment of the present invention.
  • the synchronization code comprises preferably three parts, a first synchronization code (sync 1), a frame information codeword (frame info) and a second synchronization codeword (sync 2).
  • the first synchronization codeword comprises first and third portions, labeled bit sync 1 and BS1, which are alternating 1,0 bit patterns which provides bit synchronization, and second and fourth portions, labeled "A" and its complement “A bar", which provide frame synchronization.
  • the second and fourth portions are preferably single 32,21 BCH codewords which are predefined to provide high codeword correlation reliability, and which are also used to indicate the data bit rate at which addresses and messages are transmitted.
  • Table 1 defines the data bit rates which are used in conjunction with the signaling protocol.
  • the frame information codeword is preferably a single 32,21 BCH codeword which includes within the data portion a predetermined number of bits reserved to identify the frame number, such as 7 bits encoded to define frame number 0 to frame number 127.
  • the structure of the second synchronization code is preferably similar to that of the first synchronization code described above. However, unlike the first synchronization code which is preferably transmitted at a fixed data symbol rate, such as 1600 bps (bits per second), the second synchronization code is transmitted at the data symbol rate at which the address and messages are to be transmitted in any given frame.
  • the second synchronization code allows the selective call receiver to obtain ⁇ V fine" bit and frame synchronization at the frame transmission data bit rate.
  • the signaling protocol utilized with the preferred embodiment of the present invention comprises 128 frames which include a predetermined synchronization code followed by eleven information blocks which comprise eight address, control or message codewords per phase.
  • the synchronization code enables identification of the data transmission rate, and insures synchronization by the selective call receiver with the data codewords transmitted at the various transmission rates.
  • FIG. 8 is an electrical block diagram of the selective call receiver 106 in accordance with the preferred embodiment of the present invention.
  • the heart of the selective call receiver 106 is a controller 816, which is preferably implemented using a low power MC68HC0x microcomputer, such as manufactured by Motorola, Inc., or the like.
  • the microcomputer controller hereinafter call the controller 816, receives and processes inputs from a number of peripheral circuits, as shown in FIG. 8, and controls the operation and interaction of the peripheral circuits using software subroutines .
  • the use of a microcomputer controller for processing and control functions (e.g., as a function controller) is well known to one of ordinary skill in the art.
  • the selective call receiver 106 is capable of receiving address, control and message information, hereafter called
  • the transmitted data is intercepted by an antenna 802 which couples to the input of a receiver section 804.
  • Receiver section 804 processes the received data in a manner well known in the art, providing at the output an analog 4-level recovered data signal, hereafter called a recovered data signal.
  • the recovered data signal is coupled to one input of a threshold level extraction circuit 808, and to an input of a 4-level decoder 810. Operation of the threshold level extraction circuit 808, 4-level decoder 810, symbol synchronizer 812, 4-level to binary converter 814, synchronization codeword correlator 818, and phase timing generator (data recovery timing circuit) 826 depicted in the selective call receiver of FIG. 8 is best understood with reference to United States Patent No.
  • the threshold level extraction circuit 808 comprises two clocked level detector circuits (not shown) which have as inputs the recovered data signal. Preferably, signal states of 17%, 50% and 83%, are utilized to enable decoding the 4-level data signals presented to the threshold level extraction circuit 808.
  • a clock rate selector When power is initially applied to the receiver portion, as when the selective call receiver is first turned on, a clock rate selector is preset through a control input (center sample) to select a 128X clock, i.e. a clock having a frequency equivalent to 128 times the slowest data bit rate, which as described above is 1600 bps.
  • the 128X clock is generated by 128X clock generator 844, as shown in FIG. 8, which is preferably a crystal controlled oscillator operating at 204.8 KHz (kilohertz).
  • the output of the 128X clock generator 844 couples to an input of frequency divider 846 which divides the output frequency by two to generate a 64X clock at 102.4 KHz.
  • the 128X clock allows the level detectors to asynchronously detect in a very short period of time the peak and valley signal amplitude values, and to therefore generate the low (Lo), average (Avg) and high (Hi) threshold output signal values required for modulation decoding.
  • the controller 816 After symbol synchronization is achieved with the synchronization signal, as will be described below, the controller 816 generates a second control signal (center sample) to enable selection of a IX symbol clock which is generated by symbol synchronizer 812 as shown in FIG. 8.
  • the 4-level decoder 810 preferably operates using three voltage comparators and a symbol decoder. The recovered data signal is coupled to an input of the three comparators having thresholds corresponding with normalized signal states of 17%, 50% and 83%.
  • the resulting system effectively recovers the demodulated 2- or 4- level FSK information signal by coupling the recovered data signal to the second input of an 83% comparator, the second input of a 50% comparator, and the second input of a 17% comparator.
  • the outputs of the three comparators corresponding with the low (Lo), average (Avg) and high (Hi) threshold output signal values are coupled to inputs of a symbol decoder.
  • the symbol decoder then decodes the inputs according to Table 2.
  • the MSB output from the 4-level decoder 810 is coupled to an input of the symbol synchronizer 812 and provides a recovered data input generated by detecting the zero crossings in the 4-level recovered data signal.
  • the positive level of the recovered data input represents the two positive deviation excursions of the analog 4-level recovered data signal above the average threshold output signal, and the negative level represents the two negative deviation excursions of the analog 4-level recovered data signal below the average threshold output signal.
  • the symbol synchronizer 812 uses a 64X clock at 102.4 KHz which is generated by frequency divider 846, that is coupled to an input of a 32X rate selector (not shown).
  • the 32X rate selector is preferably a divider which provides selective division by 1 or 2 to generate a sample clock which is thirty- two times the symbol transmission rate.
  • a control signal (1600/3200) is coupled to a second input of the 32X rate selector, and is used to select the sample clock rate for symbol transmission rates of 1600 and 3200 symbols per second.
  • the selected sample clock is coupled to an input of 32X data oversampler (not shown) which samples the recovered data signal (MSB) at thirty-two samples per symbol.
  • the symbol samples are coupled to an input of a data edge detector (not shown) which generates an output pulse when a symbol edge is detected.
  • the sample clock is also coupled to an input of a divide-by-16/32 circuit (not shown) which is utilized to generate IX and 2X symbol clocks synchronized to the recovered data signal.
  • the divided-by-16/32 circuit is preferably an up/down counter.
  • the output generated by the AND gate causes the count of divide-by-16/32 circuit to be advanced by one count in response to the pulse which is coupled to the input of divide- by-16/32 circuit from the data edge detector, and when the pulse coupled to the input of the AND gate arrives after the generation of a count of thirty-two by the divide-by-16/32 circuit, the output generated by the AND gate causes the count of divide-by-16/32 circuit to be retarded by one count in response to the pulse which is coupled to the input of divide- by-16/32 circuit from the data edge detector, thereby enabling the synchronization of the IX and 2X symbol clocks with the recovered data signal.
  • the symbol clock rates generated are best understood from Table 3 below.
  • the IX and 2X symbol clocks are generated 1600, 3200 and 6400 bits per second and are synchronized with the recovered data signal.
  • the 4-level binary converter 814 couples the IX symbol clock to a first clock input of a clock rate selector (not shown) .
  • a 2X symbol clock is coupled to a second clock input of the clock rate selector.
  • the symbol output signals (MSB, LSB) are coupled to inputs of an input data selector (not shown).
  • a selector signal (2L/4L) is coupled to a selector input of the clock rate selector and the selector input of the input data selector, and provides control of the conversion of the symbol output signals as either 2-level FSK data, or 4- level FSK data.
  • 2-level FSK data conversion (2L) is selected, only the MSB output is selected which is coupled to the input of a conventional parallel to serial converter (not shown) .
  • the IX clock input is selected by clock rate selector which results in a single bit binary data stream to be generated at the output of the parallel to serial converter.
  • clock rate selector When the 4-level FSK data conversion (4L) is selected, both the LSB and MSB outputs are selected which are coupled to the inputs of the parallel to serial converter.
  • the 2X clock input is selected by clock rate selector which results in a serial two bit binary data stream to be generated at 2X the symbol rate, which is provided at the output of the parallel to serial converter.
  • the serial binary data stream generated by the 4-level to binary converter 814 is coupled to inputs of a synchronization codeword correlator 818 and a demultiplexer 820.
  • Predetermined VV A" codeword synchronization patterns are recovered by the controller 816 from a code memory 822 and are coupled to an "A" codeword correlator (not shown) .
  • an "A" or tt A-bar” output is generated and is coupled to controller 816.
  • the particular "A" or ⁇ A-bar" codeword synchronization pattern correlated provides frame synchronization to the start of the frame ID codeword, and also defines the data bit rate of the message to follow, as was previously described.
  • the serial binary data stream is also coupled to an input of the frame codeword decoder (not shown) which decodes the frame codeword and provides an indication of the frame number currently being received by the controller 816.
  • the frame codeword decoder (not shown) which decodes the frame codeword and provides an indication of the frame number currently being received by the controller 816.
  • power is supplied to the receiver portion by battery saver circuit 848, shown in FIG. 8, which enabled the reception of the "A" synchronization codeword, as described above, and which continues to be supplied to enable processing of the remainder of the synchronization code.
  • the controller 816 compares the frame number currently being received with a list of assigned frame numbers stored in code memory 822.
  • the controller 816 If the currently received frame number differ from an assigned frame numbers, the controller 816 generates a battery saving signal which is coupled to an input of battery saver circuit 848, suspending the supply of power to the receiver portion. The supply of power will be suspended until the next frame assigned to the receiver, at which time a battery saver signal is generated by the controller 816 which is coupled to the battery saving circuit 848 to enable the supply of power to the receiver portion to enable reception of the assigned frame.
  • a predetermined "C” codeword synchronization pattern is recovered by the controller 816 from a code memory 822 and is coupled to a "C" codeword correlator (not shown) .
  • a "C” or “C-bar” output is generated which is coupled to controller 816.
  • the particular "C” or “C-bar” synchronization codeword correlated provides "fine” frame synchronization to the start of the data portion of the frame.
  • the start of the actual data portion is established by the controller 816 generating a block start signal (Blk Start) which is coupled to inputs of a codeword de-interleaver 824 and a data recovery timing circuit 826.
  • a control signal (2L / 4L) is coupled to an input of clock rate selector (not shown) which selects either IX or 2X symbol clock inputs.
  • the selected symbol clock is coupled to the input of a phase generator (not shown) which is preferably a clocked ring counter which is clocked to generate four phase output signals (01-04).
  • a block start signal is also coupled to an input of the phase generator, and is used to hold the ring counter in a predetermined phase until the actual decoding of the message information is to begin. When the block start signal releases the phase generator, it begins generating clocked phase signals which are synchronized with the incoming message symbols . The clocked phase signal outputs are then coupled to inputs of a phase selector 828.
  • the controller 816 recovers from the code memory 822, the transmission phase number to which the selective call receiver is assigned.
  • the phase number is transferred to the phase select output (0 Select) of the controller 816 and is coupled to an input of phase selector 828.
  • a phase clock, corresponding to the transmission phase assigned, is provided at the output of the phase selector 828 and is coupled to clock inputs of the demultiplexer 820, block de-interleaver 824, and address and data decoders 830 and 832, respectively.
  • the demultiplexer 820 is used to select the binary bits associated with the assigned transmission phase which are then coupled to the input of block de-interleaver 824, and clocked into the de-interleaver array on each corresponding phase clock.
  • the de-interleaver uses an 8 x 32 bit array which de-interleaves eight 32 bit interleaved address, control or message codewords, corresponding to one transmitted information block.
  • the de-interleaved address codewords are coupled to the input of address correlator 830.
  • the controller 816 recovers the address patterns assigned to the selective call receiver, and couples the patterns to a second input of the address correlator.
  • the message information and corresponding information associated with the address is then decoded by the data decoder 832 and stored in a message memory 850.
  • the message information is coupled to the input of data decoder 832 which decodes the encoded message information into preferably a BCD or ASCII format suitable for storage and subsequent display.
  • the software based signal processor may be replaced with a hardware equivalent signal processor that recovers the address patterns assigned to the selective call receiver, and the message related information.
  • the message information and corresponding information associated with the address may be stored directly in the message memory 850. Operation in this manner allows later decoding of the actual message information, e.g., that encoded message information that decodes into a BCD, ASCII, or multimedia format suitable for subsequent presentation.
  • the memory in performing direct storage, the memory must be structured in a manner that allows efficient, high speed placement of the message information and corresponding information associated with the address.
  • a codeword identifier 852 examines the received codeword to assign a type identifier to the codeword in response to the codeword belonging to one of a set comprising a vector field and a set comprising a message field. After determining the type identifier, a memory controller 854 operates to store the type identifier in a second memory region within the memory corresponding with the codeword.
  • a sensible alert signal is generated by the controller 816.
  • the sensible alert signal is preferably an audible alert signal, although it will be appreciated that other sensible alert signals, such as tactile alert signals, and visual alert signals can be generated as well.
  • the audible alert signal is coupled by the controller 816 to an alert driver 834 which is used to drive an audible alerting device, such as a speaker or a transducer 836. The user can override the alert signal generation through the use of user input controls 838 in a manner well known in the art.
  • the stored message information can be recalled by the user using the user input controls 838 whereupon the controller 816 recovers the message information from memory, and provides the message information to a display driver 840 for presentation on a display 842, such as an LCD display.
  • a display 842 such as an LCD display.
  • FIG 9 a memory register diagram of a non- optimal four phase structure for storing non-optimal type identifiers associated with address, control and data codewords is illustrated.
  • Motorola's FLEXTM selective call signalling protocol is based on a set of 128 frames appearing on a signalling channel during each 4 minute period of time. Battery savings in such a system is predominantly derived from the organization of messaging fields within each transmission frame. Since the active address codewords are grouped together in a defined field at the beginning of each frame, the selective call signalling device can immediately revert to a battery saver mode at the end of the particular field assigned to the device when its address is not detected. However, in order for the pager to properly locate messaging information occurring later within the frame, there are vectoring codewords assigned to indicate where the message begins and ends within the frame.
  • FLEXTM protocol means that the requirements for decoding a FLEXTM protocol frame will require a certain amount of memory.
  • an optimally designed FLEXTM protocol decoder should keep a record of active vector codewords in addition to active messaging codewords. Accordingly, a key objective of and optimal FLEXTM protocol decoder becomes minimization of the size of this required memory. Achieving this objective will ultimately result in a smaller, power efficient, and lowest cost device memory device.
  • each codeword with the possible exception of word 0 in each phase, may require reserved memory.
  • This memory comprising a first memory region, will be used to assign specific "labels" to each received codeword. In this manner, information pertaining to a particular codeword can be retrieved at a later time so that proper decoding decisions can be made. This process of labeling codewords is called “flagging" the codewords.
  • the memory associated with the 352 possible codewords in the FLEXTM protocol frame is called “flag memory” . Table 4 below describes the maximum flagging requirements for each type of codeword within a FLEXTM protocol frame.
  • FIG. 9 shows all four phases (01-04) in a frame, for completeness .
  • Each column represents one phase in a FLEXTM protocol frame containing 88 possible codewords.
  • FIG. 10 the illustration shows a memory register diagram of a single phase in a four phase structure for storing, in a first region within the memory, one-bit type identifiers denoting codewords belonging to the vector field and the message field. Only one phase register is shown in FIG. 10 for simplicity of analysis. However, one of ordinary skill in the art would realize that the principles discussed in reference to the single phase register can be easily extended to a plurality of registers corresponding with a plurality of phases, by simply applying the disclosed principles in parallel.
  • the first step in achieving the optimal solution is based on the fact that a FLEXTM protocol decoder using a memory organization depicted in FIG. 10, is capable of locating a boundary between the vector field 1001 and the message field 1002. Although this boundary location is not known at the beginning of the frame, the FLEXTM protocol decoder will dynamically track the length of the vector field 1001 and subsequently determine when the message field 1002 starts.
  • FIG. 10 where the following symbols shown in Table 5 are used to denote FLEXTM protocol codewords:
  • the codewords as designated by symbols BIWn, A, LAn and V, belong exclusively to the vector field 1001.
  • the M (message) codeword may belong to either the vector field 1001 or the message field 1002.
  • the transmission format of the FLEXTM signaling protocol utilized in accordance with the preferred embodiment of the present invention defines address and data codewords by their position within the individual frames, not by a codeword identification bit such as used by POCSAG protocol systems. This feature allows a FLEXTM protocol decoder to determine whether a particular message codeword belongs to the vector field 1001 or the message field 1002.
  • a FLEXTM protocol decoder can inherently determine a position of a boundary 1003 between the vector field 1001 and the message field 1002.
  • the instant invention makes use of this boundary, which allows the flagging requirements to be broken down into two sub-tasks: (1) flagging in the vector field 1001 and (2) flagging in the message field 1002.
  • the minimal flagging requirements for these fields are shown in the Table 6 as follows:
  • FIG. 11 shows the memory register diagram of FIG. 10, illustrating the unique offset relationship between vector codewords and address codewords maintained in the preferred embodiment of the present invention.
  • Table 6 indicates that in the vector field 1001, there are four possible word types, which can be encoded with two bits. In the message field 1002 there are two possible word types, which require only one bit to encode. Hence, the optimal solution uses two bits for flagging vectors and one bit for flagging messages. The final flagging scheme is shown below:
  • This scheme breaks the flagging requirements into two categories, a set containing the vector field 1001 comprising a short address vector, a long address vector, a first message word, and a null word, and a set containing the message field 1002 comprising a message word and a null word.
  • the members of the first set are each identified using a unique two bit symbol, while the members of the second set are identified using a unique one bit symbol.
  • the optimal solution takes advantage of the fact that in the FLEXTM protocol frame, there is an address codeword for every vector codeword, no matter how many vector codewords there are. This is clearly illustrated in the example shown in FIG. 11. In order to have two bits of memory for each vector codeword, the optimal solution uses (1) the vector codeword memory bit, and (2) the memory bit reserved for the corresponding address codeword. This concept is demonstrated using one phase in FIG. 12.
  • FIG. 12 shows the first memory register diagram from FIG. 10, and a second memory register diagram showing storage of a first bit of a type identifier denoting codewords belonging to the vector field in a first region within the memory and storage of a second bit of the type identifier in second memory region within the memory corresponding with the codeword.
  • the first region within the memory corresponds with those memory registers used to flag received address codewords 1201.
  • the second memory region 1202 is formed through a "re-use" of a portion of the first memory region 1201, when the codeword being flagged belongs to the set comprising the vector field.
  • the illustration clearly shows how the bits from the address memory are effectively "combined" with the bits from the vector memory to form two- bit vector flagging. Note that this diagram represents only one phase of data, and as previously discussed, may be extended to N phases, such as four in the preferred embodiment of the present invention.
  • the left drawing in FIG. 12 shows the memory configured as 88 x 1 array and the right drawing in FIG. 12 shows an implementation that more clearly illustrates how the two bits required for flagging are assigned to each vector codeword. This implementation is dynamic in that the array may contract or expand to accommodate the minimum or maximum number of vector words, respectively.
  • the relationship between the msb & lsb must be maintained as shown. Accordingly, the msb is taken from the address word bit and the lsb is taken from the vector word bit. This is important because the msb is then only set to a v 1' when there is an address match (either long or short) . In either case, the decoder will set the address flag when it gets an address correlation. This scheme minimizes the number of hardware adders required by the memory address logic.
  • FIG. 13 shows an organization structure for an optimally configured memory for use in the de-interleaved information memory storage device in accordance with the preferred embodiment of the present invention.
  • the memory In order to minimize the flag setting logic, the memory would ideally be organized as 4 separate banks of 88 x 1. This configuration would allow bit manipulation of each flag. However, due to overall system timing constraints related to the read/write/modify timing requirements, such a memory configuration would be too slow. It would take 88 cycles to clear the memory for just one phase, and it would take 88 cycles to write the entire memory for one phase. For this reason, the memory described in this invention is organized as 44 x 8; with each phase being assigned 11 bytes. For one phase, this memory can be cleared in 11 cycles. Each byte that needs to be written will require only two cycles because the hardware decoder will be setting individual bits within one byte of memory. Similarly, only two cycles are required by the read/modify/write operation.
  • the memory array depicted in FIG. 13 implements an optimal memory storage device for use with the de-interleaved information memory storage device described herein.
  • the memory array may be implemented as a random access memory, using conventional memory technology known to one of ordinary skill in the art.

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Abstract

Dispositif de stockage d'information comprenant une mémoire (850) permettant de stocker un mot de code récupéré d'une pluralité de blocs d'informations désentrelacées. Le mot de code est stocké dans une première région de mémoire (1201) à l'intérieur de la mémoire (850). En réponse au mot de code appartenant à un ensemble de champs de vecteur ou de messages, un identificateur (852) examine le mot de code et assigne un identificateur de type correspondant à ce mot de code. Un régisseur de mémoire (854) stocke ensuite l'identificateur de type dans une deuxième région de mémoire (1202) à l'intérieur de la mémoire (850) correspondant au mot de code.
PCT/US1997/004759 1996-04-15 1997-03-20 Dispositif de stockage en memoire d'informations desentrelacees Ceased WO1997039591A1 (fr)

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US08/632,258 1996-04-15

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4369443A (en) * 1979-12-26 1983-01-18 Meta Systems, Inc. Message communication system with message storage
US4914649A (en) * 1988-09-12 1990-04-03 Motorola, Inc. Multiple frequency message system
US5128665A (en) * 1989-08-21 1992-07-07 Motorola, Inc. Selective call signalling system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4369443A (en) * 1979-12-26 1983-01-18 Meta Systems, Inc. Message communication system with message storage
US4914649A (en) * 1988-09-12 1990-04-03 Motorola, Inc. Multiple frequency message system
US5128665A (en) * 1989-08-21 1992-07-07 Motorola, Inc. Selective call signalling system

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