WO1997033230B1 - Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structure - Google Patents
Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structureInfo
- Publication number
- WO1997033230B1 WO1997033230B1 PCT/US1997/002546 US9702546W WO9733230B1 WO 1997033230 B1 WO1997033230 B1 WO 1997033230B1 US 9702546 W US9702546 W US 9702546W WO 9733230 B1 WO9733230 B1 WO 9733230B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- packet
- application
- register file
- bus structure
- Prior art date
Links
- 238000000034 method Methods 0.000 claims 10
- 230000008878 coupling Effects 0.000 claims 7
- 238000010168 coupling process Methods 0.000 claims 7
- 238000005859 coupling reaction Methods 0.000 claims 7
- 230000000694 effects Effects 0.000 claims 2
- 241000269627 Amphiuma means Species 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000004891 communication Methods 0.000 claims 1
- 230000009977 dual effect Effects 0.000 claims 1
- 230000000977 initiatory effect Effects 0.000 claims 1
- 230000004044 response Effects 0.000 claims 1
- 235000019837 monoammonium phosphate Nutrition 0.000 abstract 3
Abstract
An asynchronous data pipe (ADP) automatically generates transactions necessary to complete asynchronous data transfer operations for an application over a bus structure. The ADP includes a register file which is programmed and initiated by the application. The register file includes the bus speed, transaction label, transaction code, destination node identifier, destination offset address, length of each data packet, packet counter, packet counter bump field, control field, and a status field. During a data transfer operation, the ADP generates the transactions necessary to complete the operation over the appropriate range of addresses, using the information in the register file as a template. The ADP increments the value in the destination offset address field for each transaction according to the length of each data packet, unless the incrementing feature has been disabled and the transactions are to take place at a fixed address. The packet counter represents the number of transactions remaining to be generated. The packet counter value is decremented after each packet of data is transferred. The application can increment the packet counter value by writing to the packet counter bump field. A multiplexer is included within a system having multiple ADPs for multiplexing the information from the ADPs onto the bus structure. A demultiplexer is included within a system having multiple ADPs for routing information from the bus structure to the appropriate ADP.
Claims
AMENDED CLAIMS
[received by the International Bureau on 29 August 1997 (29 08.97), original claims 3, 14, 20, 29 and 35 amended; remaining claims unchanged (5 pages)]
1. An asynchronous data pipe configured for coupling between an application and a bus structure for automatically controlling asynchronous data transfer operations to and from the application over the bus structure comprising: a. means for receiving instructions regarding a data transfer operation; and b. means for automatically generating transactions necessary to complete the data transfer operation between the application and a node coupled to the bus structure.
2. The asynchronous data pipe as claimed in claim 1 further comprising a register file in which the application stores the instructions regarding the data transfer operation.
3. The asynchronous data pipe as claimed in claim 2 wherein the register file is used as a template for generating the transactions and headers necessary to complete the data transfer operation without direct processor control or supervision.
4. The asynchronous data pipe as claimed in claim 3 wherein the instructions within the register file include a destination address in an address space of the bus structure, a length of data to be transferred, a length of each data packet to be transferred and a direction of the transfer.
5. The asynchronous data pipe as claimed in claim 2 further comprising communicating means configured for coupling to a data buffer, wherein the data buffer is coupled between the asynchronous data pipe and the application for sending data to and receiving data from the application.
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13. The method as claimed in claim 12 wherein the instructions include the destination address, a length of data to be transferred, a length of each data packet to be transferred and a packet counter value representing a number of packets to be transferred.
14. The method as claimed in claim 13 wherein the register file is used as a template for generating the transaction and header necessary to write a packet of data onto the bus structure without direct processor control or supervision.
15. The method as claimed in claim 14 further comprising the steps of: e. increasing the destination address by the length of a data packet; f. decrementing the packet counter value; and g. repeating steps b-f for each packet of data to be transferred until the packet counter value is equal to zero.
16. The method as claimed in claim 15 wherein the packet of data is obtained from a data memory buffer loaded by the application.
17. A method of managing a read data transfer operation between an application and a node coupled to a bus structure comprising the steps of: a. receiving instructions regarding a read data transfer operation from the application; b. generating a transaction necessary to request that a packet of data from the node be placed on the bus structure; c. ' obtaining the packet of data from the bus structure; d. stripping header information from the packet of data; and e. providing the packet of data without the header information to the application.
18. The method as claimed in claim 17 wherein the instructions received from the application are stored in a register file.
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19. The method as claimed in claim 18 wherein the instructions include a destination address, representing an address at the node where the data is to be sent from, a length of data to be transferred, a length of each data packet to be transferred and a packet counter value representing a number of packets to be transferred.
20. The method as claimed in claim 19 wherein the register file is used as a template for generating the transaction and header necessary to read a packet of data from the node without direct processor control or supervision.
21. The method as claimed in claim 20 further comprising the steps of: f. increasing the destination address by the length of a data packet; g. decrementing the packet counter value; and h. repeating steps b-g for each packet of data to be transferred until the packet counter value is equal to zero.
22. The method as claimed in claim 21 wherein the packet of data is provided to the application through a data memory buffer.
23. An apparatus for managing asynchronous data transfer operations between one or more applications and a bus structure comprising: f. a plurality of asynchronous data pipes configured for coupling between the one or more applications and the bus structure, each including: i. means for receiving instructions configured for coupling to the application for receiving instructions regarding a data transfer operation; and ii. means for automatically generating transactions necessary to complete the data transfer operation; g. a physical bus interface configured for coupling to the bus structure for placing data on the bus structure and obtaining data from the bus structure;
h. a multiplexing circuit coupled between each asynchronous data pipe and the physical bus interface for transmitting data packets from the asynchronous data pipes to the bus structure; and i. a demultiplexing circuit coupled between each asynchronous data pipe and the physical bus interface for routing data packets obtained from the bus structure to an appropriate one of the asynchronous data pipes.
24. The apparatus as claimed in claim 23 wherein each asynchronous data pipe further comprises a register file in which data and instructions regarding the data transfer operation are stored.
25. The apparatus as claimed in claim 24 wherein the data and instructions are stored in the register file by one of the applications.
26. The apparatus as claimed in claim 24 wherein the register file includes a destination address in an address space of the bus structure, a length of data to be transferred, a length of each data packet and a direction of the data transfer.
27. The apparatus as claimed in claim 26 wherein the register file further includes a transaction label value for the asynchronous data pipe and further wherein each of the asynchronous data pipes have a unique transaction label value.
28. The apparatus as claimed in claim 26 wherein the register file further includes a range of transaction label values for the asynchronous data pipe and further wherein each of the asynchronous data pipes have a unique range of transaction label values.
29. The apparatus as claimed in claim 27 wherein the register file is used as a template for generating the transactions and headers necessary to complete the data transfer operation without direct processor control or supervision.
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30. The apparatus as claimed in claim 29 wherein the demultiplexing circuit determines the appropriate asynchronous data pipe to which a data packet should be routed by the transaction label value within the data packet.
31. The apparatus as claimed in claim 30 wherein the demultiplexing circuit determines the appropriate asynchronous data pipe to which a write response packet should be routed by the transaction label value within the data packet.
32. Ih apparatus as claimed in claim 30 wherein the transactions necessary to complete the data transfer operation are generated to an increasing range of addresses, by increasing the destination address by the length of each data packet when each transaction is generated.
33. The apparatus as claimed in claim 30 wherein the transactions necessary to complete the data transfer operation are generated to a fixed address.
34. The apparatus as claimed in claim 30 wherein the bus structure is an IEEE 1394 standard bus structure.
35. An asynchronous data pipe configured for coupling between an application and an IEEE 1394 standard bus structure for managing asynchronous data transfer operations to and from the application over the bus structure comprising: a. a register file; b. a programming circuit coupled to the register file and configured for coupling to the application for receiving instructions regarding a data transfer operation from the application and storing the instructions in the register file; and c. an automatic transaction generating circuit coupled to the register file for automatically generating transactions necessary without direct processor control or supervision to complete the data transfer operation using information in the register file as a template.
-39-
The applicant has made amendments, under PCT Article 19, to the claims of the application originally filed with the PCT at the United States receiving office. These amendments serve to distinguish the applicant's invention over the European Patent Application and U.S. patent cited by the International Searching Authority. In particular, the amendments identify that the invention of the applicant automatically generates transactions necessary for data transfer operations without direct processor control or supervision.
The International Search Authority has indicated that claims 1-4, 8, 23-29, and 35- 38 are not novel or do not involve an inventive step in light of European Patent Application publication number EP 0 428 111 A (HITACHI). In HITACHI, data transfer and control is established by direct CPU intervention. When the data transfer request occurs, the CPU first sets the individual bits of the control register. The control register bits designate the size of the data to be transferred, whether the source address data and destination address data are to be incremented, and whether a second data transfer is to occur. The CPU then sets the transfer count in the transfer count register, the source and destination address data in their respective registers, and provides the bus right to the bus timing and control circuit. The bus timing and control circuit then reads and decodes the individual control bits programmed by the CPU and effects the transfer. In EP 0 428 11 1 A, the CPU is properly referred to as the "bus master."
The International Search Authority has also indicated that claims 1 1-22 are not novel or do not involve an inventive step in light of U.S. Patent 4.493,021 (AGRAWAL.) In AGRAWAL, the network bus adapter (NBA) attaches packet and transport headers to each data packet prior to transmission. A bit-sliced microsequencer and dual CPU sytem is then used to control and manage data handling and communication of the host computer with the bus.
In contrast to the prior art, which requires a general purpose CPU to construct each request packet, the essence of the applicant's invention is to remove much of the overhead normally burdening the processor or application and to effect data transfer by use of an asynchronous data pipe (ADP.) The ADP automatically generates the data transactions necessary to complete the data transfer operation. The ADP includes a register file, which is programmed by the application, not the CPU, with the requirements and characteristics for the data transfer operation. After the register file is programmed and initiated by the application, the ADP automatically generates the read or write transactions necessary to
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complete the data transfer operation over the appropriate range of addresses using the information in the register file as a template for generating the transactions and headers. Because the ADP generates the required transactions automatically, direct processor control or supervision by the initiating application is not required. At least this feature distinguishes the applicant's invention over the cited references.
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Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU21299/97A AU2129997A (en) | 1996-03-07 | 1997-02-19 | Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structure |
| AT97906666T ATE198237T1 (en) | 1996-03-07 | 1997-02-19 | ASYNCHRONOUS DATA TRANSFER DEVICE FOR MANAGING ASYNCHRONOUS DATA TRANSFERS BETWEEN AN APPLICATION PROGRAM AND A BUS STRUCTURE |
| JP53178097A JP4155413B2 (en) | 1996-03-07 | 1997-02-19 | Asynchronous data pipe that automatically manages asynchronous data transfer between the application and the bus |
| EP97906666A EP0885418B1 (en) | 1996-03-07 | 1997-02-19 | Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structure |
| DE69703732T DE69703732T2 (en) | 1996-03-07 | 1997-02-19 | ASYNCHRONOUS DATA TRANSFER DEVICE FOR MANAGING ASYNCHRONOUS DATA TRANSMISSIONS BETWEEN AN APPLICATION PROGRAM AND A BUS STRUCTURE |
| CA002247341A CA2247341C (en) | 1996-03-07 | 1997-02-19 | Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structure |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/612,321 US6519268B1 (en) | 1996-03-07 | 1996-03-07 | Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structure |
| US08/612,321 | 1996-03-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1997033230A1 WO1997033230A1 (en) | 1997-09-12 |
| WO1997033230B1 true WO1997033230B1 (en) | 1997-10-16 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1997/002546 WO1997033230A1 (en) | 1996-03-07 | 1997-02-19 | Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structure |
Country Status (10)
| Country | Link |
|---|---|
| US (4) | US6519268B1 (en) |
| EP (1) | EP0885418B1 (en) |
| JP (1) | JP4155413B2 (en) |
| KR (1) | KR100439539B1 (en) |
| AT (1) | ATE198237T1 (en) |
| AU (1) | AU2129997A (en) |
| CA (1) | CA2247341C (en) |
| DE (1) | DE69703732T2 (en) |
| TW (1) | TW381233B (en) |
| WO (1) | WO1997033230A1 (en) |
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1997
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- 1997-02-19 JP JP53178097A patent/JP4155413B2/en not_active Expired - Lifetime
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- 1997-02-19 AU AU21299/97A patent/AU2129997A/en not_active Abandoned
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- 1997-02-19 EP EP97906666A patent/EP0885418B1/en not_active Expired - Lifetime
- 1997-02-19 WO PCT/US1997/002546 patent/WO1997033230A1/en active IP Right Grant
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2003
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2006
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2009
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