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WO1997015116A2 - Circuits a verrouillage et bascules pour cadencement vrai par horloge monophase (tspc) - Google Patents

Circuits a verrouillage et bascules pour cadencement vrai par horloge monophase (tspc) Download PDF

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Publication number
WO1997015116A2
WO1997015116A2 PCT/SE1996/001315 SE9601315W WO9715116A2 WO 1997015116 A2 WO1997015116 A2 WO 1997015116A2 SE 9601315 W SE9601315 W SE 9601315W WO 9715116 A2 WO9715116 A2 WO 9715116A2
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WO1997015116A3 (fr
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Jiren Yuan
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Forskarpatent I Linkoping AB
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Forskarpatent I Linkoping AB
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356026—Bistable circuits using additional transistors in the input circuit with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration
    • H03K3/356043—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation

Definitions

  • TSPC strategy has been widely accepted as a high speed CMOS circuit technique. It has obvious advantages such as simple clock generation and distribution, small number of clocked transistors and high speed [1, 2]. However, some aspects still need to be upgraded.
  • p-blocks are the speed bottlenecks. In order to gain a maximal throughput, one often arranges all logic operations into n-blocks and leave p-blocks with no logic operation at all. Even so, when complementary signals are needed, extra inverters have to be placed after the already- slow p-blocks, which limits the maximal throughput. To increase the speed of p-block, in a large extent, is significant for improving overall throughput ofthe pipeline.
  • TSPC is not a non-overlapping clocking system and, consequently, there is an up-limit of clock slope length beyond wliich logic gates become unreliable.
  • the up- Umit slope length depends on the process parameters and the gate complexity. The value has been reducing rapidly and could be less than Ins for improperly sized circuits in sub ⁇ micron CMOS technologies.
  • the clock buffer becomes larger and larger. In certain cases, a short slope is simply required by the up- limit constraints rather than the speed, which wastes power and chip area due to the huge clock buffer. Therefore, to expand the up-limit of clock slope length is significant
  • TSPC strategy is a dynamic circuit technique which has a low-limit of working frequency.
  • toggle frequencies may become very low and circuits become unreliable.
  • static feature becomes favorable.
  • part ofthe circuit may need to stay idle temporarily. Therefore, static performance is one ofthe important robustness issues, which, if possible, should be improved.
  • a single-stage TSPC full-latch and its speed and power advantages are presented in section IV while a fast and robust TSPC double pipeline using the full-latch is proposed in section V.
  • Dual-rail latches are discussed in section VI where completely ratio-insensitive cross-coupled latches and fast flipflop arrangements are suggested.
  • section VTI dual-rail latches clocked by a single transistor and using n-transistor-only logic for both n- and p-latches are proposed.
  • Static TSPC flipflops are described in section VHI where the semi-static and fully-static versions of the previous proposed latches are introduced. Performance comparisons are shown in section DC while conclusions are given in section X.
  • Fig. 1 Four basic stages in TSPC.
  • Fig. 2 D and D* generated from p-blocks.
  • Fig. 8 Low failure risk by using TSPC-2 type precharged latches.
  • Fig. 11 A single-stage TSPC full-latch.
  • Fig. 13 Proposed stabilizing method making the latched three-state.
  • Fig. 14 The full-latch used after the modified n-latch.
  • Fig. 15 TSPC split-latches.
  • Fig. 16 The full-latch used after a modified n-split-latch.
  • Fig. 17 The single-stage TSPC full-latch made from an SN-stage.
  • Fig. 18 Speed-up critical stages in a double pipeline.
  • Fig. 19 A fast and robust double-pipeline.
  • Fig. 20 CVSL-type latches.
  • Fig. 22 Delays versus ratio for CVSL-type latches.
  • Fig. 23 Delay comparison between CVSL and cross latches.
  • Fig. 24 Combination of CVSL n- and cross p-latches.
  • Fig. 25 Fast flip flop arrangement.
  • Fig. 26 Combinations of TSPC CN-stages and cross p-latches.
  • Fig. 28 Fast flipflop using STC-1 n-latch.
  • Fig. 30 Semi-static flipflops.
  • Fig. 31 Fully-static flipflop constructed by RAM-type latches.
  • Fig. 32 Fully-static flipflop constructed by static STC-1 latches.
  • Fig. 33 Fully static flipflop constructed by static STC-1 n- and static cross p-latches.
  • Fig. 34 Semi-static fast flipflops.
  • Fig. 35 Semi-static flipflops requiring idle-high clock.
  • Fig. 37 Semi-static STCL flipflops.
  • Fig. 38 Power-delay products of group 1.
  • TSPC TSPC
  • precharged p- and n- stages and non- precharged (static) p- and n-stages, named PP, PN, SP and SN stages, shown in Fig.1.
  • PP, PN, SP and SN stages These are the simplest stages which can be used to form latches and flipflops.
  • a positive edge-triggered flipflop can be formed, in its precharged version, by a combination of PP- SP-PN-SN or, in its non-precharged version, by a combination of SP-SP-SN-SN.
  • a negative edge-triggered flipflop can be formed by exchanging the p- and n-blocks.
  • Logic operations can be included in the flipflops as long as obeying the following rules: in stages PP or PN, logic parts are placed between two clocked transistors with single-type transistors (p or n) and in stages SP or SN, logic parts are placed in the both ends with complementary-type transistors [2].
  • a pipeline can be formed by alternatively placing the p- and n-blocks with logic included or not included. From the viewpoint ofhigh throughput, we prefer to arrange all logic operations only in n-blocks and leave p-blocks as half-clock-cycle delay elements. When complementary inputs to n-blocks are needed, we have to generate them through p-blocks. Fig.
  • FIG. 2 shows complementary outputs from (a) a precharged p-block and (b) a non-precharged p-block.
  • the SP and SN stages are one-direction latches while the PP and PN stages are precharged stages.
  • the output of a SP stage can be latched only when it is low and the output of a SN stage can be latched only when it is high, see Fig. 4. Let us first look at the SN stage in which a high-output will be latched during a low clock phase.
  • node b will be discharged from (Vdd-V'n t h) to ground.
  • V s of the clocked n-transistor represented by V n gs
  • V nu ⁇ the "instant" latching is still valid.
  • V nt h the "instant" latching is still valid.
  • V nt h the "instant" latching, i e. V n gs 2 V nt h, as a robust latching condition. It is the same for a SP stage except the voltages are just opposite, which is also shown in Fig. 5.
  • TSPC latches In non-precharged TSPC latches (SP-SP or SN-SN).
  • the actual latching stage can be either the first or the second, depending on the input state.
  • the worst case happens if the first stage is the actual latching stage since it is closer to the input.
  • Fig. 6(a) shows the worst latching cases for a SN-SN latch and a SP-SP latch respectively.
  • the fastest output transition happens if the second stage is the actual latching stage, which creates a worst case for its succedent latch.
  • Fig. 6(b) shows the worst unlatching cases for a SN- SN latch and a SP-SP latch respectively.
  • a latching failure occurs only when the input is unstable during latching, which implies that latching failures only occur between two latches.
  • a latching failure could occur internally as the cases shown in Fig. 7.
  • the position ofthe second stage (SN or SP) in a precharged latch is very similar to that ofthe first stage in a non-precharged latch in Fig. 6(a) so a latching failure could occur.
  • a failure can be defined for a precharged latch when a high-output of an n-latch becomes
  • below Vdd °r a low-output of a p-latch becomes V nt h above ground.
  • the p- or n-transistor in the next precharged latch wiU have leakage current.
  • the faUures are not serious enough, the chip may work at a high frequency but not at a low frequency, which we have observed.
  • a faUure can be defined when a high-output from the dashline box of Fig. 9 becomes
  • below V dd a low-output from the dash-line box of Fig. 10 becomes V nt h above ground.
  • below V dd or a low-output from the dash-line box of Fig. 10 becomes V nt h above ground.
  • Their noise margins equal only the threshold voltages of the p-transistor (Fig. 9) and the n-transistor (Fig. 10) respectively when they are latched.
  • the faUures wUl cause leakage current in the two stages.
  • a single- stage TSPC fuU-latch foUowing a precharged n-block to form a favorable configuration in a pipeline, shown in Fig.11.
  • the TSPC fuU-latch marked by the dash-line box, is formed by introducing an extra n-transistor into the original SP stage.
  • the added n- transistor is controUed by the precharged node signal of the previous n-block.
  • the control signal has a feature of inversed clock but is data-dependent during its evaluation phase. Both p- and n-branches in the fuU latch now become non-conductive during the high clock phase and data-dependently conductive during the low clock phase.
  • the data is fully latched at the output node so the succeeding stage does not have to be precharged.
  • an inverter can be placed between them to generate complementary outputs.
  • the output node is a three-state node, just Uke that of a C 2 MOS stage [5], which is useful in, for example, driving a bus.
  • the critical delay path ofthe full- latch is still the p-branch, the same as that ofthe original SP stage, and the load increase to the precharged node ofthe previous n-block is quite small.
  • the overaU speed is certainly improved. FinaUy, the fuU-latch is insensitive to the unperfect output of the precharged n-latch. Compared to the original non-precharged TSPC latch (SP+SP), it has no intermediate latching node and the output after the inverter becomes quite robust which will never give an unperfect low state to its succeeding precharged n-latch. If TSPC-2 type precharged n-latch is used, see Fig. 11(b), it will be more robust.
  • the original static TSPC p- and n-latches are modified into three-state static n-latches.
  • a p-transistor is used to charge the intermediate node of an n-latch to high during the low clock phase and an n-transistor is used to charge the intermediate node of a p-latch to low during the high clock phase. If the purpose is only to stabilize intermediate nodes, minimum precharging transistors can be used (in this paper, mark * always represents a mmimum size).
  • a pipeline formed by the modified non-precharge latches wiU be insensitive to clock slope.
  • the single-stage TSPC fuU-latch can be used after such a modified n-latch and form a favorable configuration in a pipeline, which is shown in Fig. 14.
  • the size of the precharging p-transistor should be chosen to satisfy the puU-down speed of the single-stage fuU-latch but over- sizing should be avoid to prevent from latching faUure.
  • the sizes of the p-transistors in the first stage of the modified latch can be minimized, since they are only used preventing charge- sharing.
  • n-spht- latch The combination of a modified n-spht- latch with the single-stage fuU-latch is shown in Fig. 16. In this configuration, only three clocked transistors are used. The input p-transistor(s) can be minimized or even eliminated completely. Simulations show that the n-transistor in the output stage of the n-spht-latch can receive a half-swing through charge-sharing even if the *-marked p- transistor is missing, which works weU down to a 3V power supply.
  • the precharging p-transistor also prevents the intermediate node from a latching faUure but its over-sizing has very Uttle impact on the same kind of latching faUure as that of a precharged n-latch so the robustness of the flipflop is increased, as wUl be shown later.
  • the single-stage TSPC fuU-latch can be made from a SN stage as weU and placed after a precharged p-block or a modified static p-block. These two options are shown in Fig. 17. Of course, these are not favorable configurations for a high throughput pipeline but they could find other apphcations, e.g. in double edge-triggered flipflops. In the foUowing, we shah name the two different types of single-stage fuU-latches as p-fuU-latch and n-fuU-latch respectively.
  • Double- edge-triggered flipflops have been discussed earher [7] which can be used to construct a so-caUed double pipeline. If the above mentioned positive and negative flipflops are arranged properly, a double-pipeline can be formed easUy.
  • Fig. 18(a) shows a double pipeline formed by two such flipflop lines starting and ending with opposite- type blocks. Note that the two output blocks (p-p and n-n) must be three-state-output blocks so when one of the two is active the other one wiU not make any conflict.
  • the single-stage n-full-latch and p-fuU-latch fit to the apphcation perfectly since they basicly present only one stage delays which are approximately the same for the n- and the p-fuU-latches so they can be used for the output stages in the double-pipeline shown in Fig. 19.
  • the input stages are identical to the output stages in Fig. 19. they are controUed by the precharged node signal from their succedent blocks rather than their precedent blocks and, therefore, they are not fuU-latches indeed.
  • the input p-stage or n-stage presents a much shorter hold-time than that of a simple SP or SN stage which can also possibly be used at the front to gain speed.
  • a short hold-time is important for robust input latching. Assuming that if the input changes from low to high immediately after a positive clock edge, a simple SP stage will give a low output to the succedent precharged stage quickly enough to stop its evaluation, which has been discussed in [2].
  • the input p-stage shown in Fig. 19 takes the evaluating information of the precharged node (from high to low) to prevent the output to the precharged stage from high to low. AdditionaUy, the extra serial n-transistor in the input p-stage also delays the output transition from high to low. For the combination shown in Fig.
  • the hold times are reduced from 120ps to 30ps by replacing the SP stage with the input p-stage and from 180ps to -40ps by replacing the SN stage with the input n- stage, respectively.
  • clock and signal slopes are both 200ps in order to show the impact of the circuit itself (improvements are simUar when slopes are 300ps).
  • AU transistor widths are 2 ⁇ m except the two in the precharged p-stage which are 4 ⁇ m (the middle one) and 8 ⁇ m (the top one) respectively.
  • the improvement wiU be dramatic, which shows the design direction and the robustness ofthe proposed input configuration.
  • the input stages can be seen as fuU-latches.
  • Precharge has been involved in aU the above single-stage fuU-latches.
  • completely non-precharged latches are preferred from low power consumption point of view.
  • complementary inputs are avaUable, there are efficient ways to construct complemetary-output latches, i.e. the dual-raU latches, which have already been seen in Uterature [8].
  • the CVSL-type latches described in [8] inherently give complementary outputs.
  • the basic structures of p- and n-latches in this type are shown in Fig. 20.
  • the position ofthe clocked transistors can be exchanged with that ofthe input transistors but if the clocked transistors are directly connected to power or ground (do not worry about charge- sharing in this case) they may be sized first without increasing the fan-in ofthe latch.
  • the n-latch can never work properly and wUl stop working when W p 3 3.4 ⁇ m-
  • the n-size is better to be minimized. If the n-size is increased to 4 ⁇ m in the p-latch, the proper p- sizes have to be more than 20 ⁇ m, which makes the latch unnecessarily large. Great care must be taken in designing these latches particularly when logic is included. In the foUowing, therefore, we present two alternatives. In the first, completely ratio- insensitive cross-coupled latches are introduced and. in the second, fast flipflop arrangements are proposed.
  • Fig. 21 The completely ratio-insensitive cross p- and n-latches are shown in Fig. 21. Each of them is formed by cross-connecting two identical TSPC fuU-latch stages which has been mentioned before.
  • the reason for being ratio-insensitive is that there is no confliction between n- and p-branches. From the first glance, they seem to present larger fan-in than that of CVSL-type latches but, in fact, it is not so obvious. To be fair, we can compare their delays under the same fan-in and load. Before that, we first obtained the best ratio corresponding to the least delay for CVSL-type p- and n-latches and kept the ratio for different fan-in values.
  • Fig. 23 The cross-coupled TSPC p-latch is apparently better than the CVSL-type p- latch, see Fig. 23(a), not only ratio-insensitive but also less fan-in under the same delay. Oppositely, the cross n-latch presents larger delay than that ofthe CVSL-type n-latch but has an advantage of ratio-insensitive. A better combination could thus be a CVLS-type n- latch plus a cross p-latch, shown in Fig. 24.
  • a chain of this kind can work up to twice the clock rate of a complete CVLS-type latch chain. Note that logic can still be included in both latches and the p- latch is ratio insensitive. If the p-latch is just a passing stage in a high speed pipeline, it can be further simplified. As the CVSL-type n-latch has pull-up driving capabUity in the latching phase, the two p-transistors can be borrowed by the two SP-stages as shown in Fig. 25(b). If such a borrowing is done by a CVSL-type p-latch, it wiU require a significant size increase of the CVSL-type n-latch due to the problem of ratio- dependence. However, there is no such problem in Fig. 25(b). As long as the succedent stage is a CVSL-type n-latch, a cross-coupled TSPC n-latch or a precharged TSPC n- latch, it works. This further reduces the power consumption under the maximum speed
  • the first is that, for safety reason, the n- transistors marked by * in the SP-stages should be minimize If the flip-delay ofthe next CVSL-type n-latch is too large (with heavy logic, for example) so the minimized n- transistor is still too fast, the two SP-stages can be modified into the type shown at the right side of Fig. 25(a). Such modification can increase the puU-down delay to the desired value without increasing either fan-in or power consumption.
  • the second is that when a chain of this kind has to be terminated with the two SP-stages Uke that in Fig.
  • one more SP-stage for a single-rail output or two more SP-stages for a dual-rail output can be cascaded after one or two outputs.
  • a second arrangement is to use two separate TSPC SN-stages together with a cross-coupled TSPC p-latch, shown in Fig. 26(a).
  • the delay of n-latch is reduced so much (to half the delay of a CVSL-type n-latch) that more logic operations can be included in the n-latch although they should be complementary.
  • a third arrangement could be to cascade the two SN-stages and to arrange only single-raU logic in the first SN-stage, shown in Fig. 26(b).
  • a latch uses only a single clocked transistor which has not been reported so far.
  • STC single-transistor-clocked
  • STC-1 single-transistor-clocked latches
  • STC-2 single-transistor-clocked latches
  • the first kind of single-transistor-clocked (STC-1 ) latches are shown in Fig. 27, which is evolved from the CVSL-type latches.
  • a STC-1 p-latch gives an opposite order of output transitions to the n-latch. Therefore, the two latches can not be directly cascaded. Apart from this, the p-latch presents much larger delay than that ofthe n-latch due to the same reason as mentioned before.
  • the n-latches in the fast flipflop arrangements in Fig. 25 in the last section can possibly be replaced by the STC-1 n-latch, which are shown in Fig. 28. Since the two SP stages in Figs. 28(a) or (b) always give a high-to-low transition first, making the succeeding STC- 1 n-latch work safely. This leads to both fast and smaU cock load.
  • the STC-2 p-latch looks similar to the STC-1 n-latch. For example, both cross- coupled pairs are formed by p-transistors. However, they are quite different.
  • the basic function ofthe STC-2 p-latch is simUar to that ofthe two SP-stages, i.e. to transfer data during low clock phase and to latch the low-output data during high clock phase and the high-output data in the beginning of high clock phase.
  • the input transition order to the STC-2 p-latch is not important although the STC- 1 n-latch always gives the high-to-low transition first, which is perfect.
  • the common node of the STC-2 p- latch When clock falls, the common node of the STC-2 p- latch will be charged up to a voltage depending on the ratio between the conductances of the clocked transistor and the on-branch. Since the on-branch is formed by a p-transistor and an n-transistor in serial which sizes are minimized, the working ratio is easily satisfied. The output where the n-transistor is on wUl be kept low and the output where the n-transistor is off will be pulled to high, which wiU turn off the p-transistor where the output is low. FinaUy, both outputs are firmly defined by the puU-up and puU-down branches.
  • the reason of having smaU delay is because it has much less ratio problem and the delay is caused by only a single transition (low-to-high) not by two transitions like that of the p-latch in Fig. 27.
  • the output states will be kept although the high-output wUl lose pull-up capabUity. If the inputs change to opposite states, both outputs become low after a certain delay.
  • the original low-output wiU not share the charge on the common node, since the gate and the source of the p-transistor which is originally off wUl be pulled down simultaneously with a difference almost equal to the p-threshold voltage, confirmed by simulation.
  • the STC-2 p-latch uses only a single clocked transistor and only n- transistors in logic.
  • the delay of high-to- low transition during latching phase becomes longer due to the discharging of the common node, which is favorable to the next n-latch.
  • the delay is simulated to be approximately twice the delay of high-to-low transition of the n-latch, enough to guarantee the flip of next n-latch. Note that this delay is aUowed to be equal to a whole clock cycle so the speed is not affected.
  • the size ofthe clocked p-transistor in the STC-2 p-latch can be used to control the delay ratio between low-to-high and high-to-low transitions.
  • the fan-in of the p-latch is minimized even if logic is included, giving less load to the n-latch and making the flipflop very fast.
  • the STCL-flipflop therefore, is superior both in high speed and in low power consumption.
  • TSPC was introduced as a high-speed dynamic circuit technique.
  • a high frequency clock was assumed, which is reasonable for most of high speed circuits.
  • static performance is very useful.
  • static we mean the clock can be at zero frequency (against the concept of "dynamic"), which should be distinguished from the concept of non-precharged.
  • the MSB-circuit in an asynchronous counter the toggle frequencies may be weU beyond the low frequency limit of a dynamic circuit. In order to reduce power consumption of a large chip, part of the chip circuit may stay in idle (a zero clock frequency).
  • a static flipflop has a large noise margin and smaU clock slope sensitivity. Therefore, it is of great interest to introduce static TSPC flipflops.
  • Fig. 30(a) eliminates completely the confliction between p- and n-branches
  • Fig. 30(b) uses less transistors (less clock load) with very little confliction which will not pose any danger to the function as long as the size of p-transistor in the dashline box is kept mi imiim
  • sizes of both p- and n-transistors in the dashline boxes should be kept minimum to minimize the load.
  • the gate connections (to the half-swing nodes) in Figs. 30(a) and (b) make them very weak when they are conducting and give less load to the real output.
  • the two output nodes if the two output nodes are temporarily connected by the two input transistors when both inputs are high, the two output nodes will have a voltage difference equal to the voltage drop on the two input transistors and will later recover the original logic states when they become nontransparency again.
  • the sizes of transistors marked by * can be minimized.
  • the flipflops shown in Figs. 31 and 32 are fuUy-static and have complementary outputs available. However, the p-latches turns out to be much slower than the n-latches (more than a factor of two). It is thus necessary to replace the p-latch with a static cross p-latch.
  • the flipflop constructed by a static STC- 1 n-latch and a static cross p-latch is shown in Fig. 33.
  • the two extra p-transistors lock the high-output and the extra n-transistor locks the low-output (through one ofthe two bottom n-transistors) during high clock phase.
  • the flipflop is significantly faster than static flipflops constructed by pure RAM-type or pure static STC- 1 latches.
  • the static STC-2 p-latch in Fig. 36 can prevent this from occurring. Since the original high-output is pulled down, the common node will be forced down and the inverter wiU give a high output to the two extra n-transistors to pull aU other intemal nodes down firmly. Only when the clock goes low, the common node is charged to high and the inverter gives a low output to turn off the two extra n- transistors. In this case, the latch returns to normal . Compared to the dynamic version of the p-latch, the extra n-transistor now should be counted into the conductance ratio. However, this is not a problem.
  • the static STCL flipflop like its dynamic version, has minimized clock load and fan-in for both p- ans n-latches and superior in speed and low power consumption.
  • the semi- static version ofthe STCL flipflop can be formed by combinations of dynamic and static versions ofthe STC-2 p- and STC-1 n-latches. Positive-edge triggered semi-static flipflops suiting either idle-high or idle-low clock are given in Fig. 37.
  • the two dual-raU flipflops in Fig. 37 can also be modified into single-raU flipflops by using input inverters. IX. PERFORMANCE COMPARISONS
  • the third is the capacitance C. which is calculated by sui-ciming the capacitances of gate-to-substrate and drain/source-to- substrate connected to the node.
  • the capacitance values of n(or p)-gate-to-substrate and n-drain(source)-to-substrate are quite similar so they are weighted to 1.0 for a mmimum width transistor (2 ⁇ m), defined as a unit-capacitance, whUe the capacitance values of p-drain(or source)-to-substrate and n(or p)-gate-to-drain(or source) are weighted to 1.2 and 0.2 respectively.
  • the contribution of a gate-to- source capacitance is directly added to the gate node.
  • the contribution of a gate-to-drain capacitance is calculated in two ways. First, if the gate transition directly leads to a drain transition, its contribution is multiplied by a factor of 4 because it is not only discharged but also recharged oppositely (a factor of 2) and such a discharge- recharge happens every transition not every two transition (another factor of 2) like that of a substrate related capacitance.
  • flipflops 1-6 are single-raU types and flipflops 7-11 are dual-raU types. New proposed circuits are marked by sign "t”. Flipflops are constructed by cascading different stages indicated by their names with a connecting sign "-" between.
  • PN-SN means TSPC-1 type whUe PN/SN means TSPC-2 type.
  • the characters P and N in parentheses are used to either identify a p-latch or an n-latch or indicate the types of delay- dominant latches.
  • Stage SFL represents static versions of the TSPC single-stage fuU-latch.
  • Flipflop 10 in table 1 and flipflop 16 in table 2 are merged-stage types.
  • WD, MCS, A, CT and T mean the worst delay, the aUowable maximum clock slope, the activity rate, the number of clocked transistors and the total transistor count respectively.
  • the classic master-slave flipflop is formed by four transmission gates, four inverters and a clock buffer to offer two-phase clocks internaUy [8]. Table 2 Performance comparison of semi-static flipflops
  • the best improvements can be found by comparing the first and the last flipflops in each group. From group 1 to group 4, in the best cases, the delays are reduced by factors of 1.3, 2.1, 2.2 and 2.4 whUe the power- delay products are reduced by factors of 1.9, 3.5, 3.4 and 6.5 respectively. This indicates that the new proposed flipflops are featured by both high speed and low power consumption. In the same time, the maximum aUowable clock slopes are generaUy increased (the most obvious one is circuit 7, a factor of 3), compared to the original TSPC flipflops.
  • the flipflops using pure CVSL-type, RAM-type or classic latches aUow very long clock slopes but present largest delays and highest power-delay products, which makes them only interesting in special cases.
  • Almost aU new flipflops use less transistors and particularly less clocked transistors.
  • the STC-1 and STC-2 latches are clocked by only a single clocked transistor. Their advantages are not completely covered by the table and the plots. For example, when logic needs to be included in the latches, the unique type of flipflops ( 11, 17, 18 and 22) with n-transistor- only logic (in both n- and p-latches and in both dynamic and static versions) wui show more superior performance over the others.
  • a TSPC single-stage fuU-latch has been proposed for improving the original TSPC pipeline.
  • the delay of p-block the speed bottleneck
  • the power-delay product of such a pipeline can be reduced by a factor of 1.9.
  • the aUowable maximum clock slope are generaUy increased and in the best case by a factor of 3.
  • a fast and robust TSPC double-pipeline is introduced by using the p- and n-versions of the proposed full-latch stage for the front and the end stages of the pipeline which is the most critical in speed and robustness.
  • Dual-raU latches have inherently complementary outputs available and are usuaUy non-precharged, e.g. the CVSL-type and the RAM-type.
  • the investigation indicates that the p-blocks are the serious speed bottleneck (worse than the original TSPC) and the ratio problem needs great care.
  • new dual- latches and flipflops have been proposed. Among them are the dynamic, semi-static and fuUy-static versions of ratio-insensitive cross-coupled latches, the STC latches (single- transistor-clocked latches, STC-1 and STC-2) and the fast flipflops using the STC latches together with the TSPC SP-stages.
  • the delays are reduced by factors of 2.1, 2.2 and 2.4 respectively for the dynamic, the semi-static and the fully-static flipflops, compared to their original counterparts.
  • the power consumptions are greatly reduced so the power-delay products are improved by factors of 3.5, 3.4 and 6.5 respectively.
  • the aUowable maximum clock slopes of them can not compete with the CVSL-type and the RAM-type, they have been improved by factors of 1.5-2, compared to the original TSPC.
  • a unique point ofthe flipflops using STC latches is that aU logic transistors are in n-type (for both n- and p-latches and for both dynamic and static versions), which gives large speed room for such a pipeline.

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  • Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)

Abstract

On analyse dans ce document la vitesse, la robustesse et la performance statique des circuits à verrouillage et bascules pour cadencement vrai par horloge monophase (TSPC). On propose de nouveaux circuits à verrouillage et de nouvelles bascules permettant d'améliorer la vitesse globale, les économies d'énergie, l'insensibilité à la pente d'horloge et la performance statique du TSPC. On propose de nouveaux circuits à verrouillage et bascules à rail unique et à rail double, parmi lesquels on compte différentes versions dynamiques, partiellement statiques et entièrement statiques. Les retards sont réduits selon des facteurs de 1,3, 2,1, 2,2 et 2,4 respectivement pour les versions dynamiques à rail unique, dynamiques à rail double, partiellement statiques et entièrement statiques. En même temps, les consommations d'énergie sont également réduites, et par conséquent, les produits vitesse-consommation sont réduits selon des facteurs de 1,9, 3,5, 3,4 et 6,5 respectivement pour un taux d'activité moyen (0,25). Ces perfectionnements sont accompagnés de comptes de transistors réduits et de charges d'horloge réduites. Une version particulière des circuits à verrouillage proposés n'utilise qu'un seul transistor cadencé et que des transistors NMOS en logique (dans les circuits à verrouillage à la fois de type n et de type p et dans les versions tant dynamiques que statiques).
PCT/SE1996/001315 1995-10-17 1996-10-16 Circuits a verrouillage et bascules pour cadencement vrai par horloge monophase (tspc) Ceased WO1997015116A2 (fr)

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SE9503616A SE507550C2 (sv) 1995-10-17 1995-10-17 Anordning vid grindar och flipp-floppar av kategorin äkta enfasklockade kretsar
SE9503616-6 1995-10-17

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19749521A1 (de) * 1997-11-08 1999-06-02 Temic Semiconductor Gmbh Bistabile Kippstufe
US6515528B1 (en) 1999-06-07 2003-02-04 Infineon Technologies Ag Flip-flop circuit
WO2003061111A3 (fr) * 2002-01-15 2004-03-11 Microtune San Diego Inc Module de detection a vitesse elevee de frequence-phase
DE102004037591A1 (de) * 2004-08-03 2006-03-16 Infineon Technologies Ag Dual-Rail Precharged Flip-Flop
CN104378103A (zh) * 2014-09-16 2015-02-25 哈尔滨工业大学（威海） 双轨预充电逻辑单元结构
US9088285B2 (en) 2013-06-25 2015-07-21 Qualcomm Incorporated Dynamic divider having interlocking circuit
WO2018137751A1 (fr) * 2017-01-24 2018-08-02 Telefonaktiebolaget Lm Ericsson (Publ) Circuits à retard variable
CN111027276A (zh) * 2018-10-09 2020-04-17 刘保 基于多相电平敏感锁存器的集成电路优化系统和方法
US10840892B1 (en) 2019-07-16 2020-11-17 Marvell Asia Pte, Ltd. Fully digital, static, true single-phase clock (TSPC) flip-flop
CN112260682A (zh) * 2020-10-26 2021-01-22 加特兰微电子科技(上海)有限公司 Tspc触发器、双模预分频器和分频器相关器件

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106571825A (zh) * 2016-11-07 2017-04-19 中山大学 基于tspc电路的异步时钟信号产生电路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59134918A (ja) * 1983-01-24 1984-08-02 Toshiba Corp ラツチ回路
US5311070A (en) * 1992-06-26 1994-05-10 Harris Corporation Seu-immune latch for gate array, standard cell, and other asic applications

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19749521A1 (de) * 1997-11-08 1999-06-02 Temic Semiconductor Gmbh Bistabile Kippstufe
DE19749521C2 (de) * 1997-11-08 1999-09-02 Temic Semiconductor Gmbh Bistabile Kippstufe
US6154077A (en) * 1997-11-08 2000-11-28 Temic Semiconductor Gmbh Bistable flip-flop
US6515528B1 (en) 1999-06-07 2003-02-04 Infineon Technologies Ag Flip-flop circuit
WO2003061111A3 (fr) * 2002-01-15 2004-03-11 Microtune San Diego Inc Module de detection a vitesse elevee de frequence-phase
US6778026B2 (en) 2002-01-15 2004-08-17 Microtune (San Diego), Inc. High-speed phase frequency detection module
DE102004037591A1 (de) * 2004-08-03 2006-03-16 Infineon Technologies Ag Dual-Rail Precharged Flip-Flop
US9088285B2 (en) 2013-06-25 2015-07-21 Qualcomm Incorporated Dynamic divider having interlocking circuit
CN104378103A (zh) * 2014-09-16 2015-02-25 哈尔滨工业大学（威海） 双轨预充电逻辑单元结构
WO2018137751A1 (fr) * 2017-01-24 2018-08-02 Telefonaktiebolaget Lm Ericsson (Publ) Circuits à retard variable
US10790808B2 (en) 2017-01-24 2020-09-29 Telefonaktiebolaget Lm Ericsson (Publ) Variable delay circuits
CN111027276A (zh) * 2018-10-09 2020-04-17 刘保 基于多相电平敏感锁存器的集成电路优化系统和方法
US10840892B1 (en) 2019-07-16 2020-11-17 Marvell Asia Pte, Ltd. Fully digital, static, true single-phase clock (TSPC) flip-flop
CN112260682A (zh) * 2020-10-26 2021-01-22 加特兰微电子科技(上海)有限公司 Tspc触发器、双模预分频器和分频器相关器件

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SE507550C2 (sv) 1998-06-22
SE9503616L (sv) 1997-04-18
WO1997015116A3 (fr) 1997-05-15

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