WO1997014100B1 - A system and method for increasing functionality on the peripheral component interconnect bus - Google Patents
A system and method for increasing functionality on the peripheral component interconnect busInfo
- Publication number
- WO1997014100B1 WO1997014100B1 PCT/US1996/014939 US9614939W WO9714100B1 WO 1997014100 B1 WO1997014100 B1 WO 1997014100B1 US 9614939 W US9614939 W US 9614939W WO 9714100 B1 WO9714100 B1 WO 9714100B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory access
- direct memory
- electronic device
- coupled
- peripheral component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Abstract
An apparatus and method for enabling a Peripheral Component Interconnect ('PCI') bus (220) to support direct memory access ('DMA') tranfers (230a). The apparatus comprises a plurality of DMA controllers (230a-230n), a state machine (360) and an internal storage element (340). The plurality of DMA controllers (230a-230n) transfers DMA requests for an electronic device to the state machine (360) and DMA acknowledges from the state machine (360) to the electronic device. The state machine (360) controls the DMA transfer by performing two transactions for each DMA transfer: namely, a memory cycle and an input/output cycle. The internal storage element (340) acts as a buffer for this multiple cycle DMA transfer.
Claims
1. An apparatus configured to support a direct memory access transfer on a multiplexed bus between a main memory element and an electronic device, the apparatus comprising:
a plurality of direct memory access controllers capable of receiving a direct memory access request from the electronic device coupled to the multiplexed bus;
a state machine coupled to the plurality of direct memory access controllers, the state machine coordinating the direct memory access transfer upon detecting that the plurality of direct memory access controllers have received the direct memory access request; and
an internal storage element coupled to said state machine, the internal storage element collecting data during the direct memory access transfer.
2. The apparatus according to Claim 28, wherein the state machine coordinating the direct memory access transfer by separating the direct memory access transfer into a memory cycle and an input/output cycle.
3. The apparatus according to Claim 2, wherein the state machine coordinating the direct memory access transfer by initially determining whether the direct memory access transfer requested by the electronic device is a memory read operation.
4. The apparatus according to Claim 3, wherein if the direct memory access transfer is the memory read operation, the state machine prompts the apparatus to (i) gain ownership of the
multiplexed bus, (ii) collect data from the main memory element, (iii) transmit a direct memory access acknowledge signal to the electronic device, and (iv) perform a write cycle on the multiplexed bus by placing the data and a dummy address onto the multiplexed bus.
5. The apparatus according to Claim 2, wherein if the direct memory access transfer is a memory write operation, the state machine prompts the apparatus to (i) gain ownership of the
Peripheral Component Interconnect bus, (ii) transmit a direct memory access acknowledge signal to the electronic device, (iii) collect data from the electronic device and (iv) perform a write cycle on the Peripheral Component Interconnect bus by placing the data and an address supported by the main memory element onto the Peripheral Component Interconnect bus.
6. The apparatus according to Claim 2, wherein the plurality of direct memory access controllers are coupled to the electronic device via a first direct memory access channel of a plurality of direct memory access channels.
7. The apparatus according to Claim 6 further comprising a location register indicating if the electronic device is coupled to the Peripheral Component Interconnect bus.
8. The apparatus according to Claim 7, wherein the location register coupled to the state machine, the location register includes an identification bit and a bus bit associated with each of the plurality of direct memory access channels.
9. An apparatus configured to support a direct memory access transfer on a Peripheral Component Interconnect bus between a main memory element and an electronic device coupled to the Peripheral Component Interconnect bus, the apparatus comprising: controller means for receiving a direct memory access request from the electronic device coupled to the Peripheral Component Interconnect bus;
state means for receiving the direct memory access request from the plurality of controller means and for coordinating the direct memory access, the state means being coupled to the controller means; storage means for collecting data during the direct memory access transfer, the storage means being coupled to the state means; and
location means for determining whether the electronic device is coupled to the Peripheral Component Interconnect bus, the location means being coupled to the state means.
10. A computer system comprising
a main memory element;
a Peripheral Component Interconnect bus;
a plurality of electronic devices coupled to the Peripheral Component Interconnect bus, the plurality of electronic devices includes a first electronic device being capable of requesting a direct memory access transfer;
at least one control line coupled to the first electronic device; and
a bridge device coupled to said main memory element and further coupled to the first electronic device through the at least one control line, the bridge device enables the direct memory access transfer to be performed between the first electronic device and the main memory element.
11. The computer system according to Claim 10, wherein said plurality of direct memory access controllers of said bridge device are coupled to the first electronic device via a first direct memory access channel of a plurality of direct memory access channels.
12. The computer system according to Claim 11, wherein the state machine of the bridge device coordinates the direct memory access transfer by separating the direct memory access transfer into a memory cycle and an input/output cycle.
13. The computer system according to Claim 11, wherein the state machine of the bridge device coordinates the direct memory access transfer by initially determining whether the direct memory access transfer requested by the first electronic device is a memory read operation.
14. The computer system according to Claim 13, wherein if the direct memory access transfer is the memory read operation, the state machine prompts the bridge device to (i) gain ownership of the Peripheral Component Interconnect bus, (ii) collect data from the main memory element, (iii) transmit a direct memory access acknowledge signal to the first electronic device and (iv) perform a write cycle on the Peripheral Component Interconnect bus by placing the data and a dummy address onto the Peripheral Component Interconnect bus.
15. The computer system according to Claim 13, wherein if the direct memory access transfer is a memory write operation, the state machine prompts the bridge device to (i) gain ownership of the Peripheral Component Interconnect bus, (ii) transmit a direct memory access acknowledge signal to the first electronic device, (iii) collect data from the first electronic device and (iv) perform a write cycle on the Peripheral Component Interconnect bus by placing the data and an address supported by the main memory element onto the Peripheral Component Interconnect bus.
16. The computer system according to Claim 10, wherein the bridge device further includes a location register configured to indicate if the first electronic device is coupled to the Peripheral Component Interconnect bus.
17. The computer system according to Claim 16, wherein the location register, coupled to the state machine, includes an
identification bit and a bus bit associated with each of the plurality of direct memory access channels.
18. A computer system comprising
processing means for processing information;
memory means for storing said information;
bus means for transferring information between at least said processing means and said memory means, said bus means including a Peripheral Component Interconnect bus;
controller means for connecting said bus means to said processing means and said memory means, said controller means being coupled to said processing means and said memory means;
device means for performing a direct memory access transfer with said memory means, said device means being coupled to said bus means; and
bridge means, coupled to said controller means and said device means, for supporting said direct memory access transfer, said bridge means includes
direct memory access controller means for receiving a direct memory access request from said device means,
state means for receiving said direct memory access request from said controller means and to coordinate the direct memory access, said state means being coupled to said direct memory access controller means, and
storage means for collecting data from said memory means during a memory read operation of said direct memory access transfer and alternatively from said electronic means during a memory write operation of said direct memory access transfer, said storage means being coupled to said state means.
19. A method for performing a direct memory access transfer over a Peripheral Component Interconnect bus, the method
comprising the steps of:
(1) detecting a direct memory access request from a electronic device coupled directly to the Peripheral Component Interconnect bus; and
(2) servicing the direct memory access request by performing the direct memory access transfer between a memory element and the electronic device.
20. The method according to claim 31, wherein said separating step includes the steps of
determining whether said direct memory access request is for a direct memory access memory read, wherein if said direct memory access request is for said direct memory access memory read then, performing the following steps;
(a) obtaining ownership of the Peripheral Component Interconnect bus,
(b) collecting data from the main memory element into a storage element,
(c) transferring a direct memory access acknowledge signal to the electronic device, and
(d) performing an input/output write cycle by placing said data and a dummy address onto the Peripheral Component Interconnect bus.
21. The method according to claim 20, wherein if said direct memory access request is determined to be a direct memory access memory write during said determining step, said determining step further includes the steps of
(e) obtaining ownership of the Peripheral Component
Interconnect bus;
(f) transferring a direct memory access acknowledge signal to the electronic device;
(g) performing an input/output read cycle with a dummy address onto the Peripheral Component Interconnect bus;
(h) collecting data from the electronic device and storing said data within said storage element; and
(i) performing a write cycle with a memory address on the Peripheral Component Interconnect bus.
22. The method according to claim 20, wherein prior to the step (d), the method comprising the steps of:
determining whether a location of the electronic device has been previously identified, wherein if said location has been identified determining whether the electronic device is coupled to the Peripheral Component Interconnect bus, wherein
performing step (d) if the electronic device is coupled to the Peripheral Component Interconnect bus and setting appropriate bits within a location register to store a location of the electronic device for a subsequent direct memory access transfer if the electronic device is coupled to the Peripheral Component Interconnect bus, and alternatively
performing multiple input/output write cycles if the electronic device is coupled to an Industry Standard
Architecture bus.
23, The method according to claim 22, wherein after transferring said direct memory access acknowledge signal to the electronic device and before performing said input/output read cycle, the method comprising the steps of: determining whether a location of the electronic device has been previously identified, wherein if said location has been identified determining whether the electronic device is coupled to the Peripheral Component Interconnect bus, wherein
performing said input/ output cycle if the electronic device is coupled to the Peripheral Component Interconnect bus and setting appropriate bits within a location register to store a location of the electronic device for a subsequent direct memory access transfer if the electronic device is coupled to the Peripheral Component Interconnect bus, and alternatively
performing multiple input/output read cycles if the electronic device is coupled to an Industry Standard
Architecture bus.
24. A system comprising:
a memory element;
a multiplexed bus;
a direct memory access (DMA) device coupled to the
multiplexed bus; and
a bridge coupled to the multiplexed bus and the DMA device, the bridge device supports a direct memory access transfer between the memory element and the DMA device.
25. The system according to claim 24, wherein the
multiplexed bus includes a Peripheral Component Interconnect bus.
26. The system according to claim 24 further comprising a system controller coupled to both the memory element and the multiplexed bus to support communications between the DMA device and the memory element through the bridge.
27. The system according to claim 24, wherein the at least one control line coupled between the DMA device and the bridge is dedicated to support communications solely between the DMA device and the memory element.
28. The apparatus according to claim 1, wherein the multiplexed bus includes a Peripheral Component Interconnect bus.
29. The computer system according to claim 10, wherein the bridge device including:
a plurality of direct memory access controllers that receive the direct memory access request from the first electronic device;
a state machine coupled to said plurality of direct memory access controllers, the state machine coordinates the direct memory access transfer upon detecting that the plurality of direct memory access controllers received the direct memory access request; and
an internal storage element coupled to the state machine, the internal storage element collects data during the direct memory access transfer.
30. The computer system according to Claim 10 further comprising:
a central processing unit; and
a system controller coupled to the central processing unit and the main memory element, the system controller assisting to establish a communication path between the memory element and the first electronic device.
31. The method according to claim 19, wherein the servicing step includes the step of separating a direct memory access transfer into a memory cycle and an input/ output cycle.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU71125/96A AU7112596A (en) | 1995-09-26 | 1996-09-18 | A system and method for increasing functionality on the peripheral component interconnect bus |
| DE19681574T DE19681574T1 (en) | 1995-09-26 | 1996-09-18 | System and method for increasing functionality on the PCI bus |
| BR9610950A BR9610950A (en) | 1995-09-26 | 1996-09-18 | System of a method to increase the functionality on the peripheral component interconnection bus |
| GB9803706A GB2319642B (en) | 1995-09-26 | 1996-09-18 | A system and method for increasing functionality on the peripheral component interconnect bus |
| KR1019980702208A KR100271336B1 (en) | 1995-09-26 | 1996-09-18 | A system and method for increasing functionality on the peripheral component interconnect bus |
| HK98112384.2A HK1011228B (en) | 1995-09-26 | 1996-09-18 | A system and method for increasing functionality on the peripheral component interconnect bus |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/534,187 US5805842A (en) | 1995-09-26 | 1995-09-26 | Apparatus, system and method for supporting DMA transfers on a multiplexed bus |
| US08/534,187 | 1995-09-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1997014100A1 WO1997014100A1 (en) | 1997-04-17 |
| WO1997014100B1 true WO1997014100B1 (en) | 1997-06-26 |
Family
ID=24129034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1996/014939 Ceased WO1997014100A1 (en) | 1995-09-26 | 1996-09-18 | A system and method for increasing functionality on the peripheral component interconnect bus |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5805842A (en) |
| KR (1) | KR100271336B1 (en) |
| AU (1) | AU7112596A (en) |
| BR (1) | BR9610950A (en) |
| DE (1) | DE19681574T1 (en) |
| GB (1) | GB2319642B (en) |
| WO (1) | WO1997014100A1 (en) |
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| US4577313A (en) * | 1984-06-04 | 1986-03-18 | Sy Kian Bon K | Routing mechanism with encapsulated FCS for a multi-ring local area network |
| US5191657A (en) * | 1989-11-09 | 1993-03-02 | Ast Research, Inc. | Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus |
| JPH05114905A (en) * | 1991-04-08 | 1993-05-07 | Digital Equip Corp <Dec> | Treatment filtering of messages using single address and protocol table bridges |
| US5396602A (en) * | 1993-05-28 | 1995-03-07 | International Business Machines Corp. | Arbitration logic for multiple bus computer system |
| US5450551A (en) * | 1993-05-28 | 1995-09-12 | International Business Machines Corporation | System direct memory access (DMA) support logic for PCI based computer system |
| US5446869A (en) * | 1993-12-30 | 1995-08-29 | International Business Machines Corporation | Configuration and RAM/ROM control of PCI extension card residing on MCA adapter card |
| US5471590A (en) * | 1994-01-28 | 1995-11-28 | Compaq Computer Corp. | Bus master arbitration circuitry having improved prioritization |
| US5448558A (en) * | 1994-04-05 | 1995-09-05 | International Business Machines Corporation | Method and apparatus for managing packet FIFOS |
| US5524235A (en) * | 1994-10-14 | 1996-06-04 | Compaq Computer Corporation | System for arbitrating access to memory with dynamic priority assignment |
| US5542053A (en) * | 1994-11-30 | 1996-07-30 | International Business Machines Corporation | Bridge interface between two buses of a computer system with a direct memory access controller programmed by a scatter/gather programmer |
| US5557758A (en) * | 1994-11-30 | 1996-09-17 | International Business Machines Corporation | Bridge between two buses of a computer system that determines the location of memory or accesses from bus masters on one of the buses |
| US5642489A (en) * | 1994-12-19 | 1997-06-24 | International Business Machines Corporation | Bridge between two buses of a computer system with a direct memory access controller with accessible registers to support power management |
| US5495569A (en) * | 1994-12-30 | 1996-02-27 | Compaq Computer Corp. | Circuit for ensuring that a local interrupt controller in a microprocessor is powered up active |
| US5559968A (en) * | 1995-03-03 | 1996-09-24 | Compaq Computer Corporation | Non-conforming PCI bus master timing compensation circuit |
-
1995
- 1995-09-26 US US08/534,187 patent/US5805842A/en not_active Expired - Lifetime
-
1996
- 1996-09-18 DE DE19681574T patent/DE19681574T1/en not_active Withdrawn
- 1996-09-18 AU AU71125/96A patent/AU7112596A/en not_active Abandoned
- 1996-09-18 BR BR9610950A patent/BR9610950A/en not_active IP Right Cessation
- 1996-09-18 GB GB9803706A patent/GB2319642B/en not_active Expired - Fee Related
- 1996-09-18 KR KR1019980702208A patent/KR100271336B1/en not_active Expired - Fee Related
- 1996-09-18 WO PCT/US1996/014939 patent/WO1997014100A1/en not_active Ceased
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