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WO1997009790A1 - Systeme de decimation de signaux a vraisemblance maximale de reponse partielle (prml) - Google Patents

Systeme de decimation de signaux a vraisemblance maximale de reponse partielle (prml) Download PDF

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Publication number
WO1997009790A1
WO1997009790A1 PCT/US1996/002743 US9602743W WO9709790A1 WO 1997009790 A1 WO1997009790 A1 WO 1997009790A1 US 9602743 W US9602743 W US 9602743W WO 9709790 A1 WO9709790 A1 WO 9709790A1
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WO
WIPO (PCT)
Prior art keywords
circuit
signal
control circuit
prml
clock
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Ceased
Application number
PCT/US1996/002743
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English (en)
Inventor
David Hitchcox
Paul Shepherd
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Analog Devices Inc
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Analog Devices Inc
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Publication of WO1997009790A1 publication Critical patent/WO1997009790A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H21/00—Adaptive networks
    • H03H21/0012—Digital adaptive filters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
    • H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
    • H03H17/065—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer
    • H03H17/0664—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation

Definitions

  • This invention relates to a partial response maximum likelihood (PRML) channel signal processor and more particularly to such a signal processor which has reduced power requirements.
  • PRML partial response maximum likelihood
  • a recording head In magnetic recording devices, such as magnetic disks and tapes, a recording head is used to read and write information to and from a magnetic surface.
  • data In a typical rotating-based storage system, data is stored on magnetic disks in a series of tracks.
  • the read/write head detects variations in the magnetic orientation of the disk surface.
  • a pattern of external and internal fields are created as the head and recording surface are moved relative to each other. The patterns are similar to a series of bar magnetics of changing polarities. The polarity transitions are then readable as transitions in the magnetic flux at the recording surface.
  • the magnetic field of the storage surface In the read mode the magnetic field of the storage surface is detected and a voltage is induced in a coil proportional to the rate of change of the flux.
  • PRML channels such as partial response maximum likelihood (PRML) channels
  • PRML channels typically include, inter alia, an analog to digital converter (ADC) which converts incoming analog data signals from a storage medium to digital signals and a digital signal processor system which is comprised of a timing recovery loop, gain recovery loop and an adaptive filter circuit.
  • ADC analog to digital converter
  • the adaptive filter circuit shapes the data signal so that it conforms to the typical shape of the PRML signal to be detected.
  • the timing recovery loop also known as the phase control loop, adjusts the sampling phase of the data signal provided to the ADC and the gain recovery or control loop adjusts the gain of the data signal provided to the ADC.
  • the adaptive filter, timing recovery loop, and gain recovery loop are complex circuits which contain, among other things, many banks of delay registers.
  • the adaptive filter, timing recovery and gain recovery loops operate at the same frequency as the sampling clock which samples the incoming data signals so that each time the data signals are sampled all of the capacitors within the banks of registers are charged. It is known that the power dissipated in these circuits is proportional to the operating frequency of the circuits. Thus, since the clock sampling frequency which operates these circuits is very high, typically 125 MHz, the digital signal processing circuit and hence the PRML channel have significant power requirements.
  • This invention results from the realization that the power requirements of a PRML signal processor system and PRML channel are directly proportional to the operating frequency of its circuits and from the further realization that a truly power efficient PRML signal processor system and channel can be achieved by decreasing or decimating the frequency of operation of one or more of the adaptive filter, timing recovery loop and gain recovery loop.
  • This invention features a decimating PRML signal processor system for processing a PRML data signal which includes an adaptive filter circuit for receiving and shaping the data signal.
  • There is a clock circuit for providing clock signals for driving each of the circuits and a decimation controller for reducing the rate of the clock signals to at least one of the circuits to decrease the power required to operate the system.
  • an analog to digital converter for converting the data signal from analog to digital and providing the digital signal to the adaptive filter circuit.
  • the controller may include means for reducing the clock rate at the same level for each circuit.
  • the controller may include means for reducing the clock rate at different levels for each circuit.
  • the phase control circuit may include a mode selector for setting the phase control circuit to one of a tracking mode and an acquisition training mode.
  • the mode selector may interconnect the phase control circuit with the adaptive filter in the tracking mode and to the ADC in the acquisition training mode.
  • Fig. 1 is a schematic block diagram of the decimating PRML signal processor system according to this invention
  • Fig. IA is a more detailed schematic block diagram of the decimation controller of Fig. 1;
  • Fig. 2 is an analog PRML waveform illustrating the function of the phase control circuit of Fig. 1;
  • Fig. 3 is a schematic diagram of the input registers of a prior art phase control circuit;
  • Fig. 4 is a timing diagram depicting the operation of the prior art phase control circuit of Fig. 3;
  • Fig. 5 is a schematic diagram of the input registers of the phase control circuit of Fig. 1 according to this invention.
  • Fig. 6 is a timing diagram of the phase control circuit of Fig. 5;
  • Fig. 7 illustrates the operation of the gain control circuit of Fig. 1;
  • Fig. 8 is a schematic diagram of the input circuit of a prior art data control circuit
  • Fig. 9 is a timing diagram of the prior art gain control circuit of Fig. 8.
  • Fig. 10 is schematic diagram of the gain control circuit of Fig. 1 according to this invention.
  • Fig. 11 is a timing diagram of the gain control circuit of Fig. 10;
  • Fig. 12 depicts a data signal waveform and a standard PRML waveform illustrating the operation of the adaptive filter circuit
  • Fig. 13 is a schematic diagram of a prior art adaptive coefficient circuit
  • Fig. 14 is a timing diagram of the prior art circuit of Fig. 13;
  • Fig. 15 is a schematic diagram of the adaptive coefficient circuit of Fig. 1 according to this invention.
  • Fig. 16 is a timing diagram of the adaptive coefficient circuit of Fig. 15.
  • a partial response maximum likelihood (PRML) channel 10 for processing a read signal from a storage medium obtained by magnetic read head 12.
  • Magnetic read head 12 provides data signals read from the storage medium to a variable gain amplifier 14 which outputs the data signals to continuous time programmable filter 15.
  • Continuous time programmable filter 15 converts the incoming raw analog read signals to analog PRML signals of a predetermined order (e.g. PR4, EPR4) .
  • the PRML signals from continuous time programmable filter 15 are provided to analog to digital converter (ADC) 16 which samples the analog PRML signals at the system clock frequency, typically, 125 MHz, which clock signal is provided by a system sampling clock within voltage controlled oscillator (VCO) 18.
  • ADC analog to digital converter
  • Digital signals sampled at the clock frequency are provided from analog to digital converter 16 to finite impulse response (FIR) filter 22 within digital signal processing block 24 and to multiplexer 26 whose function is described below.
  • FIR filter 22 outputs over line 27 a multi-level PRML digital signal to Viterbi detector 28 which decodes the signal and outputs over line 29 a serial binary signal corresponding to the analog signals read by magnetic read head 12 from the storage disk.
  • the output of FIR filter 22 over line 27 is also provided to multiplexer 26.
  • the output of multiplexer 26 is provided to gain control circuit 30 and phase control circuit 32.
  • Phase control circuit 32 provides phase error feedback signals ⁇ T to digital to analog converter 33 which causes VCO 18 to adjust the sampling phase of ADC 16 to ensure that the analog read signals are being sampled appropriately.
  • This phase control technique is well known in the art and is often referred to as phase or timing recovery. See for example, U.S. Patent No. 4,890,299, entitled Fast Timing Acquisition for Partial-Response Signalling, issued December 26, 1989 and No. 5,341,249, entitled Disk Drive Using PRML Class IV
  • multiplexer 26 selects the signal from line 27 at the output of FIR filter 22 as the input to phase control circuit 32 in response to a signal on line 34 to multiplexer 26.
  • a signal is provided over line 34 to multiplexer 26 which causes multiplexer 26 to provide phase control circuit 32 with the output of analog to digital converter 16.
  • the signal enabling this selection of multiplexer 26 is typically called the acquisition signal and when this signal is used, the phase recovery loop is referred to as the acquisition phase recovery loop. This acquisition recovery loop is used to shorten the phase correction by locking to the phase of the preamble signal which closely matches the phase of the data signals to be read in the tracking mode.
  • Gain control circuit 30 provides a gain error feedback signal AP over line 35 to variable gain amplifier 14 to adjust the gain of the data signal so that its amplitude matches the amplitude of the predetermined PRML signal which is programmed by the user.
  • the gain control technique is well known in the art. See, for example, U.S. Patent Nos. 4,890,299 and 5,341,249 and the publication "A PRML System for Digital Magnetic Recording".
  • Adaptive coefficient circuit block 36 receives from gain control circuit 30 a gain error signal, e k , which is used to calculate AP within gain control circuit 30, and a slope signal, sign ⁇ k , from FIR filter 22.
  • the adaptive coefficients, h k are calculated and are provided over line 37 to coefficient adjust circuit 38 within FIR filter 22.
  • FIR circuit 22 Within FIR circuit 22, as is well known in the art, are a number of multipliers which adjust the output of FIR filter 22 according to the values of coefficients h k in order to shape the FIR filter output signal in accordance with the desired PRML signal. See, for example, U.S. Patent No. 5,341,249 and publication "A PRML System for Digital Magnetic Recording".
  • the adaptive coefficient circuit block 36 and the coefficient circuit 38 of FIR filter 22 form in conjunction an adaptive filter circuit.
  • Phase control circuit 32, gain control circuit 30 and adaptive coefficient circuit 36 all operate under the control of a clock signal.
  • Adjustable clock frequency circuit 40 which receives the system clock frequency from VCO 18, is capable of outputting the system clock frequency and virtually any (n) multiple of the system clock frequency to gain and phase control circuits 30 and 32 and adaptive coefficient circuit 36 to reduce the power dissipated by these circuits, digital signal processor circuit 24, and the overall PRML channel 10.
  • decimation controller 42 which includes a switch 44 (actually comprised of three individual switches as shown in Fig. IA) that when switched into connection with terminal 46, under the control of a decimation control signal over line 47, is exclusively in connection with the system clock.
  • gain control circuit 30, phase control circuit 32, and adaptive coefficient circuit 36 are all operated in accordance with prior art systems at the system clock sampling frequency.
  • reduced frequency clock 40 is capable of operating all three of the gain control circuit 30, phase control circuit 32 and adaptive coefficient circuit 36 at reduced frequencies to reduce the power dissipated in these circuits. Or, each of these circuits can be operated at the same reduced frequency, each at a different reduced frequency, or two at one reduced frequency and the other at another reduced frequency. Circuit 40 is even capable of operating any one or two of the circuits at the system clock frequency and one or two of the others at a reduced frequency.
  • Decimation controller 42 is shown in more detail in Fig.
  • IA to include three individual switches 44a-c, interconnected at a first end with phase control circuit 32, gain control circuit 30 and adaptive coefficient circuit 36, respectively, and at a second end selectively interconnected with terminals 46a-c or terminals 48a-c.
  • the positions of switches 44a-c are individually controlled by control signals supplied over lines 47a-c.
  • Terminals 48a-c include a number of sub terminals, such as 48a'-48c', which enable the interconnection of the switches to various reduced frequency clock signals CK/2...CK/n.
  • this invention which reduces the amount of power consumed by phase control circuit 32, gain control circuit 30 and adaptive coefficient circuit 36, is achieved by operating each of these circuits with two clock signals, CK, and CK 2 , having an increased period (or reduced frequency) which is a multiple of the system clock period, wherein clock signal CK 2 is delayed by one system clock period with respect to clock signal CK,
  • reduced clock circuit 40 generates pairs of reduced frequency clock signals (CK, and CK 2 ) at frequencies CK/2...CK/n and these signals are provided to terminals 48a-48c.
  • system clock signals CK are provided to terminals 46a-c. Therefore, switches 44a-c can be individually connected to any pair of reduced frequency clock signals or to the pair of system clock signals to operate each circuit individually at either a reduced frequency or at the system clock frequency, respectively.
  • Clock logic circuit is typically programmed to operate the circuits at predetermined frequency but the operating frequencies of the circuits may be adjusted by the user.
  • phase control circuit 32 gain control circuit 30, and adaptive coefficient circuit 36, the previous design of their input registers, and the design of their input registers according to this invention is described in turn below.
  • PRML waveforms described below are PR4 waveforms this is not a limitation of this invention as other order PRML signals could also be utilized.
  • the invention is described below using clock frequencies reduced by 50% (i.e. CK/2) and this is also not a limitation of this invention as any reduced frequency which is a multiple of the system clock frequency may be utilized as long as the circuits still properly perform their function.
  • Phase control circuit 32 compares adjacent samples taking proper account of sign, such as 52 D 0 and 53 D, to see if they are equal. If they are equal then this indicates that the sampling frequency is in phase with waveform 50 and is sampling the PR4 signal properly at points located symmetrically about peak 60.
  • sample point 53 D has a value of nineteen, (twenty- four corresponds to peak value 60) , while sample point 52 D 0 has a value of twenty.
  • the sampling frequency is adjusted accordingly by a phase error signal ⁇ T generated by phase control circuit 32.
  • each pair of sample points are compared and are used to generate phase error signal ⁇ T. That is, signals 52 D 0 and 53 D,, 53 D j and 54 D 2 , 54 D 2 and 55 D 3 , 55 D 3 and 56 D 4 and 56 D 4 and 57 D 5 ...etc. are compared and used to generate phase error signal ⁇ .
  • Phase control circuit 32' configured according to prior art systems to operate exclusively at the system clock sampling frequency, is shown in Fig. 3 to include a set of input registers 70 and 72, for generating the Y (n) (sign Y (n) ) and Y (n - D (sign (n .i ) ) signals on output lines 74 and 76, respectively, from input signal D n on input line 78.
  • Signal Dn is actually the output in the tracking mode from FIR filter 22, Fig. 1, provided over line 27.
  • the sign signals are simply the most significant bits of the samples.
  • Signal Y (n) is the present sample D n output from delay register 70 and sign (Y (n) ) is the polarity (+ or -) of that sample.
  • Signal Y ⁇ is the previous sample D (n ., ) which was delayed by delay register 72 and sign is the polarity of that sample.
  • These delay registers and the remaining circuitry in phase control circuit 32' operate under the control of the system clock frequency by a clock signal supplied on input line 82 tied to both delay registers 70 and 72 which causes signals Y (n) (sign Y (n) ) and Y (n ., ) (sign (Y f c. 1) ) to be generated every clock cycle.
  • There signals are used to calculate the phase error signal ⁇ T according to the following equation:
  • Timing diagram 90 depicts how the incoming samples D 0 - D 5 , Fig. 2, to phase control circuit 32', Fig. 3, are used to calculate a phase error signal ⁇ T every cycle of the system sample clock.
  • Signals D 0 - D 5 of waveform 92 are typically 6 bit digital words representing the values of samples of data from waveform 50, Fig. 2, which are provided to phase control circuit 32' at the system clock sample rate shown in waveform 94.
  • Waveform 96 depicts the Y (n) (sign Y (n) ) output on line 74, Fig. 3, after each clock cycle and waveform 98 depicts the Y (D . ⁇ (sign Y (D ., ) ) output on line 76, Fig.
  • Waveform 100 illustrates that the phase error signal ⁇ T is generated at every clock cycle and it is generated for each adjacent sample (i.e. D 0 and D,, Di and D 2 , D 2 and D 3 , D 3 and D 4 , and D 4 and D 5 ) .
  • Phase control circuit 32, Fig. 5, is shown to include a set of input registers 110 and 112 whose operation is controlled by separate clock signals CK, and CK 2 on input lines 114 and 116 with frequencies lower than the system clock sampling frequency CK and delayed one system clock period with respect to each other.
  • Input signal D n is introduced to both delay registers 110 and 112 on input line 118, output signals Y (n) (sign (Y (n) ) are output from delay register 112 over line 120 and signals Y ⁇ ., ) (sign (Y (n ., ) ) are output from delay register 110 over output line 122.
  • Timing diagram 130 illustrates the timing of clock signals CK, and CK 2 according to this invention and how they effect the outputs of delay registers 110 and 112, Fig. 5 as well as the error signal outputs ⁇ T from phase control circuit 32.
  • Sample data waveform 132 including samples D 0 -
  • D 5 , Fig 2 is sampled at the system clock frequency depicted by waveform 134.
  • phase control circuit 32, Fig. 5 is operated at a reduced frequency it does not utilize each data sample D 0 - D 5 in calculating the phase error signal ⁇ T.
  • Delay register 110, Fig. 5, is operated by clock signals CK,, waveform 136, and delay register 112, Fig. 5, is operated by clock signals CK 2 , waveform 138.
  • clock signals CK, and CK 2 operate at one half the system clock sampling frequency and are offset in time from each other by one period of the system clock. Because the clock frequency operating phase control circuit 32 is effectively reduced or decimated by 50%, the update rate of the phase error calculations is similarly reduced.
  • phase error signal ⁇ T is calculated only 50% of the time. As illustrated by waveform 144 ⁇ T signals generated only by sample pairs D 0 and D,, D 2 and D 3 , and D 4 and D 5 are calculated. Since, in this example, the frequency of operation of phase control circuit 32 is reduced by 50%, so is the power consumed by the circuit.
  • GAIN CONTROL CIRCUIT The operation of the gain control circuit 30, Fig. 1, is best illustrated by observing waveforms 150 and 152, Fig. 7, which represent, respectively, the actual analog data signal introduced to analog to digital converter 16 and a desired analog data read signal during preamble.
  • Gain control circuit 30 is used to provide a feedback error correction signal AP to variable gain amplifier 14 to adjust waveform 150 so that its amplitude at the various sample points, taken at the system clock sampling frequency, are equivalent to the amplitude of the desired analog PRML waveform 152.
  • Sample points 153 YY,, 154 YY 2 , 155 YY 3 , 156 YY 4 and 157 YY S are shown not to coincide with desired sample points 153'-157'.
  • gain control circuit 30 accordingly adjusts variable gain amplifier 14 with an error correction signal AP to amplify waveform 150 such that it has the desired amplitude.
  • Prior art gain control circuit 30' configured according to prior art systems to operate exclusively at the system clock sampling frequency, is shown in Fig. 8 to include an input circuit 160 which includes input registers 162 and 164 and gain logic circuit 166.
  • Signal YY tract (sign YY n ) is input to delay register 162 over input line 168.
  • the output of delay register 162 is the delayed sample YY n ' (sign YY n ') , which is input to gain logic circuit 166.
  • Gain logic circuit 166 calculates signal gain error signal e k and provides that signal to delay register 164 which outputs on line 170 the e k error signal. Input registers 162 and 164 are operated by the system clock supplied over line 172. Within gain control circuit 30' the following gain error algorithm is implemented using error signal e k to generate the gain error correction signal Av:
  • Timing diagram 200 depicts the timing of obtaining samples YY n , (sign YY n ') and the calculation of error signal e k and gain error correction signal AP .
  • Sample waveform 202 which is output from FIR filter 22, Fig. 1, includes an output of digital 6 bit samples YY,...YY 5 taken at the system clock sampling frequency which is depicted by waveform 204.
  • Waveform 206 shows that error signals e k ,...e k4 are obtained at the onset of each clock signal and used in the calculation of the gain error correction signal AP, waveform 207, at each clock cycle.
  • Gain control circuit 30, Fig. 10 is configured according to the present invention to operate at a fraction of the normal clock sample rate.
  • Circuit 30 includes input delay registers 220 and 222 with gain logic circuit 224 interconnected therebetween.
  • Signal YY n (sign YY n ) is input to delay register 220 over line 226 at the first clock signal CK, supplied over line 228.
  • Delay registers 220 outputs a delayed signal YY n ' (sign YY n ') to gain logic 224 which outputs error signal e k to delay register 222 driven by a second clock signal CK 2 supplied over line 230.
  • Delay register 222 outputs over line 232 the gain error correction signal AP provided to variable gain amplifier 14, Fig. 1.
  • Clock signals CK,, CK 2 are operated at a fraction of the system clock sampling frequency which, as demonstrated below, reduces the update rate of the gain error calculations and hence the power consumed by gain control circuit 30.
  • Timing diagram 240 illustrates how using the present invention which reduces or decimates the clock signal operating gain control circuit 30 does not utilize all of the sample data output from the FIR filter 22 to generate the error correction signal AP .
  • samples used in calculating AP are taken at one half the normal frequency or rate, thereby reducing the power consumed by gain circuit 30 by one half.
  • Data signal waveform 242 includes a number of 6 bit data samples YY 0 - YY 5 which are output from FIR filter 22, Fig. 1, at the system clock frequency shown by waveform 244.
  • Clock waveforms CK, 246 and CK 2 248 which, in this example, operate at one half the system clock frequency, are delayed relative to one another by one clock period of waveform 244.
  • clock signals CK, and CK 2 respectively operate delay registers 220 and 222 of Fig. 10.
  • Clock signal CK is used to cause delayed sample YY n ' to be output from delay register 220, Fig. 10, at the rising edge of each CK, clock signal and to generate the error signal e k corresponding to sample YY n as indicated by waveform 250. Since this frequency is half of the system clock frequency, (waveform 244) only every other data sample, in this case YY 0 , YY 2 , are YY 4 are obtained by gain control cijrcuit 30.
  • Waveform 252 illustrates that at the leading edge of every CK 2 clock signal, the gain error correction signal AP for each sample (YY 0 .
  • YY 2 , and YY 4 is calculated and generated. Because delay registers 220, 222 are operated at half the clock frequency only half the samples taken by analog to digital converter 16, Fig. 1, are used by the gain control circuit 30 to calculate and generate a gain error correction signal AP, thus, decreasing the amount of power required to operate gain control circuit 30 by one half.
  • Analog PRML waveform 260 is sampled at sample points 262 D 0 , 263 D,, 264 D 2 , 265 D 3 , 266 D 4 and 267 D 5 .
  • the gain and phase control circuits are used to adjust the sampling phase to ensure that sampling is occurring at the proper portion of the incoming PRML waveform and that the gain of the incoming PRML waveform is at the appropriate level, respectively.
  • Adaptive filtering operates to shape the PRML incoming waveform so that it conforms to the shape of a predetermined PRML waveform indicated by waveform 270.
  • adaptive coefficients within adaptive coefficient circuit 36, Fig. 1 are generated and output to coefficient update adjust circuit 38 within FIR filter 22 to adjust the output of FIR filter 22 so that its output waveform does correspond to the expected PRML wave shape.
  • h k are the new coefficients, h k ., are the previous coefficients
  • ⁇ is the loop gain
  • e k is the error signal from gain control circuit 30
  • sign u k is the slope signal from FIR filter 22.
  • the h k+1 adaptive coefficients from logic 286 are supplied to delay register 288 which, after a delay, supplies the adaptive coefficients h k over line 290 to coefficient adjust circuit 38 within FIR filter 22 to provide appropriate shaping of the waveform.
  • Timing diagram 300 depicts how the e k and sign u k data samples are generated each system clock cycle as indicated by waveform 302.
  • System clock waveform 304 shows that at the leading edge of each clock signal, the e k and sign u k samples are taken.
  • Adaptive coefficient waveform 306 depicts that at the leading edge of each clock signal following the signal cycle which obtained the e k and sign u k data samples the h k+1 coefficients are generated and output.
  • the updated coefficients, h k are available one clock cycle later over line 290 as indicated by waveform 307.
  • adaptive coefficient circuit 36 includes input registers 310 and 312 driven by a reduced clock frequency signal CK, provided over line 314.
  • Delay registers 310 and 312 provide to logic circuit 316 the e k and sign u k signals from gain control circuit 30 and FIR filter 22, Fig. 1, respectively.
  • Delay register 318 is driven by a second clock signal CK 2 , provided over line 319, operating at the same reduced frequency as CK,except it is delayed relative to CK, by the equivalent of one normal clock period of CK waveform 304, Fig. 14.
  • Timing diagram 320 depicts how adaptive coefficients h k are output less often with circuit 36, Fig. 15, than with circuit 36', Fig. 13.
  • Waveform 322 depicts data signals e k0 and signup - ek 5 and signup.
  • Clock CK, waveform 326 operates, in this example, at one half of the system clock frequency depicted as waveform 324.
  • clock waveform 326 data samples e k and sign u k are output from delay registers 310 and 312.
  • waveform 330 only every other data sample, i.e.
  • Clock waveform CK 2 328 is used for timing the output of the adaptive coefficients h k .
  • the adaptive coefficients h k are generated, waveform 332. Because only every other data sample is utilized, only the adaptive coefficients h k for every other data sample are output thereby reducing the power consumed by 50% as compared to prior art adaptive coefficient circuit 36, Fig. 13.
  • Each of the circuits 30, 32 and 36 could by operated at the system clock frequency by providing the system clock signals to both the CK, and CK 2 inputs of these circuits.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

Système (10) de décimation de signaux PRML destiné à traiter un signal de données PRML et comprenant: un circuit de filtre adaptatif (22) destiné à recevoir et à mettre en forme le signal de données; un circuit de commande de gain (30), réagissant au circuit de filtre adaptatif (22), destiné à régler le gain du signal de données; un circuit de commande de phase (32), réagissant au circuit de filtre adaptatif, destiné à régler la phase du signal de données; un synchronisateur (40) produisant des signaux commandant chacun des circuits; et un contrôleur de décimation (42) destiné à réduire la cadence des signaux d'horloge destinés à au moins un des circuits afin de réduire la puissance requise pour le fonctionnement du système.
PCT/US1996/002743 1995-09-06 1996-03-01 Systeme de decimation de signaux a vraisemblance maximale de reponse partielle (prml) Ceased WO1997009790A1 (fr)

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US52405595A 1995-09-06 1995-09-06
US08/524,055 1995-09-06

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
EP1111606A1 (fr) * 1999-12-20 2001-06-27 Fujitsu Limited Appareil d'ajustement d'horloge pour un système de reproduction de données et un appareil ayant un système de reproduction de données comportant un tel appareil d'ajustement d'horloge
GB2371695A (en) * 2000-12-07 2002-07-31 Ubinetics Ltd Signal processing

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Title
IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 1995, Digest of Technical Papers, RICHETTA et al., "A 16MB/s PRML Read/Write Data Channel", pages 78-79. *
IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 29, No. 12, December 1994, UEHARA et al., "A 100 MHz A/D Interface for PRML Magnetic Disk Read Channels". *
IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, Vol. 10, No. 1, January 1992, CIDECIYAN et al., "A PRML System for Digital Magnetic Recording", pages 38-56. *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1111606A1 (fr) * 1999-12-20 2001-06-27 Fujitsu Limited Appareil d'ajustement d'horloge pour un système de reproduction de données et un appareil ayant un système de reproduction de données comportant un tel appareil d'ajustement d'horloge
US6977879B1 (en) 1999-12-20 2005-12-20 Fujitsu Limited Apparatus for adjusting phase of clock signal based on phase error calculated from sampled values of readout signal
GB2371695A (en) * 2000-12-07 2002-07-31 Ubinetics Ltd Signal processing
WO2002047258A3 (fr) * 2000-12-07 2003-09-12 Ubinetics Ltd Traitement de signal
GB2371695B (en) * 2000-12-07 2005-02-16 Ubinetics Ltd Signal processing

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