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WO1997009673A1 - Transfert de code a un ordinateur sans acceder a une ram - Google Patents

Transfert de code a un ordinateur sans acceder a une ram Download PDF

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Publication number
WO1997009673A1
WO1997009673A1 PCT/US1996/014082 US9614082W WO9709673A1 WO 1997009673 A1 WO1997009673 A1 WO 1997009673A1 US 9614082 W US9614082 W US 9614082W WO 9709673 A1 WO9709673 A1 WO 9709673A1
Authority
WO
WIPO (PCT)
Prior art keywords
register
cpu
instruction
input element
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1996/014082
Other languages
English (en)
Other versions
WO1997009673A9 (fr
Inventor
David L. Paulsen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Metricom Inc
Original Assignee
Metricom Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/566,877 external-priority patent/US5664194A/en
Application filed by Metricom Inc filed Critical Metricom Inc
Publication of WO1997009673A1 publication Critical patent/WO1997009673A1/fr
Publication of WO1997009673A9 publication Critical patent/WO1997009673A9/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping

Definitions

  • This invention relates to techniques for starting computer systems and more particularly to a method for downloading executable code to a computer which is not provided with conventional boot code autonomous from the central processing unit.
  • Flash memory devices come in at least two forms —bulk erase, and boot-block.
  • Bulk erase flash devices must be erased in toto.
  • the device In order for a device using a bulk erase flash memory device to permit the consumer to update its stored program, the device must first erase its entire stored program, and then re-program it. If the process is interrupted after erasure but prior to enough of the stored program to be programmed (typically an interval of many seconds) , the device is rendered inoperable. Furthermore, because the boot program has been erased, the device cannot be reloaded.
  • Boot block flash memory devices have been devised to address this problem. In these devices, a portion of the memory is separately erasable, permitting a boot program to be stored there. Unfortunately, boot block flash memory devices are expensive. In addition, they require that the memory device be pre-programmed prior to fabrication, which adds manufacturing cost to the device.
  • a start-up mode after reset whereby boot- up instructions are by default always accepted directly from an external source.
  • the device may comprise a gate array (GA) which is connected directly via a serial port to a receiving or input device, to receive program code for transfer directly as instructions to a microprocessor-type central processing unit.
  • the central processing unit is part of a computer controlled device containing a microprocessor, memory (a RAM) , and typically a bulk erase flash memory device, the flash memory device being unprogrammed when the computer controlled device is fabricated originally.
  • the gate array directly monitor bits received via the serial port from the input device and shifts them into a local register from which bytes or words are loaded directly into the CPU as instructions.
  • a boot sequence is thereby accepted in this manner to load random access memory of the free-running CPU which thereafter can control transfer of additional executable code or load a permanent boot sequence into bulk erase (nonvolatile) flash memory.
  • the invention can be incorporated into a wireless modem/packet terminal node controller.
  • the input device may be a coupling to an external computer system, typically a serial input.
  • Figure 1 is a block diagram of the system having a CPU, flash memory, RAM, gate array, serial port and receiving device, according to the invention.
  • Figure 2A is a schematic of a first version of circuitry inside the gate array which, in conjunction with the data being shifted in, forms the boot loader.
  • Figure 2B is a schematic of a second version of circuitry inside the gate array which, in conjunction with the data being shifted in, forms the boot loader.
  • FIG. 1 is a flowchart illustrating the sequence of operations according to the invention.
  • a computer-based system 10 such as a terminal node controller
  • the CPU 12, flash memory 14, RAM 16, and gate array 18 are connected to a data bus 24 and an address bus 26.
  • the gate array is coupled to the serial port 20 which in turn is coupled to receiving device 22.
  • the receiving device is for example a serial connector.
  • the gate array 18 has data i/o, address input and control input to/from the CPU 12, and a serial input line 28 and a control line 30.
  • FIG. 2A there is shown a schematic diagram of a first version of the gate array 18.
  • a serial I/O section 32 There is a serial I/O section 32, a receiving register section 34, and a CPU instruction control section 36.
  • timing circuitry 38 is provided to automatically terminate the default boot sequence in the event no valid request for instruction is received.
  • FIG. 2B there is shown a schematic diagram of a second version of the gate array 18.
  • a serial I/O section 132 receives serial data from a serial I/O section 132 and a serial data from a serial data bus 136.
  • no timing circuitry is provided to automatically terminate the default boot sequence in the event no valid request for instruction is received.
  • An external "push" signal 138 is provided which must be present to activate and maintain the boot sequence.
  • Step A Upon reset or power up (Step A) , the "virgin flash" mode is initiated (Step B) and the gate array looks for instruction requests from the CPU 12 (Step C) .
  • the gate array waits for about 16 ms to determine if a valid instruction request is received.
  • the "push" signal 138 In the alternative embodiment of Fig. 2B, the "push" signal 138 must remain asserted throughout the "virgin flash” mode. These alternative functions control the exit mechanism.
  • the receiving register section 134 routinely accepts serial data each cycle from the serial port 20. Each cycle the register is checked to see if it is full (Step E) . If not, a filler instructions, such as a No-op, a jump-to-self instruction or equivalent instruction, is returned to the CPU (Step F) . If it is full, the content of the virgin register is sent to the CPU as an instruction (Step G) and the register is cleared for receipt of the next stream of bits to form instructions. (A "one" bit is sent via the serial port as a start bit for the beginning of each instruction bit stream.)
  • the invention allows a CPU to execute instructions directly from external sources totally bypassing local memory. It is noteworthy that the instructions are executed one at a time as received, not waiting for an accumulation of a series of instructions, as in the case of conventional front-panel loading of boot instructions. This invention could even be used in applications of computer systems which have no RAM.
  • the invention could also be used in connection with a parallel input port by appropriate choice of an input register to receive and output data in parallel, e.g., a dual- port parallel register. What is important is a start-up mode after reset which is the acceptance of instructions directly from an external source.
  • the invention can be used in a number of applications, such as loading BIOS's into PC's; updating code in PDA's.

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)

Abstract

Dispositif comportant un mode de mise en marche après remise à zéro, de telle sorte que les instructions d'amorçage sont, par défaut, toujours acceptées directement d'une source extérieure. Le dispositif comporte une matrice de portes (18), reliée directement par un port série (20) à un dispositif d'entrée (22), pour recevoir un code de programme destiné à être transféré directement à titre d'instructions à une unité de traitement (UC) (12). L'UC fait partie intégrante d'un dispositif géré par ordinateur (CCD) comportant un microprocesseur, une mémoire à accès aléatoire (RAM) (16), et une mémoire flash (14), cette dernière étant non programmée lorsque le CCD est fabriqué. Lorsque le CCD commence à être mis sous tension, un mode spécial de fonctionnement apparaît, selon lequel la matrice de portes (18) contrôle directement les bits reçus et les déplace vers un registre local, à partir duquel les multiplets sont chargés dans l'UC (12) en tant qu'instructions. Une séquence d'amorçage peut ainsi charger la RAM (16) de l'UC (12), qui peut ensuite commander le transfert d'un code exécutable additionel de chargement d'une séquence permanente d'amorçage dans la mémoire flash (14) (non volatile) à effacement en bloc.
PCT/US1996/014082 1995-09-07 1996-09-03 Transfert de code a un ordinateur sans acceder a une ram Ceased WO1997009673A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US300095P 1995-09-07 1995-09-07
US60/003,000 1995-09-07
US08/566,877 1995-12-04
US08/566,877 US5664194A (en) 1995-12-04 1995-12-04 Method for autonomously transferring code to a computer without accessing local memory by the central processing unit

Publications (2)

Publication Number Publication Date
WO1997009673A1 true WO1997009673A1 (fr) 1997-03-13
WO1997009673A9 WO1997009673A9 (fr) 1997-04-17

Family

ID=26671141

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/014082 Ceased WO1997009673A1 (fr) 1995-09-07 1996-09-03 Transfert de code a un ordinateur sans acceder a une ram

Country Status (1)

Country Link
WO (1) WO1997009673A1 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6267294B1 (en) * 1998-09-11 2001-07-31 Robotic Vision Systems Inc. Method of operating a charge coupled device in an accelerated mode, and in conjunction with an optical symbology imager
US7015809B1 (en) 2002-08-14 2006-03-21 Skipper Wireless Inc. Method and system for providing an active routing antenna
US7042394B2 (en) 2002-08-14 2006-05-09 Skipper Wireless Inc. Method and system for determining direction of transmission using multi-facet antenna
US7515544B2 (en) 2005-07-14 2009-04-07 Tadaaki Chigusa Method and system for providing location-based addressing
US7610050B2 (en) 2002-08-14 2009-10-27 Tadaaki Chigusa System for mobile broadband networking using dynamic quality of service provisioning
US7778149B1 (en) 2006-07-27 2010-08-17 Tadaaki Chigusa Method and system to providing fast access channel
US8160096B1 (en) 2006-12-06 2012-04-17 Tadaaki Chigusa Method and system for reserving bandwidth in time-division multiplexed networks

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5325529A (en) * 1990-05-18 1994-06-28 Compaq Computer Corporation External boot information loading of a personal computer
US5408624A (en) * 1990-11-09 1995-04-18 Ast Research, Inc. Method and apparatus for down-loading instructions from a host computer system to a memory in a peripheral controller for execution by a core microprocessor in the peripheral controller
US5444861A (en) * 1992-06-01 1995-08-22 United Technologies Corporation System for downloading software

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5325529A (en) * 1990-05-18 1994-06-28 Compaq Computer Corporation External boot information loading of a personal computer
US5408624A (en) * 1990-11-09 1995-04-18 Ast Research, Inc. Method and apparatus for down-loading instructions from a host computer system to a memory in a peripheral controller for execution by a core microprocessor in the peripheral controller
US5444861A (en) * 1992-06-01 1995-08-22 United Technologies Corporation System for downloading software

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6267294B1 (en) * 1998-09-11 2001-07-31 Robotic Vision Systems Inc. Method of operating a charge coupled device in an accelerated mode, and in conjunction with an optical symbology imager
US7015809B1 (en) 2002-08-14 2006-03-21 Skipper Wireless Inc. Method and system for providing an active routing antenna
US7042394B2 (en) 2002-08-14 2006-05-09 Skipper Wireless Inc. Method and system for determining direction of transmission using multi-facet antenna
US7610050B2 (en) 2002-08-14 2009-10-27 Tadaaki Chigusa System for mobile broadband networking using dynamic quality of service provisioning
US7515544B2 (en) 2005-07-14 2009-04-07 Tadaaki Chigusa Method and system for providing location-based addressing
US7778149B1 (en) 2006-07-27 2010-08-17 Tadaaki Chigusa Method and system to providing fast access channel
US8160096B1 (en) 2006-12-06 2012-04-17 Tadaaki Chigusa Method and system for reserving bandwidth in time-division multiplexed networks

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