WO1997007581A1

WO1997007581A1 - Static var compensator

Info

Publication number: WO1997007581A1
Application number: PCT/GB1996/001935
Authority: WO
Inventors: David John Young; Bjarne Reinholdt Andersen
Original assignee: GEC Alsthom Ltd
Current assignee: GE Power UK
Priority date: 1995-08-11
Filing date: 1996-08-09
Publication date: 1997-02-27
Anticipated expiration: 1998-02-11
Also published as: GB2304240B; GB2304240A; GB9516495D0; AU6745996A

Abstract

The invention provides means and a method of reducing the stresses on a switching device used to interrupt capacitive current in a static var compensator for electrical systems. During the normal process of opening a switch at zero currents, a high charge is trapped on the series capacitor in the compensator. After a further half cycle the applied voltage and the capacitor voltage are additive imposing a voltage exceeding twice the peak system voltage on the switching device. According to the invention, the compensator includes a current-limiting inductor and control means arranged to perform a sequence of switching operations on the thyristor thereby to cause an at least partly discharged condition of the capacitor means to coincide with a zero-current state of the series circuit. Preferably, the thyristor is switched OFF at zero current, then ON after a delay, following which the capacitor resonates with the current-limiting inductor and, at a point at which the capacitor voltage is near zero and the current is near zero, the thyristor is switched OFF again, leaving little or no offset on the blocked valve voltage. The blocking sequence may include more than one opening and closing operation before the final opening operation at the coincidence point.

Description

STATIC VAR COMPENSATOR Background of the Invention This invention relates to static var (volt-amp reactive) compensators for use in controlling vars and regulating the supply voltage in, for example, high-voltage supply systems. Static var compensators are known in which a series circuit comprising a capacitor bank, a switch and a current limiting reactor is connected across the supply system, the switch being controlled to switch the capacitor bank into or out of circuit according to the demands of the system. In a typical three-phase system three such series circuits may be connected in a delta arrangement.

The energy levels involved often require the series circuits to take currents of thousands of amperes and the switches to withstand voltage levels of perhaps twenty thousand volts or more. Where, as is common, thyristor valves are employed as the switch, it is not presently possible to obtain thyristors individually rated for these conditions and consequendy the switch comprises a thyristor valve assembly consisting of a number of thyristors in series (each series device or parallel group of devices being known as a 'level') and, in certain cases, a number of paths in parallel. Thyristors of the type in question are expensive and it is desirable to limit the numbers as far as possible. However, it is essential that the thyristors be able to withstand the voltage levels that may arise during switching operations, which voltages may be considerably in excess of those obtaining in steady state conditions, especially as a result of the turn-off or blocking operation.

An object of the present invention is to control the switch in such a manner as to limit the voltage to which the switch may be subjected in a blocking (turn-off) operation.

Summary of the Invention In accordance with a first aspect of the invention, there is provided a static var compensator for connection to an AC supply, the compensator including at least one series circuit comprising capacitor means, inductive reactor means and switching means, the switching means being provided to switch the capacitor means and inductive reactor means into or out of circuit, the compensator including control means for performing a turn-off operation on said switching means, said control means being to this end arranged to perform a sequence of switching operations on said switching means thereby to cause an at least partly discharged condition of the capacitor means to coincide with a zero-current state of the series circuit.

The control means may be arranged to open the switching means at or near to a zero-current state ofthe series circuit, close the switching means after a delay, and re-open the switching means at said coincidence condition.

The control means may be arranged to close the switching means after a delay of less than a half-cycle at the AC system frequency, and preferably after a delay of less than a quarter-cycle.

When the switching means is closed, current flow in the series circuit being subject to resonance ofthe series circuit components, the control means may be arranged to permit one or more pulses of resonant current of alternating polarity to occur before the switching means is reopened.

The resonant frequency ofthe series circuit, taking into account inductive reactance associated with the AC system to which the compensator is connected, may be greater than the AC system frequency, the delay period may be approximately 0.2 times the period of the

AC system frequency and the control means may be arranged to permit two pulses of resonant current of alternating polarity to occur before the switching means is reopened.

The electronic switching means may comprise thyristors.

The compensator may comprise a three-phase delta-connected arrangement of said series circuits. Alternatively, it may comprise a three-phase star-connected arrangement of said series circuits having a star-point connected to the star-point of a three-phase supply system. It is also possible to have a star-connected compensator in which the star-point is isolated, two of the star-connected arms comprising said series circuits and the third arm comprising a said series circuit but without the switching means. The control means may be arranged to open and, following a delay period, close the switching means more than once during said turn-off operation.

In accordance with a second aspect of the invention, there is provided a method of controlling a static var compensator comprising at least one series circuit of capacitor means, inductive reactor means and switching means, the switching means being provided to switch the capacitor means and inductive reactor means into or out of circuit, in which method the capacitor means Ls switched out of circuit by opening the switching means at or near to a zero-current state of the series circuit, the switching means is closed after a delay period, and the switching means is re-opened at or near to a zero-current state of the series circuit, the delay period being such as to cause an at least partly discharged condition ofthe capacitor means to coincide with a zero-current state of the series circuit. There may be at least one additional sequence of opening and, following a delay period, closing the switching means prior to said re-opening of the switching means at a zero-current state of the series circuit, the various delay periods being such as to cause an at least partly discharged condition of the capacitor means to coincide with a zero-current state of the series circuit. In accordance with a third aspect of the invention, there is provided a method of controlling the switching means of a static var compensator, the compensator including capacitor means, inductive reactor means and switching means in a series resonant circuit connected across an AC supply system and having a resonant frequency higher than the AC system frequency, the method comprising the steps of: - opening the switching means at a zero-current or near-zero-current state of the series circuit, thereby leaving the capacitor means charged;

- closing the switching means after a delay period insufficient to allow the voltage across the switching means to rise to the sum of the voltage across the capacitor means and the peak voltage ofthe AC system, said closing ofthe switching means causing the flow of a composite current through the series circuit, the composite current comprising a transient resonant component and a steady fundamental component, the composite current having one or more zero-current transitions which coincide with values of the voltage across the capacitor means less than the peak value ofthe AC system voltage, and

- reopening the switching means at a said zero-current transition, the delay period being selected such that said zero-current transition coincides with a low value of the voltage across the capacitor means.

The said zero-current transition may be the second or later such transition after the closing of the switching means.

The said delay period may be less than a quarter-cycle at the AC system frequency. Brief Description of the Drawings An embodiment of a static var compensator in accordance with the invention will now be described, by way of example only, with reference to the accompanying drawings, of which: Figure 1 is a diagram ofthe basic elements of a series circuit comprising a capacitor

(bank) and a thyristor valve assembly for switching the capacitor in or out of circuit;

Figure 2 is a graph ofthe voltages and currents in the circuit of Figure 1 on blocking the thyristor valve from a steady state in a conventional manner;

Figure 3 is a similar graph of the effect of temporarily blocking the thyristor valve for a period of 4 ms;

Figure 4 is a graph of a blocking operation according to the invention using a preferred delay period of 4 ms;

Figures 5 and 6 are similar graphs showing the blocking operation with delay periods of 3 ms and 5 ms, respectively; Figures 7(a) and 7(b) are diagrams of delta and star arrangements of the series circuits of Figure 1;

Figures 8(a) and (c) are vector diagrams ofthe voltages arising when switching off the three phases in a star arrangement with floating star-point, and

Hgure 9 is a diagram of the two-valve star-connected TSC resulting from the analysis of Figures 8(a), (b) and (c).

Detailed Description of an Embodiment ofthe Invention Referring now to Figure 1, the series circuit shown, known as a thyristor switched capacitor (TSC) circuit, may be connected between one phase (V₀) of a three phase system and star-point/neutral (N), as shown, or may be one arm of a delta arrangement. The capacitor C and thyristor valve T are the basic components, the reactor L being provided to limit the current and also the rate of change of current in normal turn-on and under fault conditions.

The series circuit is resonant and the reactor L is chosen to give a self-resonant frequency in the range from about 150 to 250 Hz. The choice of a low self-resonant frequency requires a large reactance, which keeps the rate of change of current to a low value, but increases the cost of both capacitor and reactor. Figure 1 shows a switching means in the form of a simple thyristor valve T comprising a pair of thyristors back-to-back to provide conduction in both directions. When the switch is closed, a control means (not shown) provides gating pulses at 90° after the zero voltage crossings, so mamtaining the thyristor valve in an unblocked condition. In this condition, as current falls to zero in one of the back-to-back thyristors it is picked up smoothly in the other. The left hand parts of the graphs of Figure 2 show this situation. The valve voltage is zero up to time T„ while the voltage drop across the capacitor is in phase with, but exceeds the supply voltage (V₀) by between about 5 and 13% to counteract the antiphase voltage across the reactor L. At a suitable zero current transition, e.g. T,, the thyristor valve is blocked. At this point the capacitor is fully charged, the charge is trapped and the capacitor voltage persists at its peak value as shown in Figure 2 (negative upper electrode/positive lower). One half- cycle after the valve is blocked, the supply voltage reaches its positive peak value, the upper capacitor electrode is taken to the same voltage and the lower electrode is thereby driven excessively positive, to a value equal to the trapped capacitor voltage plus the supply voltage. This combined voltage on the lower electrode, amounting to more than twice the supply peak voltage, is applied across the thyristor valve which would, in the absence of any relieving facility, have to be rated accordingly. The resulting large excursions of the valve voltage are shown in Figure 2. The present application ofthe invention is directed to reducing this overvoltage and preventing the thyristor valve having to hold off excessive applied voltages in its blocked condition.

The invention exploits the fact that since the series circuit - the TSC circuit in the particular case - is a resonant circuit having a resonant frequency different from and higher than the system frequency, it is possible to activate the resonance by charging the capacitor (by normal operation), and 'unloading' the charged capacitor at a suitable instant so as to produce charging/discharging oscillations with current zeros at least one or more of which are at instants which do not coincide with maxima in the applied supply voltage. It thus becomes possible to obtain a current zero coincidentally with a zero value, or at least a low value, of capacitor voltage. Opening the switch, i.e. blocking the thyristor valve, at such an instant results in a subsequent valve voltage which may be no more than the applied, supply voltage.

Figure 3 shows an intermediate stage in achieving this result. The left-hand sides ofthe graphs show the steady condition with the capacitor in circuit. At time T„ as before, the switch is opened at a current zero, leaving the capacitor fully charged. The voltage across the valve now begins to rise as it did in Figure 2. However, if the switch is reclosed by deblocking the valve after a short delay period, in Figure 3 four milliseconds, the valve voltage drop will return to zero as shown. The charged capacitor can now discharge, the capacitor current, as shown in the lower graph, being a composite current comprising a transient component due to the resonant circuit and the steady state fundamental current. It can be seen that the resonant component produces zero current transitions at instants which do not correspond on a regular basis to maxima in the capacitor voltage graph. Thus the basic correspondence between zero-current transitions and capacitor-voltage maxima has been destroyed by the resonance. It will be clear that, while the phase of the fundamental current component is fixed in relation to the supply voltage, the phase of the resonant transient is determined by the instant T₂ at which the switch is re-closed. By controlling this instant T ₂ therefore, the current zeros, or rather, a selected one of them, can be shifted to coincide with a zero value ofthe capacitor voltage, or at least a very low value. Blocking of the valve at such a point, e.g. T₃, would then cause very little or no increase in the subsequent valve voltage over and above the supply voltage.

If the delay period T, - T₂ is allowed to extend for half of a system cycle, no advantage would be gained and the position would be the same as in Figure 2. The delay period during which the valve is temporarily blocked must therefore be less than half a system cycle. At delay period values between one half and one quarter the system cycle, an advantage is gained over the basic system but the blocked-valve voltage will still, initially, exceed the peak supply voltage. It is preferable therefore to use a delay period normally not exceeding a quarter-cycle.

In Figure 3 the system frequency is 50 Hz and the delay period is four milliseconds, i.e. one-fifth of the cycle period. Comparing the current and capacitor voltage graphs of Figure 3 it may be seen that the first current zero transition Z, coincides with a high value of capacitor voltage (which occurs shortly before the peak of the applied system voltage). The next current zero transition Z-, however, coincides with a zero value of the capacitor voltage as described above and would give an appropriate time to block the valve. The third current zero transition Z_j coincides with a moderately low value of capacitor voltage and could be acceptable in some circumstances.

Figure 4 illustrates a blocking operation derived from Figure 3 in which the delay period is four milliseconds and the resonant period extends to the second current zero transition Z-,. Two pulses of resonant current of alternating polarity are permitted to flow before the valve is again blocked. The subsequent peak voltage across the valve is almost exactly equal to the applied system voltage because the voltage trapped on the capacitor is almost zero.

The effect of shortening and lengthening the delay period in particular circumstances is illustrated in Figures 5 and 6. In Figure 5 the delay period is reduced to three milliseconds, which has the effect of advancing the cycle of resonant current oscillation and making the second current zero, previously Z_j, coincide with a significant value of capacitor voltage. The result is an increase of about 35% in the maximum voltage to which the valve is subjected, compared with the condition of Figure 4. In Figure 6 a delay period of 5 milliseconds is used, which delays the cycle of resonant current and allows the capacitor voltage to overshoot its zero value in the opposite direction before the current zero transition occurs; this produces an increase in the valve voltage of about 45% compared with the condition of Figure 4.

In both cases (Figure 5 and Figure 6), however, the valve voltage peak is significantly less than it is in the absence of the invention, i.e. in Figure 2, where the valve voltage peak exceeds the supply voltage peak by more than 100%.

It will be noted that the resonant frequency in Figures 2-6 is approximately 2.5 times the system frequency (i.e. 125 Hz instead of 50 Hz), this despite the fact that, as mentioned earlier, the reactor employed as component L in the TSC circuit (see Figure 1) is selected to give a resonant frequency of between three and five times the system frequency. The reason for this is that the inductance of the supply as a whole has to be taken into account. This takes the form of system reactances and coupling transformer reactances which appear in series with the ciirrent-limiting reactor L, increasing the effective value of L and lowering the resonant frequency.

For a given TSC circuit, there will be a range of firing instants, ending the delay period, which will result in an acceptably small residual charge on the capacitor. The instant of zero current will in practice be influenced by variations in the impedance of the supply circuit, as referred to above, and of other shunt circuits; it will also be influer^ed by externally imposed harmonic distortion and transient effects and, in a polyphase circuit, by imbalance and interactions between phases. While the invention can be exploited in a single phase system, as described above, a typical application is in a three phase system. Conventional TSC circuits are connected in delta, as shown in Figure 7(a), each series circuit arm comprising capacitor C, reactor L and valve T as before. The TSC circuit is connected to the high voltage transmission system by a star-delta transformer TF. Star connection of TSC circuits would normally only be considered if the transformer and TSC star points were solidly linked, as shown in Figure 7(b), in which case the thyristor valves could have fewer series 'levels' but would have to be rated for a higher current. The total valve rating of the star connected TSC of Figure 7(b) would be exactly the same as for the delta connected circuit If the line to line voltage of the transformer in Figure 7(a) is V_L and the line current is I_L then the total valve rating is:

whereas in Figure 7(b), where the phase voltage is V fS, the total valve rating is:

If the star point ofthe TSC were isolated, i.e. the star point link in Figure 7(b) were removed, the normal operating voltages would be as in Figure 8(a) and the basic switching- off sequence would be: 1. Current flow ceases in the first phase, e.g. phase a-n, to reach current zero, leaving a residual charge on the capacitor of slightly more than phase voltage; the voltage of the star point shifts to the mid-point of the line voltage between the other two. phases, increasing the effective phase voltage, Va-n, by 50% (Figure 8(b)).

2. The other two phase impedances are now effectively connected in series across the line to line voltage which lags the first phase by 90°. Current zero is 90° (i.e. one quarter-cycle) after the first current zero.

3. Only one switch is needed to interrupt this current (the other is superfluous since the two would be in series) but it needs to be rated for line-to-line voltage (Figure 8(c)). Thus, as shown in Figure 9, only two valves, each rated for line-to-line voltage and normal phase current, are needed for switching a three phase TSC with floating star-point. The total nominal kVA rating of these valves is 2 x V_L x I_L which is 115% of the rating of three delta-connected valves (3 x V_L x I,y3), but only 2/3 of the number of levels is needed for the star-connected arrangement. This may present a considerable advantage in those cases where the current rating of the thyristor valve is inherently equal to, or greater than, the phase current I_L and very much greater than the delta current

While the invention would normally be applied to delta connected TSC circuits as shown in Figure 7(a), or to star-connected circuits as in Figure 7(b) with solidly linked star points, it may also be applied to the two valve, three phase arrangement of Figure 9 if the star point is allowed to float.

Thus any static var compensator employing series circuits of electronic switching means, capacitor and damping reactor will benefit from application of the invention, irrespective of the overall configuration of the compensator.

It will be clear that, while thyristors are the commonly used switching element, any electronic switching means may be employed in a particular application, or indeed, in some cases, even a very fast acting mechanical switch. While the invention has been described mainly in terms of an embodiment in which the blocking operation comprises the steps of first opening the switching means, waiting for a period, closing the switching means then, at a suitable zero-current point, re-opening the switching means, it may also be advantageous to have an arrangement in which more than one closing operation and more than one delay occurs during the blocking operation. Also, although the reactor L in the series circuit has been described as being of such a value as will provide a resonant frequency of between about 150 and 250 Hz, in practice other values are possible also.

Claims

1. A static var compensator for connection to an AC supply, the compensator including at least one series circuit comprising capacitor means, inductive reactor means and switching means, the switching means being provided to switch the capacitor means and inductive reactor means into or out of circuit, the compensator including control means for performing a turn-off operation on said switching means, said control means being to this end arranged to perform a sequence of switching operations on said switching means thereby to cause an at least partly discharged condition of the capacitor means to coincide with a zero-current state of the series circuit.

2. A compensator as claimed in Claim 1 , in which the control means is arranged to open the switching means at or near to a zero-current state of the series circuit, close the switching means after a delay, and re-open the switching means at said coincidence condition.

3. A compensator as claimed in Claim 2, in which the control means is arranged to close the switching means after a delay of less than a half-cycle at the AC system frequency.

4. A compensator as claimed in Claim 2, in which the control means is arranged to close the switching means after a delay of less than a quarter-cycle at the AC system frequency.

5. A compensator as claimed in any one of Claims 2 to 4, in which, when the switching means is closed, current flow in the series circuit being subject to resonance of the series circuit components, the control means is arranged to permit one or more pulses of resonant current of alternating polarity to occur before the switching means is reopened.

6. A compensator as claimed in any one of Claims 2 to 5, in which the resonant frequency of the series circuit, taking into account inductive reactance associated with the AC system to which the compensator is connected, is higher than the AC system frequency, the delay period is approximately 0.2 times the period of the AC system frequency and the control means is arranged to permit two pulses of resonant current of alternating polarity to occur before the switching means is reopened.

7. A compensator as claimed in any one of the preceding claims. in which the switching means comprises thyristors.

8. A compensator as claimed in any one of the preceding claims, comprising a three-phase delta-connected arrangement of said series circuits.

9. A compensator as claimed in any one of Claims 1 to 7, comprising a three- phase star-connected arrangement of said series circuits having a star-point connected to the star-point of a three-phase supply system.

10. A compensator as claimed in any one of Claims 1 to 7, comprising a three- phase star-connected arrangement with an isolated star-point, in which two of the star- connected arms comprise said series circuits and the third arm comprises a said series circuit but without the electronic switching means.

11. A compensator as claimed in Claim 2, in which the control means is arranged to open and, following a delay period, close the switching means more than once prior to said re-opening of the switching means at said coincidence condition.

12. A method of controlling a static var compensator comprising at least one series circuit of capacitor means, inductive reactor means and switching means, the switching means being provided to switch the capacitor means and inductive reactor means into or out of circuit, in which method the capacitor means is switched out of circuit by opening the switching means at or near to a zero-current state of the series circuit, the switching means is closed after a delay period, and the switching means is reopened at or near to a zero-current state ofthe series circuit, the delay period being such as to cause an at least partly discharged condition of the capacitor means to coincide with a zero-current state of the series circuit.

13. A method of controlling the switching means of a static var compensator, the compensator including capacitor means, inductive reactor means and switching means in a series resonant circuit connected across an AC supply system and having a resonant frequency higher than the AC system frequency, the method comprising the steps of:

- opening the switching means at a zero-current or near-zero-current state of the series circuit, thereby leaving the capacitor means charged;

- closing the switching means after a delay period insufficient to allow the voltage across the switching means to rise to the sum of the voltage across the capacitor means and the peak voltage ofthe AC system, said closing of the switching means causing the flow of a composite current through the series circuit, the composite current comprising a transient resonant component and a steady fundamental component, the composite current having one or more zero-current transitions which coincide with values of the voltage across the capacitor means substantially below the peak value of the AC system voltage, and - reopening the switching means at a said zero-current transition, the delay period being selected such that said zero-current transition coincides with a low value of the voltage across the capacitor means.

14. A method as claimed in Claim 13, in which said zero-current transition is the second or later such transition after the closing of the switching means.

15. A method as claimed in any one of Claims 12 to 14, in which said delay period is less than a quarter-cycle at the AC system frequency.

16. A method as claimed in any one of Claims 12 to 15, in which said switching means comprises thyristors.

17. A method as claimed in Claim 12, including at least one additional sequence of opening and, following a delay period, closing the switching means prior to said re- opening ofthe switching means at a zero-current state ofthe series circuit, the various delay periods being such as to cause an at least partly discharged condition of the capacitor means to coincide with a zero-current state of the series circuit.

18. A static var compensator substantially as hereinbefore described with reference to Figures 1 to 6, or to Figures 1 to 6 as modified in accordance with Figures 7(a), 7(b) or 9 of the drawings.

19. A method of controlling a static var compensator, substantially as hereinbefore described with reference to Figures 1 to 6 of the drawings.