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WO1997006599B1 - Structure et procede de programmation efficace, incorporee au systeme et destinee a des circuits de logique programmable remanente - Google Patents

Structure et procede de programmation efficace, incorporee au systeme et destinee a des circuits de logique programmable remanente

Info

Publication number
WO1997006599B1
WO1997006599B1 PCT/US1996/013036 US9613036W WO9706599B1 WO 1997006599 B1 WO1997006599 B1 WO 1997006599B1 US 9613036 W US9613036 W US 9613036W WO 9706599 B1 WO9706599 B1 WO 9706599B1
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WO
WIPO (PCT)
Prior art keywords
data
register
isp
address
instruction
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1996/013036
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English (en)
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WO1997006599A1 (fr
Filing date
Publication date
Priority claimed from US08/512,796 external-priority patent/US5734868A/en
Application filed filed Critical
Priority to JP9508692A priority Critical patent/JPH11511307A/ja
Priority to EP96927385A priority patent/EP0843915A1/fr
Publication of WO1997006599A1 publication Critical patent/WO1997006599A1/fr
Publication of WO1997006599B1 publication Critical patent/WO1997006599B1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Abstract

Cette structure de programmation/effacement/vérification, incorporée au système et destinée à des circuits de logique programmable rémanente, comprend une broche (TDI) d'entrée de données, une broche de sortie de données, un registre (103A, 103B) d'instructions, une pluralité de registres (506A, 506B) de données, y compris un registre de programmation incorporé au système, le registre d'instructions et la pluralité de registres de données étant couplés en parallèle entre la broche d'entrée de données et celle de sortie de données, ainsi qu'un contrôleur synchronisation du registre d'instructions et de la pluralité de registres de données. Le registre de programmation incorporé au système comporte un champ d'adresses, un champ de données et un champ d'état. Il suffit d'entrer seulement une fois une instruction de programmation de base pour programmer/effacer le dispositif entier. Plus particulièrement, des paquets de données/adresses peuvent être glissés dos à dos dans le registre de programmation incorporé au système sans qu'il soit nécessaire d'insérer des instructions multiples entre chaque paquet au niveau de la broche d'entrée de données, ce processus diminuant ainsi de manière très importante le temps requis pour programmer/effacer le dispositif entier, par comparaison avec le temps requis pour les procédés connus de programmation incorporée au système. En outre, l'invention concerne un procédé efficace de fourniture de l'état (à savoir le résultat) des opérations de programmation incorporée au système, soit à l'intention de l'utilisateur terminal, soit pour le logiciel de soutien.
PCT/US1996/013036 1995-08-09 1996-08-09 Structure et procede de programmation efficace, incorporee au systeme et destinee a des circuits de logique programmable remanente Ceased WO1997006599A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP9508692A JPH11511307A (ja) 1995-08-09 1996-08-09 非揮発性プログラム可能論理装置用の効率的なインシステムプログラミング構成体及び方法
EP96927385A EP0843915A1 (fr) 1995-08-09 1996-08-09 Structure et procede de programmation efficace, incorporee au systeme et destinee a des circuits de logique programmable remanente

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/512,796 US5734868A (en) 1995-08-09 1995-08-09 Efficient in-system programming structure and method for non-volatile programmable logic devices
US08/512,796 1995-08-09

Publications (2)

Publication Number Publication Date
WO1997006599A1 WO1997006599A1 (fr) 1997-02-20
WO1997006599B1 true WO1997006599B1 (fr) 1997-03-20

Family

ID=24040601

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/013036 Ceased WO1997006599A1 (fr) 1995-08-09 1996-08-09 Structure et procede de programmation efficace, incorporee au systeme et destinee a des circuits de logique programmable remanente

Country Status (4)

Country Link
US (2) US5734868A (fr)
EP (1) EP0843915A1 (fr)
JP (1) JPH11511307A (fr)
WO (1) WO1997006599A1 (fr)

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US6738962B1 (en) * 2000-06-12 2004-05-18 Altera Corporation Configuration and/or reconfiguration of integrated circuit devices that include programmable logic and microprocessor circuitry
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EP1438662A2 (fr) * 2001-10-11 2004-07-21 Altera Corporation Detection d'erreur sur des ressources logiques programmables
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US7521960B2 (en) * 2003-07-31 2009-04-21 Actel Corporation Integrated circuit including programmable logic and external-device chip-enable override control
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US7138824B1 (en) 2004-05-10 2006-11-21 Actel Corporation Integrated multi-function analog circuit including voltage, current, and temperature monitor and gate-driver circuit blocks
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US7242218B2 (en) * 2004-12-02 2007-07-10 Altera Corporation Techniques for combining volatile and non-volatile programmable logic on an integrated circuit
US7116181B2 (en) * 2004-12-21 2006-10-03 Actel Corporation Voltage- and temperature-compensated RC oscillator circuit
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US7446378B2 (en) * 2004-12-29 2008-11-04 Actel Corporation ESD protection structure for I/O pad subject to both positive and negative voltages
US7919979B1 (en) * 2005-01-21 2011-04-05 Actel Corporation Field programmable gate array including a non-volatile user memory and method for programming
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US7602655B2 (en) * 2006-01-12 2009-10-13 Mediatek Inc. Embedded system
US7546498B1 (en) * 2006-06-02 2009-06-09 Lattice Semiconductor Corporation Programmable logic devices with custom identification systems and methods
US7778074B2 (en) * 2007-03-23 2010-08-17 Sigmatel, Inc. System and method to control one time programmable memory
US8060453B2 (en) 2008-12-31 2011-11-15 Pitney Bowes Inc. System and method for funds recovery from an integrated postal security device
US8055936B2 (en) 2008-12-31 2011-11-08 Pitney Bowes Inc. System and method for data recovery in a disabled integrated circuit
US8516176B1 (en) 2012-10-11 2013-08-20 Google Inc. Gang programming of devices
US10599853B2 (en) 2014-10-21 2020-03-24 Princeton University Trust architecture and related methods
US11314865B2 (en) 2017-08-01 2022-04-26 The Trustees Of Princeton University Pluggable trust architecture

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