WO1997006560A1

WO1997006560A1 - Low cost local interconnect process

Info

Publication number: WO1997006560A1
Application number: PCT/US1996/012695
Authority: WO
Inventors: H. Monte Manning
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 1995-08-03
Filing date: 1996-08-05
Publication date: 1997-02-20
Anticipated expiration: 1998-02-03
Also published as: AU6689296A

Abstract

A method is provided for fabrication of a local interconnect polycide layer for connection of active devices within a silicon substrate. A polysilicon layer (20) is deposited over the insulating layer (15) before contact openings (25) are etched. Metal silicide (40) such as tungsten silicide is then deposited over the insulating layer and into the contact opening, forming direct contact between the silicide layer and the active areas. The polysilicon layer acts merely as an adhesion layer while the silicide serves as an interconnect. Ohmic contact is achieved without the need to dope the polysilicon or the silicide.

Description

J-

LOW COST LOCAL INTERCONNECT PROCESS

This invention was made with Government support under Contract No. MDA 972-92-C-0054 awarded by Advanced Research Projects Agency (ARPA). The Government has certain rights in this invention.

Backorouπd of the Invention This invention relates to the fabrication of local interconnect layers for integrated circuits, and more particularly to the fabrication of silicide local interconnect for static random access memory devices.

In processing integrated circuits, electrical contact must be made among circuit nodes, such as isolated device active regions formed within a single-crystal silicon substrate. Traditionally, these active regions are connected by highly conductive paths or lines. These are fabricated above a dielectric or insulating layer which covers the substrate surface. For local interconnect of nearby circuit elements and interlayer connection, such extreme conductivity is not critical, though resistivity should not be excessively high. To provide electrical connection between the conductive path and active regions, windows or openings in the dielectric are etched to enable the conductive layer to contact the desired regions. Such openings are typically referred to as contact openings, or simply "contacts." Conductive lines and interconnects ideally have low overall resistance, which resistance depends upon both sheet resistivity and contact resistivity. While aluminum and other low-resistance metals (e.g., copper, gold) may have very low sheet resistance, integration of these metals as a local interconnect is difficult because of their high temperature instability and poor step coverage into contacts during deposition. The surface upon which the metal is to be deposited must be relatively smooth and therefore requires some type of planarization prior to metal deposition, which complicates the process. Additionally, many of the typical low-resistance metals also can contaminate the substrate in which the active devices are formed, causing parasitic leakage currents or device failure. For this reason, a diffusion barrier must also be formed to prevent diffusion of the metal ions to the silicon substrate. This also adds a level of complexity not required for alternative local interconnect materials.

It is also important for contemporary circuit fabrication that interconnect material form ohmic (low resistance) contact with doped silicon active areas. Polycrystalline silicon, or polysilicon for short, can be doped with n- or p-type dopants to provide such ohmic contact to doped active areas. Metal silicide also provides low contact resistance, while at the same time providing relatively low sheet resistance over short distances. Such materials are often employed in a local interconnect process as an intermediary layer between active areas and conductive metal lines. One common method of forming metal silicide is a self-aligned silicidation process, often referred to as

"salicidation." A thin layer of refractory metal, such as tungsten or titanium, is deposited over the dielectric layer and through the contact opening to contact the underlying silicon active area. The structure is generally heated in a first sinter step at high temperature in a nitrogen environment to form titanium silicide (predominantly TiSi₂), for example. During the sinter, titanium reacts with the exposed silicon (at the contact) to form TiSi₂. The titanium which overlies the dielectric reacts with ambient nitrogen to form titanium nitride (TiN). After the first sinter, the TiN and unreacted titanium maγ be removed in a wet etch and a final sinter is performed to Iower the suicide's sheet resistance to acceptable levels. The final sinter converts the titanium from the C49 phase to the lower resistance C54 phase.

Salicidation, however, is accompanied by numerous difficulties. During the sinter process, both silicon and dopant from shallow junctions diffuse into the forming siiicide. Dopant depletion from shallow junctions causes junction leakage and/or high contact resistance. At the same time interstitials or spikes are injected into the substrate, increasing diffusion of the dopants into the silicide and exacerbating the leakage problem. Often, high anneal temperatures are required later in the integration process to activate dopants. This may cause agglomeration and therefore high resistance within the silicide line. Additionally, salicidation (used to clad polysilicon gates and MOS source/drains with silicide) is prone to causing shorts across oxide spacers, reducing yield. When salicide is used in a local interconnect process, the unreacted metal and byproducts must be patterned after the first sinter step. Instead of completely removing all Ti metal and TiN, this patterning step allows selected TiN/Ti regions to remain, providing interconnect between salicided regions. This patterning step requires that TiN be etched selectively against TiSi in order to retain the advantages of the siiicide and to prevent the etch from reaching the underlying active area. As yet, no anisotropic dry etch process has been developed to provide good selectivity between these layers, where "good selectivity" is defined as greater than 10:1 etching of TiN over TiSi₂. Selective wet etch is possible, but since wet etches are isotropic, unwanted lateral etching cannot be controlled. Wet etch cannot provide the narrow and close line/space pairs often required by high density integrated circuits.

Alternatively, polycide (a combination of polysilicon and silicide layers) may serve as the local interconnect layer. Prior art polycide interconnect has been formed by depositing both polysilicon and silicide after the contacts have been opened in the insulating layer. Before the polysilicon can be deposited, native oxide, which grows on the exposed silicon substrate in oxygen environments, should be cleaned with an HF solution in deionized water. Polysilicon is then deposited through the openings to contact the active areas and silicide is deposited over the polysilicon. The active areas, polysilicon, and silicide, respectively, are thus in series contact with one another to form a low-resistance line. The polysilicon acts both as a low-resistance contact material and as an adhesion layer interposed between the oxide and the silicide.

Unfortunately, polysilicon can form rectifying contacts with the active areas in these prior art interconnects. The polysilicon layer must therefore be doped to match the dopant type of the contacted active region, in order to ensure ohmic contact. This doping step requires an additional mask. In the fabrication of CMOS circuits, which utilize complementary n- and p-channel devices, interconnects require two masks for doping the different regions of interconnect which contact the p+ drain and the n+ drain. Each of these masks is expensive both to create for different chip designs and to use in production. it is therefore an object of the present invention to avoid the problems introduced in integrated circuit fabrication by salicidation of interconnect layers. It is a further object of the present invention to reduce the number of masks required by silicide deposition techniques known to the art. Summary of the Invention

Disclosed is a method for forming a local interconnect layer wherein an insulating layer and a polysilicon layer are first formed over the circuit elements to be connected. Contact openings exposing a plurality of circuit nodes, such as active areas within a silicon substrate, are etched through both the insulating layer and the polysilicon layer. A metal or silicide is then deposited over the polysilicon layer and into the contact openings to provide direct electrical contact between the exposed circuit nodes and the silicide.

Brief Description of the Drawings Figure 1 is a partial schematic section of an integrated circuit following deposition of an insulating layer and a polysilicon layer in accordance with an embodiment of the present invention.

Figure 2 is a partial schematic section of the integrated circuit of Figure 1 following an etch step. Figure 3 is a partial schematic section of the integrated circuit of Figure 2 following deposition of a metal or silicide.

Detailed Description of the Preferred Embodiments As described in the Background section above, prior art polycide interconnect layers (composite polysilicon and silicide) are generally deposited over integrated circuits after contact openings are etched into the insulating layer. The polysilicon layer, however, must be masked and doped to avoid rectifying contacts with the doped silicon active areas. In the case of CMOS devices, for example, two masks are required to dope different areas of the polysilicon both n+ and p-i- to match the differently doped active areas. The present invention advantageously eliminates the need for these masks.

Figure 1 is a sectional view of a CMOS device 10 following deposition or growth of an insulating layer 15 and a polysilicon layer 20 in accordance with the present invention. The insulating layer 15 in the preferred embodiment comprises an oxide, but other dielectric materials such as nitride or oxide-nitride-oxide composite (ONO) may also serve as the insulating layer. Oxides are commonly used in tetraethyl orthosilicate (TEOS) or boron phosphosilicate glass (BPSG) forms. The deposition of oxide is well known in the art and need not be explained here in any detail. The oxide layer 15 should be thick enough to provide electrical isolation of the underlying circuit elements, preferably between 500 A and 3000 A.

Some metals and metal suicides, such as tungsten and tungsten silicide (WSi₂), do not adhere well when deposited directly over insulating materials such as oxide or nitride, resulting in poor reliability and lower yield. Therefore, the present invention provides the polysilicon layer 20 as an adhesion layer for the silicide which is to be deposited. Since adhesion is the polysilicon's primary function, the thickness of the polysilicon layer 20 is not critical. Preferably, however, the polysilicon layer 20 should be on the order of about 100 A to 1000 A, and most preferably about 500 A.

As with oxide deposition, polysilicon may be deposited by any of a number of known means, particularly because polysilicon step coverage into contact openings is not a concern with the present invention. Thus sputtering, chemical vapor deposition (CVD), or any other method may be acceptable. The next step in this preferred embodiment is to perform a contact etch to open a plurality of contact openings 25 (Figure 2) to a plurality of active areas 30 and 31 through both the oxide 15 and the polysilicon 20.

Contact may also be made to an other circuit node 35 from which conductive interconnection is desired, as illustrated in Figure 2. At least one mask, similar to masks provided in prior art etch steps, is required to define the contact openings 25 in accordance with the preferred embodiment.

It will be understood by one of skill in the art that the contact openings 25 may penetrate through other layers as well, depending on the process with which the local interconnect is associated. The etch may be accomplished by a number of known means but should select against the area to be contacted. Thus, in the preferred embodiment, the polysilicon 20 and oxide 15 should be selectively etched while an n+ active area 30, a p+ active area 31, and an interconnect node 35 should stop the etch.

One possible process to provide this etch employs a magnetically enhanced reactive ion etch (MERIE) reactor, flowing equal amounts of CF< and CHF₃. The chamber pressure should be maintained at about 200 mTorr, the applied magnetic field at about 50 Gauss, and the applied RF energy at about 600W. The wafer should be etched under these conditions for enough time to clear the oxide 15 through the mask down to the substrate. In fact, an overetch (about 25%) should be performed to ensure that the substrate is cleaned of all oxide 15 at the window 25.

Following the etch step, a conductive layer 40 (Figure 3), comprising a metal or a silicide, is then formed over the polysilicon layer 20 and into the etched contact openings 25. Refractory metal suicides are preferred for this layer 40, due to their low sheet resistance as well as low contact resistance with silicon or metal. In the preferred embodiment, tungsten silicide (predominantly WSi₂) forms the silicide layer 40. Other suicides, such as TiSi₂, CoSi₂, PtSi, or NiSi may also be employed. Alternatively, a metal deposition, such as elemental tungsten (W) may be deposited over the polysilicon 20 and into the contact openings 25.

The silicide 40 of the preferred embodiment may be deposited by any known means, including co- evaporation, co-sputtering and chemical vapor deposition (CVD) techniques. Low pressure chemical vapor deposition (LPCVD) methods are particularly efficient for conformal deposition of silicide into high aspect contact openings. In the case of TiSi₂, low pressure CVD methods are disclosed in U.S. Patents No. 5,240,739, No. 5,278,100, No. 5,376,405, all issued to Doan et al., and U.S. Patent No. 4,233,791, issued to Sandhu et al. All of the above references are assigned to the assignee of the present invention and disclose improvements to CVD deposition of suicides like TiSi₂. These disclosures are hereby incorporated by reference into the present disclosure. Alternatively, plasm enhanced CVD (LPCVD) allows low temperature CVD for metal suicides. U.S. Patent No. 5,344,792, issued to Sandhu et al., discloses such a LPCVD and is hereby incorporated by reference.

CVD deposition of refractory metal suicides involves gas phase mixture of a volatile refractory complex, such as a refractory halide, and a silicon source, such as silane (SiH₄). For the preferred embodiment, WSi₂ is deposited through a reaction among tungsten fluoride (WF₆) flowing at a rate of 3 seem; SiH₄ at 300 se m; and argon (Ar) at 500 seem. The reaction preferably takes place at about 400°C under about 500 mTorr of pressure. The ratio of W:Si in the reaction results in a silicon-rich mixture. After deposition of the silicide 40, a rapid thermal anneal step (RTA) may be performed to Iower the resistivity of the layer 40. Because this anneal takes place over a very short time (between about 5 and 30 seconds), pre-existing circuit structures are not damaged by the RTA. At the same time, the RTA may aid reaction of the silicide 40 with the underlying polysilicon 20, strengthening the adhesion between the layers. After the anneal, excess unreacted metal may be selectively washed with a chlorine or fluorine based etch, for TiSi₂ or CoSi₂, for example. Because the polysilicon 20 then adheres well to both the underlying oxide 15 and the overlying silicide 40, the polysilicon layer 20 is referred to as an adhesion layer.

This adhesion is not required at the contact openings 25 between the silicide 40 and the active areas 30 and 31. Rather, the deposited siiicide 40 of the present invention directly contacts the active areas 30 exposed by the etch step. The same is true of any other contact nodes 35 exposed by the etch step described above. Since the poly layer 20 acts only as an adhesion layer and plays no role in conduction between each active area 30 and the silicide 40, no doping of the polysilicon 20 is required. The silicide 40 itself forms ohmic contact with both p + active areas 30 and n+ active areas 31, so that the silicide 40 need not be doped either.

Thus, the masks and doping steps which would otherwise be needed for doping the polysilicon have been eliminated by the present invention, reducing the costs of integrated circuit formation. The invention has particular utility in conjunction with local interconnect for CMOS circuits, as illustrated in Figure 3. Due to the silicide 40 having direct contact with both the n+ and p+ active areas, 30 and 31, two separate mask steps are avoided: one for π-doping regions of the polycide overlying the n+ active areas 30, and one for p-doping regions of the polycide overlying the p+ active areas 31. Direct contact between the silicide 40 and the active areas, 30 and 31, entails an additional benefit: any native oxide formed over the active area after the etch step is broken up by the silicide deposition. Thus, expensive precautions against the formation of interlayer oxide and pre-cleaning steps may be avoided.

It will be understood by those skilled in the art that the method of interconnection disclosed herein may equally be applied to the formation of buried contacts, though the forgoing description has focused on local interconnect. For example, a gate conductor may require electrical contact to both p-doped and n-doped active areas. The present invention allows formation of such contact without doping the contact material (silicide). It will be understood that the present invention is applicable wherever polycide may provide electrical contact between or among circuit elements.

Although the foregoing invention has been described in terms of a preferred embodiment, other embodiments will become apparent to those of ordinary skill in the art, in view of the disclosure herein. Accordingly, the present invention is not intended to be limited by the recitation of preferred embodiments, but is instead intended to be defined solely by reference to the appended claims.

Claims

WHAT IS CLAIMED:

I. A method of fabricating a local interconnect layer for an integrated circuit, the method comprising the steps of: forming an insulating layer over a plurality of circuit elements; depositing a polysilicon layer over the insulating layer; selectively etching a plurality of contact openings through both the insulating layer and the polysilicon layer to expose a plurality of pre-selected circuit nodes associated with the circuit elements; and depositing a conductive layer over the polysilicon layer and into the contact openings, forming direct electrical contact between the exposed circuit nodes and the conductive layer. 2. The method of Claim 1, wherein the circuit comprises a static random access memory cell.

3. The method of Claim 1, wherein the integrated circuit comprises a CMOS device and the exposed circuit nodes comprise at least two active areas having doping types opposite to one another.

4. The method of Claim 1, wherein the conductive layer comprises a metal silicide layer.

5. The method of Claim 4, wherein the metal silicide layer comprises a tungsten silicide layer. 6. The method of Claim 5, wherein the insulating layer comprises an oxide.

7. The method of Claim 6, wherein the oxide layer comprises a tetraethyl orthosilicate.

8. The method of Claim 7, wherein the polysilicon layer has a thickness of between about 100 A and 1000 A.

9. The method of Claim 8, wherein the polysilicon layer thickness is about 500 A. 10. The method of Claim 9, wherein the etch step comprises a magnetically enhanced reactive ion etch.

II. The method of Claim 10, wherein the etch step comprises the steps of: flowing an amount of CF₄ and an equal amount of CHF₃; setting a chamber pressure at about 200 mTorr; setting an applied magnetic field at about 50 Gauss; and setting an applied RF power at about 600 Watts.

12. The method of Claim 4, further comprising an anneal step after the silicide deposition step.

13. The method of Claim 12, wherein the anneal step is performed at between 600°C and 900°C.

14. The method of Claim 4, further comprising an excess metal clean step after the silicide deposition step.

15. The method of Claim 4, wherein the silicide deposition step comprises a chemical vapor deposition process within a CVD reactor.

16. The method of Claim 15, wherein the siiicide deposition step comprises a low pressure process.

17. The method of Claim 16, wherein the low pressure chemical vapor deposition comprises the steps of: fiowiπg an amount of WF₆ at 3 seem; flowing an amount of SiH₄ at 300 seem; flowing an amount of Ar at 500 seem; setting a reactor temperature at about 400°C; and setting a reactor pressure at about 500mTorr.

18. An integrated circuit comprising a silicon substrate having at least one doped active area, an insulating layer covering the substrate and having at least one contact opening therethrough to the active area, a polysilicon adhesion layer covering the insulating layer except over the contact opening, and a conductive local interconnect layer over the adhesion layer and through the contact opening, the local interconnect layer directly contacting the active area, and the adhesion layer interposed between the local interconnect layer and the insulating layer except in the contact opening.

19. The integrated circuit of Claim 18, comprising a CMOS device, wherein the local interconnect layer directly contacts at least one n-doped active area and at least one p-doped active area.

20. The integrated circuit of Claim 18, wherein the local interconnect comprises a metal silicide. 21. The integrated circuit of Claim 20, wherein the local interconnect layer comprises a tungsten silicide, and the insulating layer comprises an oxide.

22. A method of fabricating a local interconnect layer for an integrated circuit, the method comprising the steps of: forming a polysilicon layer over an insulating layer, the insulating layer covering a plurality of circuit nodes, both the polysilicon and insulating layers having a plurality of aligned contact holes over the circuit nodes; and depositing a metal silicide layer over the polysilicon layer and into the contact holes, forming direct electrical contact between the circuit nodes and the silicide.