[go: up one dir, main page]

WO1997004560A1 - Mise en correspondance d'une cellule de donnees dans un reseau de communications - Google Patents

Mise en correspondance d'une cellule de donnees dans un reseau de communications Download PDF

Info

Publication number
WO1997004560A1
WO1997004560A1 PCT/US1996/011917 US9611917W WO9704560A1 WO 1997004560 A1 WO1997004560 A1 WO 1997004560A1 US 9611917 W US9611917 W US 9611917W WO 9704560 A1 WO9704560 A1 WO 9704560A1
Authority
WO
WIPO (PCT)
Prior art keywords
queue
link
entry
virtual
translation table
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1996/011917
Other languages
English (en)
Inventor
Michael E. Gaddis
Richard G. Bubenik
Stephen A. Caldara
Stephen A. Hauser
Thomas A. Manning
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Network Communications Inc
Ascom Nexion Inc
Original Assignee
Fujitsu Ltd
Fujitsu Network Communications Inc
Ascom Nexion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Network Communications Inc, Ascom Nexion Inc filed Critical Fujitsu Ltd
Priority to JP9506863A priority Critical patent/JP2000501901A/ja
Priority to AU65007/96A priority patent/AU6500796A/en
Priority to PCT/US1996/011917 priority patent/WO1997004560A1/fr
Publication of WO1997004560A1 publication Critical patent/WO1997004560A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17375—One dimensional, e.g. linear array, ring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4604—LAN interconnection over a backbone network, e.g. Internet, Frame Relay
    • H04L12/4608—LAN interconnection over ATM networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/11—Identifying congestion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/18—End to end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/26—Flow control; Congestion control using explicit feedback to the source, e.g. choke packets
    • H04L47/266—Stopping or restarting the source, e.g. X-on or X-off
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/29—Flow control; Congestion control using a combination of thresholds
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/30—Flow control; Congestion control in combination with information about buffer occupancy at either end or at transit nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/62—Queue scheduling characterised by scheduling criteria
    • H04L47/621—Individual queue per connection or flow, e.g. per VC
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
    • H04L49/105—ATM switching elements
    • H04L49/106—ATM switching elements using space switching, e.g. crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
    • H04L49/105—ATM switching elements
    • H04L49/107—ATM switching elements using shared medium
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1515—Non-blocking multistage, e.g. Clos
    • H04L49/153—ATM switching fabrics having parallel switch planes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1553—Interconnection of ATM switching modules, e.g. ATM switching fabrics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1553—Interconnection of ATM switching modules, e.g. ATM switching fabrics
    • H04L49/1576—Crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H04L49/201—Multicast operation; Broadcast operation
    • H04L49/203—ATM switching fabrics with multicast or broadcast capabilities
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/255—Control mechanisms for ATM switching fabrics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/256—Routing or path finding in ATM switching fabrics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H04L49/309—Header conversion, routing tables or routing tags
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/45—Arrangements for providing or supporting expansion
    • H04L49/455—Provisions for supporting expansion in ATM switches
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/55—Prevention, detection or correction of errors
    • H04L49/552—Prevention, detection or correction of errors by ensuring the integrity of packets received through redundant connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/55—Prevention, detection or correction of errors
    • H04L49/555—Error detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5614—User Network Interface
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5614—User Network Interface
    • H04L2012/5616—Terminal equipment, e.g. codecs, synch.
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5625—Operations, administration and maintenance [OAM]
    • H04L2012/5627—Fault tolerance and recovery
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5628—Testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H04L2012/5631—Resource management and allocation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H04L2012/5631—Resource management and allocation
    • H04L2012/5632—Bandwidth allocation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H04L2012/5631—Resource management and allocation
    • H04L2012/5632—Bandwidth allocation
    • H04L2012/5634—In-call negotiation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H04L2012/5631—Resource management and allocation
    • H04L2012/5632—Bandwidth allocation
    • H04L2012/5635—Backpressure, e.g. for ABR
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/564—Connection-oriented
    • H04L2012/5642—Multicast/broadcast/point-multipoint, e.g. VOD
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/564—Connection-oriented
    • H04L2012/5643—Concast/multipoint-to-point
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5647—Cell loss
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5647—Cell loss
    • H04L2012/5648—Packet discarding, e.g. EPD, PTD
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5649—Cell delay or jitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5651—Priority, marking, classes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H04L2012/5682—Threshold; Watermark
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H04L2012/5683—Buffer or queue management for avoiding head of line blocking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5685—Addressing issues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Definitions

  • This invention relates generally to the field of communication systems, and more particularly to mapping a data cell in a communication switch.
  • a communication system includes a collection of components that communicate, manipulate, and process information in a variety of ways.
  • This system may support different access technologies, such as frame relay, circuit services, and new and evolving connection-based or connectionless services, that communicate information, such as data, voice, and video.
  • Switches in the communication systems employ hardware and software to route information generated by access technologies to an intended destination.
  • a to-switch port processor may receive various data cells over multiple connections or links.
  • Each data cell may have a header which contains multiple bits of information used in processing the data cell.
  • the header may comprise a 12-bit virtual path identification (VPI) field and a 16-bit virtual channel identification (VCI) field.
  • VPI field and VCI field form a 28-bit identifier for the data cell.
  • a data cell is processed according to a queue descriptor associated with its VPI/VCI identifier. It is extremely expensive, however, to map all of the combinations for the VPI/VCI identifier in a look-up table which includes a separate queue descriptor for each combination.
  • a system for mapping a data cell in a communication switch.
  • the system includes a virtual translation table having at least one virtual path translation table queue entry and at least one virtual channel translation table queue entry.
  • a to-switch port processor which can access the virtual translation table, has at least one link which receives a data cell.
  • the to-switch port processor maps the received data cell to a queue number using the virtual translation table. Queue number is used to identify an associated queue descriptor to access state information used to manage the connection.
  • a method for mapping multiple data cells to a single queue descriptor in a communication switch.
  • the method includes receiving a first and a second data cell.
  • Each of the first and second data cells has an associated identifier.
  • the identifier of the first data cell is different from the identifier of the second data cell.
  • a virtual translation table comprising a plurality of queue entries is referenced. Each queue entry specifies the same queue descriptor.
  • the first and second data cells are mapped to the queue descriptor using different queue entries from the virtual translation table.
  • An important technical advantage of the present invention includes providing a virtual translation table for mapping data cells.
  • the virtual translation table includes a plurality of data entries, which are referenced according to ranges of VCI fields and VPI fields.
  • Each data entry in the virtual translation table specifies a queue number. Multiple data entries may specify the same queue number. Each queue number can be used to reference a specific queue descriptor which dictates how a data cell should be processed. Because multiple VPI/VCI identifiers can be mapped to the same queue descriptor via the virtual translation table, a separate queue descriptor is not required for each combination of the VPI/VCI identifier. Thus, the amount of memory required to support data cells in a communication switch is substantially minimized or reduced. Other important technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.
  • FIGURE 1 illustrates a system for mapping a data cell in a communication switch
  • FIGURE 2 illustrates a number of data structures contained within the to-switch port processor shown in FIGURE 1;
  • FIGURE 3 illustrates details for the virtual translation table shown in FIGURE 1 and an exemplary link boundary entry shown in FIGURE 2;
  • FIGURE 4 illustrates exemplary formats of various data entries shown in FIGURE 3.
  • FIGURE 5 is a flow chart of a method for mapping a data cell in a communication switch.
  • FIGURES 1-5 of the drawings like numerals being used for like and corresponding parts of the various drawings.
  • FIGURE 1 illustrates a system 10 for mapping data cells in a communication switch, such as an asynchronous transfer mode (ATM) switch.
  • System 10 includes a to-switch port processor (TSPP) and a memory 14.
  • TSPP 12 may be implemented as an application-specific integrated circuit (ASIC) .
  • ASIC application-specific integrated circuit
  • TSPP 12 includes a plurality of links 16-30 (labeled as LINK0-LINK7 in FIGURE 1) . Although TSPP 12 generally supports eight such links, it must be understood that in other embodiments, TSPP 12 may include either more or less links.
  • Links 16-30 may support asynchronous transfer mode (ATM) cell relay (OC-12, OC-3c, 155 Mbps UTP), frame relay (Tl, El, T3, E3, V.35), circuit emulation (Tl, El, T3, E3) , internetworking using Ethernet, Fast Ethernet, Internet Protocol (IP), or IP over ATM, or any other communications protocol or access technology.
  • ATM synchronous transfer mode
  • TSPP 12 converts the incoming ATM cell 31 into an internal cell 32 for transfer within system 10.
  • Internal cell 32 constitutes a "packet" of information which may include a virtual path identification (VPI) field 34 and a virtual channel identification (VCI) field 36 that is taken from incoming ATM cell 31.
  • VPN virtual path identification
  • VCI virtual channel identification
  • TSPP 12 inserts a link field 38 into internal cell 32 that identifies the link that the incoming ATM cell arrived on.
  • VPI field 34 and VCI field 36 may be part of a header for internal cells 32.
  • TSPP 12 includes a plurality of data structures which can be used in processing internal cells 32. These data structures are illustrated and described below in more detail with reference to FIGURE 2.
  • Memory 14 may be coupled to TSPP 12. Memory 14 can be implemented in memory internal or external to TSPP 12. In one embodiment, memory 14 may be implemented in an external random access memory (RAM) .
  • Memory 14 includes a plurality of data tables including virtual translation table (VXT) 40 and a queue descriptor table 44.
  • VXT 40 is illustrated and described below in more detail with reference to FIGURE 3.
  • Queue descriptor table 44 comprises a plurality of queue descriptors which can be used to direct the operation of queues for processing of data cells. Each individual queue can be set to process either data cells or special cells. The same queue descriptor can be used to process cells having different VPI/VCI identifiers.
  • the information in VXT 40 and queue descriptor table 44 may be configured or initialized by software.
  • FIGURE 2 illustrates various data structures that may be contained within TSPP 12 shown in FIGURE 1.
  • These data structures include a link boundary look-up table 46, a range (R) bit 48, a range queue number 50, an exception (X) bit 52, an exception queue number 54, a Payload Type (PT) action table 56 having an S bit 56a and an A bit 56b, a PT queue number 58, a special action table 60 having an M bit 60a and an A bit 60b, and a special action queue number 62.
  • R range
  • X exception
  • PT Payload Type
  • PT Payload Type
  • special action table 60 having an M bit 60a and an A bit 60b
  • special action queue number 62 a special action queue number 62.
  • These data structures can be implemented as registers and may be configured or initialized by software.
  • Link boundary look-up table 46 comprises a number of link boundary entries 64-78, which correspond to links 16-30, respectively, of TSPP 12. Each link boundary entry 64-78 can be used to associate a data cell received at the corresponding link 16-30 with a related data entry in VXT 40, as described below in more detail.
  • Range bit 48 is used to determine whether a data cell should be discarded if the VPI field of the cell is not within an appropriate range.
  • Range queue number 50 comprises a queue number that is used for further processing of a data cell with an out of range VPI whenever range bit 48 is set to "1.”
  • Range queue number 50 is associated with a queue descriptor that will redirect internal cell 32 for special processing.
  • Exception bit 52 is used to determine whether a data cell should be discarded because it is an exception.
  • Exception queue number 54 comprises a queue number which may be used when exception bit 52 is set to "1.” Like range queue number 50, exception queue number 54 also references a queue descriptor that will redirect the cell for special processing.
  • PT action table 56 comprises a number of entries which can be used to direct the processing of a data cell under certain conditions, as described below.
  • the entries in PT action table 52 are indexed by the PT field in the cell header.
  • PT action table 52 comprises eight entries, each entry corresponding to the eight possible payload types in an incoming ATM cell 31.
  • PT queue number 58 specifies a PT queue number which can be used to reference a queue descriptor contained in queue descriptor table 44.
  • Special action table 60 also includes a number of entries which can be used to direct the processing of a data cell under certain conditions.
  • the entries in special action table 60 are indexed by the VCI field 36 of internal cell 32.
  • special action table 60 comprises thirty-two entries, each entry corresponding to a particular special action in the communication switch.
  • Special action queue number 62 identifies a special action queue number which can be used to reference a queue descriptor in queue descriptor table 44.
  • FIGURE 3 illustrates details for VXT 40 shown FIGURE 1 and exemplary link boundary entry 68 shown in FIGURE 2.
  • FIGURE 3 illustrates how link boundary entry 68 can be used to reference a particular data entry within VXT 40.
  • VXT 40 comprises a connection VXT 80 and a flow control VXT 82, which are stored in memory 14 at an offset defined by the same address.
  • Connection VXT 80 is used to map the header of internal cell 32 to a specific queue number which can then be used to reference a queue descriptor in queue descriptor table 44.
  • Flow control VXT 82 is referenced when a cell received at TSPP 12 is a credit update cell.
  • flow control VXT 82 is used to map the credit VPI/VCI contained in the payload of a credit update cell to a from-switch port processor (FSPP) queue number associated with a particular FSPP 13.
  • FSPP from-switch port processor
  • VXT 40 generally applies to both connection VXT 80 and flow control VXT 82.
  • VXT 40 may include a plurality of data entries (described below) used in mapping a data cell to a descriptor. The number of data entries may be equal to the number of queues supported for a particular port processor configuration.
  • VXT 40 can be divided into a number of link tables, each corresponding to a link 16-30 of TSPP 12. For example, link "2" table 84 corresponds to link 20 (labeled as "LINK2”) of TSPP 12. It should be understood that in an embodiment in which multiple T ⁇ PPs 12 are present, a separate link table is maintained for each link of each TSPP 12.
  • Exemplary link "2" table 84 in VXT 40 comprises a virtual channel translation table (VCXT) section 86 and a virtual path translation table (VPXT) section 88.
  • VCXT section 86 may include one or more VCXT queue entries, such as exemplary VCXT queue entry 90.
  • VPXT section 88 may include one or more VPXT queue entries, such as exemplary VPXT queue entry 92, and one or more VCXT range entries, such as exemplary VCXT range entry 94.
  • the VCXT queue entries and VPXT queue entries comprise queue numbers for referencing queue descriptors contained in queue descriptor table 44 of memory 14 shown in FIGURE 1.
  • VCXT range entries define a particular range within VCXT section 86 within which the VCI in a particular internal cell 32 should fall.
  • Exemplary VCXT queue entry 90, VPXT queue entry 92, and VCXT range entry 94 are illustrated and described below in more detail with reference to FIGURE 4.
  • VXT 40 can be referenced and defined by the link boundary entries 64-78 in link boundary look-up table 46 of TSPP 12 shown in FIGURE 2.
  • Link boundary entry 68 is shown for purposes of illustration.
  • Link boundary entry 68 comprises an enable (E) bit 80, a GFC (G) bit 82, a start 84, and a VP limit 86.
  • Enable bit 80 is used to selectively enable or disable processing for the link corresponding to the link boundary entry. When enable bit 80 is set to "0,” all data cells entering TSPP 14 from that link are discarded.
  • GFC bit 82 dictates whether the GFC field of the incoming ATM cell 31 should be set to "0000.”
  • Start 84 and VP limit 86 define physical boundaries in VXT 40.
  • a "start” specifies an offset from the base of VXT 40 to the link table for the link corresponding to the link boundary entry.
  • start 84 specifies the offset for link "2" table 84.
  • VPI limit 86 specifies the boundary which separates VCXT section 86 from VPXT section 88 in link table 84.
  • FIGURE 4 illustrates details for exemplary data entries 90-94 shown in FIGURE 3.
  • VCXT range entry 94 comprises a VCXT offset 104, a virtual channel (VC) limit 106, a terminated virtual path (T) bit 108, and a valid (V) bit 110.
  • VCXT offset 104 and VC limit 106 define a VCI range within VCXT section 86.
  • VCXT offset 104 defines an offset from the base of link table 84 to the beginning of the VCI range.
  • VC limit 86 defines the end of the VCI range. Terminated virtual path bit 108 can be used to distinguish between the various data entries in VPXT section 88.
  • terminated virtual path bit 108 is set to "0," the entry will be a VCXT range entry. If the terminated virtual path bit 108 is set to "1,” then the entry is a VPXT queue entry.
  • Valid bit 110 is used to specify whether VCXT range entry 94 is valid or not. If valid bit 110 is set to "1,” then the VCXT range entry is valid. Otherwise, if valid bit 110 is set to "0,” VCXT range entry 94 is invalid.
  • VPXT queue entry 92 comprises a TSPP virtual path selection (VPS) queue number 112, a special action (S) bit 114, an RCC bypass (RB) bit 116, an FSPP flow control queue number 118, a terminated virtual path (T) bit 120, and a valid (V) bit 122.
  • TSPP VPS queue number 112 can be used to reference a queue descriptor for the virtual path (VP) connection of a data cell, such queue descriptor being contained in queue descriptor table 44.
  • Different VPXT queue entries may contain the same TSPP VPS queue number, thereby referencing the same queue descriptor.
  • Special action bit 114 can be used to specify whether special processing, as defined by special action table 60 in TSPP 12, should be performed on a data cell. If special action bit 114 is set to "1," special processing should be performed.
  • RCC bypass bit 116 can be used to specify whether the decoding of QFC protocol message cells on the VP connection should be bypassed. If RCC bypass bit 116 is set to "1," normal decoding of cell headers is used to determine if the data cell is a QFC protocol message cell. If the data cell received at TSPP 12 is a credit update cell, then FSPP flow control queue number 118 is transmitted along with credit information to an appropriate FSPP over a suitable interface, such as a T2F interface.
  • terminated virtual path bit 120 is used to distinguish between a VCXT range entry and a VPXT queue entry. If terminated virtual path bit 120 is set to "1," then the entry is a VPXT queue entry.
  • Valid bit 122 can be used to specify whether VPXT queue entry 92 is valid or invalid.
  • VCXT queue entry 90 comprises a TSPP virtual channel service (VCS) queue number 124, a special action (S) bit 126, an operation and maintenance (OAM)/(M) bit 128, an FSPP flow control queue number 130, a terminated virtual path (T) bit 132, and a valid (V) bit 134.
  • TSPP VCS queue number 124 can be used to reference a particular queue descriptor contained in queue descriptor table 44 of memory 14. Different VCXT queue entries may contain the same TSPP VCS queue number, thereby referencing the same queue descriptor.
  • Special action bit 126 can be used to specify whether special processing, as defined by special action table 60 in TSPP 12, should be performed.
  • OAM bit 128 can be used to specify whether cells should be specially processed for OAM cell insertion. If OAM bit 128 is set to "1," then OAM cell processing should be performed. If the received data cell is a credit update cell, then FSPP flow control queue number 130 is sent to an appropriate FSPP along with credit information. Terminated virtual path bit 132 does not serve any function in VCXT queue entry 90 because this bit is used to distinguish between VCXT range entries and VPXT queue entries. Valid bit 134 can be used to specify whether VCXT queue entry 90 is valid.
  • FIGURE 5 is a flow chart of a method 200 for mapping a data cell in a communication switch. Method 200 describes the operation of system 10. Method 200 begins at step 202 where a data cell, such as incoming ATM cell 31, is received at one of links 16-30 of TSPP 12. At this incoming ATM cell 31 is converted into internal cell 32 that contains the ingress link number.
  • TSPP 12 references a link boundary entry 64-78 in link boundary entry table 46, the link boundary entry corresponding to the link 16-30 at which the cell is received. For example, if internal data cell 32 is received at link 20 (labeled "LINK2"), boundary entry 68 is referenced.
  • TSPP 12 determines whether the enable bit in the corresponding link boundary entry is set to "0.” If so, TSPP 12 discards the data cell at step 206. Otherwise, if the enable bit is set to "1,” TSPP 12 determines whether the GFC bit in the link boundary entry is set to "1" at step 208. If so, then TSPP 12 sets the GFC field equal to "0000" for the look-up process at step 210.
  • TSPP 12 references the link table in VXT 40 corresponding to the link at which the data cell is received at step 212.
  • link "2" table 84 is referenced when internal cell 32 is received at LINK2.
  • link boundary entry 68 specifies a start 100 for link "2" table 84 in VXT 40.
  • Link boundary entry 68 also specifies a VP limit 102 which separates VCXT section 86 from VPXT section 88 in the link table 84.
  • TSPP 12 determines whether the VPI field 34 of the cell is within range. In other words, with regard to the example of internal cell 32, VPI field 34 of cell 32 must fall within VPXT section 88. If the VPI field is not within range, then at step 216, TSPP 12 determines whether range bit 48 in TSPP 12 is set to "1.” If so, TSPP 12 uses range queue number 50 to reference a queue descriptor for further processing of the data cell at step 218. Otherwise, if range bit 48 is set to "0," TSPP 12 discards the data cell at step 206.
  • TSPP 12 performs a VPXT look-up at step 220. In other words, TSPP 12 uses VPI field 34 in data cell 32 to reference either a VPXT queue entry or a VCXT range entry within VPXT section 88.
  • TSPP 12 determines whether the valid bit of the referenced entry is set to "0.” If so, the entry is not valid.
  • TSPP 12 determines whether exception bit 52 in TSPP 12 is set to "1" at step 224. If so, TSPP 12 uses exception queue number 54 to referenced a special descriptor for further processing of the data cell at step 226. If exception bit 52 is set to "0", TSPP 12 discards the cell at step 206.
  • TSPP 12 determines whether the valid bit in the data entry is not set to "0" at step 222, then the entry is valid. TSPP 12 then determines whether the terminated virtual path bit of the entry is set to "0" at step 228. If the terminated virtual path bit is not set to "0,” then the entry is a VPXT queue entry, such as VPXT queue entry 92. TSPP 12 then determines at step 230 whether the S bit 114 in the VPXT queue entry is set to "1.” If the S bit 114 is set to "0,” at step 236 TSPP 12 uses the TSPP VPS queue number from the VPXT queue entry to reference a queue descriptor from queue descriptor table 44 in memory 14.
  • TSPP 12 determines whether the value of the VCI field 36 in internal cell 32 is less than or equal to "31" at step 234. Typically, VCI values less than "31” are reserved for cells relating to special actions, such as establishing connections. If the value of VCI field 36 is greater than "31,” TSPP 12 uses the TSPP VSP queue number from the VPXT queue entry to reference a queue descriptor at step 236.
  • TSPP 12 processes the data cell as a virtual path service connection according to special action table 60 of TSPP 12 as follows. If an M bit 60a of VCI field 36 is set to "0,” TSPP 12 uses the TSPP VPS queue number from the VPXT queue entry at step 236. If the M bit 60a is set to "1" and the value of an A bit 60b of VCI field 36 is set to "0,” TSPP 12 discards data cell 32 at step 206. Otherwise, if both the M bit 60a and the A bit 60b are set to "1,” TSPP 12 uses special action queue number 62 in TSPP 12 to reference a queue descriptor contained within queue descriptor table 44 of memory 14.
  • TSPP 12 determines whether VCI field 36 of data cell 32 is within the established range. If not, TSPP 12 checks whether range bit 48 in TSPP 12 is set to "1" at step 216, as described above.
  • TSPP 12 performs a VCXT look-up in the retrieved link table at step 246. More specifically, TSPP 12 uses the VCI field 36 in the data cell 32 to reference a VCXT queue entry, such as VCXT queue entry 90, in VCXT section 86 of link table 84. At step 248, TSPP 12 determines whether the valid bit of the referenced VCXT queue entry is set to "0.” If so, the VCXT queue entry is not valid, and TSPP 12 determines whether exception bit 52 in TSPP 12 is set to "1" at step 224, as described above. If the valid bit in the VCXT queue entry is set to
  • TSPP 12 then processes the data cell 32 according to the OAM bit and a CLP bit of the cell at step 250 as follows. If the OAM bit is set to “1" and the CLP bit is set to "0,” TSPP 12 captures the OAM cell header at step 252. If the OAM bit and the CLP bit are both set to "1,” TSPP 12 captures the OAM payload, attaches the previously captured OAM header and then uses the TSPP VCS queue number in the entry to reference a queue descriptor from queue descriptor table 44 in memory 14 at step 236.
  • TSPP 12 determines whether the S bit 126 of the VCXT queue entry is set to "1" at step 254. If not, TSPP 12 uses TSPP VCS queue number of the VCXT queue entry to reference a queue descriptor from queue descriptor table 44 at step 236.
  • TSPP 12 processes the cell 32 as a VCI connection according to PT action table 56 in TSPP 12 as follows. If an S bit 56a in the VCXT queue entry is set to "0,” TSPP 12 uses the TSPP VCS queue number in the entry to reference a queue descriptor from queue descriptor table 44 at step 236. If S bit 56a in the VCXT queue entry is set to "1" and A bit 56b is set to "0,” then TSPP 12 discards data cell 32 at step 206.
  • TSPP 12 uses PT queue number 58 in TSPP 12 to reference a queue descriptor from queue descriptor table 42 of memory 14 at step 258. It should be understood that if a cell received at step 258
  • TSPP 12 is a credit update cell
  • TSPP 12 processes the cell in substantially the same manner as method 200 described above, except that FSPP flow control queue numbers in the data entries of a referenced link table will be used instead of the TSPP queue numbers.
  • Multiple internal cells 32 may be received and mapped to various queue descriptors in queue descriptor table 44. Some of these internal cells may have different VPI/VCI identifiers, but nonetheless will be mapped to the same descriptors using VXT 40. Consequently, because a separate queue descriptor is not maintained for each VPI/VCI identifier, the amount of memory needed to support the internal cells is substantially reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Système (10) permettant d'effectuer la mise en correspondance d'une cellule de données (32) dans un réseau de communications. Le système (10) comprend une table de conversion virtuelle (40) comportant au moins une entrée de file d'attente de table de conversion de trajet virtuel (92) et au moins une entrée de file d'attente de table de conversion de canal virtuel (90). Un dispositif de type 'vers le processeur du port de commutation' (12) pouvant accéder à la table de conversion virtuelle (40) possède au moins une liaison (16-30) à même de recevoir la cellule de données (32). Le dispositif 'vers le processeur de port de commutation' (12) fait la projection de la cellule de données reçue (32) sur un descripteur de file d'attente en utilisant la table de conversion virtuelle (40).
PCT/US1996/011917 1995-07-19 1996-07-18 Mise en correspondance d'une cellule de donnees dans un reseau de communications Ceased WO1997004560A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP9506863A JP2000501901A (ja) 1995-07-19 1996-07-18 通信交換機内のデータセルのマッピング
AU65007/96A AU6500796A (en) 1995-07-19 1996-07-18 Mapping a data cell in a communication switch
PCT/US1996/011917 WO1997004560A1 (fr) 1995-07-19 1996-07-18 Mise en correspondance d'une cellule de donnees dans un reseau de communications

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US149895P 1995-07-19 1995-07-19
US60/001,498 1995-07-19
PCT/US1996/011917 WO1997004560A1 (fr) 1995-07-19 1996-07-18 Mise en correspondance d'une cellule de donnees dans un reseau de communications

Publications (1)

Publication Number Publication Date
WO1997004560A1 true WO1997004560A1 (fr) 1997-02-06

Family

ID=38659408

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/011917 Ceased WO1997004560A1 (fr) 1995-07-19 1996-07-18 Mise en correspondance d'une cellule de donnees dans un reseau de communications

Country Status (3)

Country Link
JP (1) JP2000501901A (fr)
AU (1) AU6500796A (fr)
WO (1) WO1997004560A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999022566A2 (fr) 1997-11-04 1999-05-14 Koninklijke Philips Electronics N.V. Reseau de communication utilisant differentes proprietes de transmission

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5083269A (en) * 1989-01-10 1992-01-21 Kabushiki Kaisha Toshiba Buffer device suitable for asynchronous transfer mode communication
US5436893A (en) * 1992-12-05 1995-07-25 Netcom Limited ATM cell switch suitable for multicast switching
US5521915A (en) * 1993-01-29 1996-05-28 Alcatel Cit Synchronous digital channel cell assembly and disassembly device, synchronous digital channel switching center, and asynchronous digital channel switching center
US5528588A (en) * 1994-09-14 1996-06-18 Fore Systems, Inc. Multicast shared memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5083269A (en) * 1989-01-10 1992-01-21 Kabushiki Kaisha Toshiba Buffer device suitable for asynchronous transfer mode communication
US5436893A (en) * 1992-12-05 1995-07-25 Netcom Limited ATM cell switch suitable for multicast switching
US5521915A (en) * 1993-01-29 1996-05-28 Alcatel Cit Synchronous digital channel cell assembly and disassembly device, synchronous digital channel switching center, and asynchronous digital channel switching center
US5528588A (en) * 1994-09-14 1996-06-18 Fore Systems, Inc. Multicast shared memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999022566A2 (fr) 1997-11-04 1999-05-14 Koninklijke Philips Electronics N.V. Reseau de communication utilisant differentes proprietes de transmission

Also Published As

Publication number Publication date
JP2000501901A (ja) 2000-02-15
AU6500796A (en) 1997-02-18

Similar Documents

Publication Publication Date Title
US5905729A (en) Mapping a data cell in a communication switch
EP1005779B1 (fr) Dispositif de transfert d'ip et de commutation atm
US6272144B1 (en) In-band device configuration protocol for ATM transmission convergence devices
US6137798A (en) Connectionless network for routing cells with connectionless address, VPI and packet-identifying VCI
JP3129244B2 (ja) 通信制御装置
US6430187B1 (en) Partitioning of shared resources among closed user groups in a network access device
US20030026262A1 (en) Channel resource allocation arrangement and method
JPH06335079A (ja) Ａｔｍ網におけるセル多重化装置
EP1047280B1 (fr) Systèmes de communication
US6996109B2 (en) ATM cell transmitting/receiving device of ATM switching system
US6829248B1 (en) Integrated switching segmentation and reassembly (SAR) device
JP2005253077A (ja) Ａｔｍデータをリアルタイムで再組立するシステム、方法、およびプログラム
WO1997004560A1 (fr) Mise en correspondance d'une cellule de donnees dans un reseau de communications
AU729578B2 (en) ATM communications system for transmitting internet data packets
US7403533B2 (en) AAL2 switching apparatus and method
WO1999003237A1 (fr) Cellule mta augmentee de donnees tampon
EP0941592B1 (fr) Acheminement de paquets dans un systeme de telecommunications
WO1997004566A1 (fr) Conversion entre une cellule interne et des cellules a mode de transfert asynchrone de differents standards
JP3477851B2 (ja) 通信制御装置および交換機システム
KR100275769B1 (ko) 비동기 전송 모드 셀 처리 시스템의 메모리 운영방법
KR100455266B1 (ko) 아이피 망에서의 에이티엠 셀 전송 방법 및 장치
KR0185860B1 (ko) 에이에이엘 타입 1에서의 고정비트율 데이터 처리장치 및 그처리방법
JPH07321794A (ja) 端末収容装置およびその動作方法
JPH05136809A (ja) ヘツダ処理方式
WO1997004569A1 (fr) Identification de ports et de lignes

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE HU IL IS JP KE KG KP KR KZ LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TR TT UA UG UZ VN AM AZ BY KG KZ MD RU TJ TM

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): KE LS MW SD SZ UG AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
ENP Entry into the national phase

Ref country code: JP

Ref document number: 1997 506863

Kind code of ref document: A

Format of ref document f/p: F

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: CA