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WO1997040527A1 - Procede de realisation d'une zone dopee dans un substrat de semi-conducteur - Google Patents

Procede de realisation d'une zone dopee dans un substrat de semi-conducteur Download PDF

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Publication number
WO1997040527A1
WO1997040527A1 PCT/DE1997/000707 DE9700707W WO9740527A1 WO 1997040527 A1 WO1997040527 A1 WO 1997040527A1 DE 9700707 W DE9700707 W DE 9700707W WO 9740527 A1 WO9740527 A1 WO 9740527A1
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WO
WIPO (PCT)
Prior art keywords
trench
main surface
doped
semiconductor substrate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE1997/000707
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German (de)
English (en)
Inventor
Ulrike GRÜNING
Volker Lehmann
Reinhard Stengl
Hermann Wendt
Herbert Schäfer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of WO1997040527A1 publication Critical patent/WO1997040527A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/058—Forming charge compensation regions, e.g. superjunctions by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures

Definitions

  • the semiconductor technology is based on the production of doped regions in crystalline semiconductor substrates.
  • dopant is introduced into the semiconductor substrate, so that the electrical properties change.
  • the crystalline structure of the semiconductor substrate remains essentially unchanged in the doped regions.
  • Doped areas are usually produced by diffusion or implantation.
  • the dopant introduced is then electrically activated in a tempering step. Since the diffusion in the semiconductor substrate is essentially isotropic, doped regions produced by diffusion have a lateral extent which is essentially equal to or greater than their depth. The depth of doped areas created by implantation depends on the energy with which the implantation takes place. Doped areas with a depth of up to approximately 5 ⁇ m can be produced by implantation.
  • doped regions are required which have a greater depth than width.
  • Such doped areas are often referred to as vertical doping.
  • such doped regions should have a depth corresponding to the thickness of the semiconductor substrate.
  • the invention is based on the problem of specifying a method for producing a doped region in a semiconductor substrate, with which doped regions of great depth can be produced. This problem is solved by a method according to claim 1. Further refinements of the invention emerge from the remaining claims.
  • a trench is produced in a main surface of a semiconductor substrate.
  • a doped layer is then grown epitaxially.
  • dopant is added so that the doped layer grows up in situ.
  • the doped layer fills the trench.
  • the part of the doped layer arranged in the trench forms the doped region.
  • the dimensions of the doped region depend exclusively on the geometry of the trench.
  • the application of the method can be used particularly advantageously for the production of doped regions with great depth.
  • doped regions with a depth of 5 ⁇ m to 500 ⁇ m, for example 200 ⁇ m and a width of 0.2 ⁇ m to 40 ⁇ m, for example 1 ⁇ m can be realized.
  • the ratio of depth to width is greater than 1.
  • the doped region Since the trench is filled by the doped layer, which is grown epitaxially, the doped region has essentially the same crystal structure as the semiconductor substrate.
  • doped regions both of the same conductivity type as the substrate and of the opposite conductivity type as the substrate can be produced.
  • the dopants are built into the doped layer and electrically activated during epitaxial growth of the doped layers.
  • Tempering step for electrical activation of the dopants is therefore not necessary in the method according to the invention.
  • Parts of the doped layer located on the main surface of the semiconductor substrate can be removed by anisotropic etching or chemical / mechanical polishing.
  • the trench has any cross section parallel to the main surface.
  • the trench can have a circular, square, rectangular, elongated, strip-shaped or annular cross section parallel to the main surface.
  • the trench is made, for example, by anisotropic etching using a mask.
  • the trench is produced by electrochemical etching.
  • the semiconductor substrate is brought into contact with an electrolyte with the main surface.
  • the semiconductor substrate is connected to the electrolyte as an anode.
  • minority charge carriers move in the semiconductor substrate to the main surface in contact with the electrolyte.
  • a space charge zone forms on this surface. Since the field strength in the area of depressions in the surface is greater than outside it, the minority charge carriers preferably move to these points. This leads to a structuring of the surface. The deeper an initially small unevenness becomes due to the etching, the more minority charge carriers move there because of the increased field strength and the stronger the etching attack at this point. In this way, holes grow in the main surface of the semiconductor substrate.
  • Holes that cross the entire semiconductor substrate can be produced by means of electrochemical etching.
  • the arrangement of the holes can be predetermined by providing the main surface with recesses on which the etching attack begins with electrochemical etching.
  • the depressions are formed, for example, by masked etching with an alkaline etching. In order to produce strip-shaped or ring-shaped trenches, these depressions are arranged in such a way that adjacent holes grow together during electrochemical etching.
  • the electrochemical etching takes place in a fluoride-containing, acidic electrolyte.
  • the epitaxy process is preferably carried out in a parameter range in which the epitaxy is limited by the surface reaction. This ensures that the doped layer grows uniformly on the entire surface, that is to say both in the area of the main surface and in the trench.
  • the epitaxial process in the temperature range between 700 ° and 900 °, preferably 850 ° C., in the pressure range between 1 and 20 torr, preferably 10 torr, with at least water is preferably carried out on a semiconductor substrate which comprises monocrystalline silicon at least in the region of the main surface ⁇ substance and dichlorosilane process gas performed.
  • the dopant is added in the form of diborane, phosphorus or arsine.
  • the dopant is added from a storage container which contains diluted dopant in a carrier gas, for example H2 or Ar.
  • a proportion of the dopant of 100 ppm in a gas mixture the flow rate of the gas mixture is set in the range between 0.5 sccm and 6 sccm, preferably 3 sccm.
  • the epitaxy takes place with limited surface reaction.
  • the trench preferably has a slightly conical cross section. This means that the side walls of the trench are tilted a few degrees against the normal of the main surface. This tilt angle is preferably 0.01 ° to 3 °. This ensures a void-free filling of the trench.
  • the method can advantageously be used in the production of power components with deep-reaching doped areas and / or many adjacent low-doped pn junctions.
  • Figure 1 shows a substrate with trenches.
  • FIG. 2 shows the substrate with an epitaxially grown first doped layer and an epitaxially grown second doped layer.
  • Figure 3 shows the substrate after removing the on the
  • Main surface arranged parts of the first doped layer and the second doped layer.
  • a substrate 1 made of, for example, n-doped, monocrystalline silicon is brought into contact with an electrolyte with a main surface 2.
  • the substrate 1 has depressions which are formed, for example, with the aid of a photoresist mask and subsequent alkaline etching with KOH.
  • the electrolyte contains fluoride and is acidic. It contains a hydrofluoric acid concentration of 1 to 50 percent by weight, preferably 6 percent by weight.
  • An oxidizing agent for example hydrogen peroxide, can be added to the electrolyte to suppress the development of hydrogen bubbles on the main surface 2 of the substrate 1.
  • a voltage of, for example, 3 volts is applied between the substrate 1 and the electrolytes.
  • the substrate 1, which has a specific resistance of 5 ⁇ cm, for example, is connected as an anode.
  • the substrate 1 is illuminated from a surface opposite the main surface 2.
  • a current density of 10 mA / cm * ⁇ is set in the substrate 1 by the illumination.
  • trenches 3 are etched into the main surface 2 (see FIG. 1).
  • the trenches 3 have an essentially circular cross section in the region of the main surface 2.
  • the trenches 3 In the area of the main surface 2, the trenches 3 have a diameter of, for example, 1 ⁇ m.
  • the trenches 3 are produced with a depth of, for example, 200 ⁇ m.
  • the trenches 3 have slightly conical side walls which are tilted by 0.1 ° with respect to the normal to the main surface 2 (this tilting is not shown in the figures).
  • a first doped layer 4 is grown on the main surface 2 and the surface of the trenches 3.
  • the epitaxial process is carried out, for example, at 850 ° C., 10 torr with 40 slm hydrogen and 200 sccm dichlorosilane. Phosphon or arsine from a gas mixture containing H2 or Ar and 100 ppm dopant is added as a dopant with a flow rate of 3 sccm.
  • the first doped layer 4 is n + -doped with a dopant concentration of 10 ⁇ 7 cm " 3.
  • the first doped layer 4 is grown in a layer thickness of, for example, 0.2 ⁇ m. Since the epitaxy process is in the parameter range used is surface reaction limited, the first doped layer 4 grows with an essentially constant layer thickness.
  • a second doped layer 5 is grown on the first doped layer 4 in a further epistemic process.
  • the second epitaxial process is carried out at 850 ° C., 10 torr with 40 slm hydrogen and 200 sccm dichlorosilane.
  • diborane from a gas mixture containing H2 or Ar and 100 ppm diborane is added at a flow rate of 3 sccm.
  • the second doped layer 5 is p + -doped with a dopant concentration of, for example, 10- 1 - 7 cm " 3.
  • the second doped layer 5 is grown in a layer thickness of, for example, 0.3 ⁇ m.
  • the first doped layer 4 and the second doped layer 5 completely fill the trenches 3 (see FIG. 2).
  • the second main surface of the substrate 1 is then exposed outside the trenches 3 by chemical / mechanical polishing (see FIG. 3).
  • p + -doped regions 5 'and n + -doped regions 4' are formed in the region of the trenches 3.
  • the crystal quality in the p + -doped regions 5 'and in the n + -doped regions 4' is comparable to the crystal quality of the substrate 1.
  • the n + -doped regions 4 'and the p + -doped regions 5' and the parts of the substrate 1 arranged in between form a dense sequence of pn junctions.
  • the p + -doped regions 5 'and the ⁇ -doped regions 4 "extend deeper into the substrate 1 than corresponds to their lateral dimensions.
  • the exemplary embodiment described can be modified in that the n + -doped layer 4 completely fills the trenches 3 or that the n + -doped layer 4 is omitted and the p + -doped layer 5 is grown on the surface of the trenches 3 and the trenches 3 completely filled.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)

Abstract

Pour réaliser une zone dopée dans un substrat de semi-conducteur (1), on produit une tranchée (3) que l'on remplit d'une couche de semi-conducteur (4, 5) dopée, formée par épitaxie. Ce procédé convient particulièrement à la réalisation de zones dopées profondes, de ce que l'on appelle des dopages verticaux, ainsi que de nombreuses jonctions p-n faiblement dopées telles que, par exemple, celles requises dans les nouveaux composants de puissance.
PCT/DE1997/000707 1996-04-22 1997-04-07 Procede de realisation d'une zone dopee dans un substrat de semi-conducteur Ceased WO1997040527A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19615920 1996-04-22
DE19615920.2 1996-04-22

Publications (1)

Publication Number Publication Date
WO1997040527A1 true WO1997040527A1 (fr) 1997-10-30

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999023704A1 (fr) * 1997-11-03 1999-05-14 Infineon Technologies Ag Composant semi-conducteur
US6337499B1 (en) 1997-11-03 2002-01-08 Infineon Technologies Ag Semiconductor component
WO2007107461A1 (fr) * 2006-03-21 2007-09-27 Robert Bosch Gmbh Procédé de fabrication d'une structure semi-conductrice et structure semi-conductrice correspondante
DE102004010676B4 (de) * 2003-03-07 2009-04-16 Fuji Electric Holdings Co., Ltd. Verfahren zur Herstellung eines Halbleiterwafers
DE10053463B4 (de) * 1999-10-28 2012-03-01 Denso Corporation Verfahren zur Herstellung eines Halbleitersubstrats

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3740276A (en) * 1970-08-24 1973-06-19 Texas Instruments Inc Multi-component semiconductor network and method for making same
GB2017401A (en) * 1977-12-23 1979-10-03 Gen Electric Planar gate turn-off field controlled thyristors and method of making the same
EP0296348A1 (fr) * 1987-05-27 1988-12-28 Siemens Aktiengesellschaft Procédé d'attaque pour creuser des trous ou des sillons dans du silicium de type n
JPH02111062A (ja) * 1988-10-20 1990-04-24 Matsushita Electric Ind Co Ltd 半導体メモリの製造方法
EP0390522A2 (fr) * 1989-03-29 1990-10-03 Canon Kabushiki Kaisha Transistor bipolaire et appareil de conversion photoélectrique utilisant celui-ci
US5216275A (en) * 1991-03-19 1993-06-01 University Of Electronic Science And Technology Of China Semiconductor power devices with alternating conductivity type high-voltage breakdown regions
DE4310205C1 (de) * 1993-03-29 1994-06-16 Siemens Ag Verfahren zur Herstellung einer Lochstruktur in einem Substrat aus Silizium
US5438215A (en) * 1993-03-25 1995-08-01 Siemens Aktiengesellschaft Power MOSFET

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3740276A (en) * 1970-08-24 1973-06-19 Texas Instruments Inc Multi-component semiconductor network and method for making same
GB2017401A (en) * 1977-12-23 1979-10-03 Gen Electric Planar gate turn-off field controlled thyristors and method of making the same
EP0296348A1 (fr) * 1987-05-27 1988-12-28 Siemens Aktiengesellschaft Procédé d'attaque pour creuser des trous ou des sillons dans du silicium de type n
JPH02111062A (ja) * 1988-10-20 1990-04-24 Matsushita Electric Ind Co Ltd 半導体メモリの製造方法
EP0390522A2 (fr) * 1989-03-29 1990-10-03 Canon Kabushiki Kaisha Transistor bipolaire et appareil de conversion photoélectrique utilisant celui-ci
US5216275A (en) * 1991-03-19 1993-06-01 University Of Electronic Science And Technology Of China Semiconductor power devices with alternating conductivity type high-voltage breakdown regions
US5438215A (en) * 1993-03-25 1995-08-01 Siemens Aktiengesellschaft Power MOSFET
DE4310205C1 (de) * 1993-03-29 1994-06-16 Siemens Ag Verfahren zur Herstellung einer Lochstruktur in einem Substrat aus Silizium

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 014, no. 328 (E - 0952) 13 July 1990 (1990-07-13) *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999023704A1 (fr) * 1997-11-03 1999-05-14 Infineon Technologies Ag Composant semi-conducteur
US6337499B1 (en) 1997-11-03 2002-01-08 Infineon Technologies Ag Semiconductor component
DE10053463B4 (de) * 1999-10-28 2012-03-01 Denso Corporation Verfahren zur Herstellung eines Halbleitersubstrats
DE10066433B4 (de) * 1999-10-28 2013-04-18 Denso Corporation Verfahren zur Herstellung eines Halbleitersubstrats
DE102004010676B4 (de) * 2003-03-07 2009-04-16 Fuji Electric Holdings Co., Ltd. Verfahren zur Herstellung eines Halbleiterwafers
WO2007107461A1 (fr) * 2006-03-21 2007-09-27 Robert Bosch Gmbh Procédé de fabrication d'une structure semi-conductrice et structure semi-conductrice correspondante
US8148234B2 (en) 2006-03-21 2012-04-03 Robert Bosch Gmbh Method for manufacturing a semiconductor structure, and a corresponding Semiconductor Structure

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