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WO1996037954A2 - Circuit pour generer une impulsion d'horloge commandee par porte a la demande - Google Patents

Circuit pour generer une impulsion d'horloge commandee par porte a la demande Download PDF

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Publication number
WO1996037954A2
WO1996037954A2 PCT/US1996/008100 US9608100W WO9637954A2 WO 1996037954 A2 WO1996037954 A2 WO 1996037954A2 US 9608100 W US9608100 W US 9608100W WO 9637954 A2 WO9637954 A2 WO 9637954A2
Authority
WO
WIPO (PCT)
Prior art keywords
logic state
clock signal
transitions
inactive
active
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1996/008100
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English (en)
Other versions
WO1996037954A3 (fr
Inventor
Christopher E. Phillips
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Priority to KR1019970700563A priority Critical patent/KR970705233A/ko
Priority to EP96917876A priority patent/EP0772909A2/fr
Publication of WO1996037954A2 publication Critical patent/WO1996037954A2/fr
Publication of WO1996037954A3 publication Critical patent/WO1996037954A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Definitions

  • the present invention relates to gated clock generation circuits and, in particular, to a demand- based gated clock generation circuit which provides robust clocking at high operating frequencies, even under severe skew conditions.
  • a register 10 is connected to receive data, via a two-to-one data selector 12, in response to rising edge transitions of a system clock signal, CKl.
  • the two-to-one data selector 12 selects between recirculated data 14, recirculated from the register 10, and externally provided data 16 in response to an enable signal, EN.
  • EN enable signal
  • the recirculated data 14 is clocked into the register 10.
  • the enable signal, EN is high, the externally supplied data 16 is clocked into the register 10.
  • the register 10 is clocked even when no data is being provided externally. Since it is not desired to change the contents of the register 10 when no data is being provided externally
  • the register 10 is unnecessarily clocked in this situation, and power is unnecessarily consumed.
  • gated register clocking circuits There have been attempts to implement "gated" register clocking circuits. With gated register clocking, a register is clocked only when it is desired to change the contents of the register. However, these circuits typically require strict control of set-up and hold times. Particularly in high frequency applications, clock skewing may cause violation of the strict set-up and hold time requirements.
  • the present invention is a demand-based clocking circuit for generating a demand-based gated clock signal.
  • a latch circuit e.g., a D-type flip flop
  • the enable signal has an active logic state and an inactive logic state.
  • a clock input is connected to receive a first input clock signal having periodic clock cycles. In each of the clock cycles, the first input clock signal has a first logic state during a first portion of the clock cycle and transitions to a second logic state during a second portion of the clock cycle.
  • the data output is connected to provide a shifted enable signal that transitions from the inactive logic state to the active logic state on the first transition of the first input clock signal from the first to the second logic state after the enable signal transitions from the inactive to the active logic state, and that transitions from the active to the inactive logic state on the first transition of the first input clock signal from the first to the second logic state after the enable signal transitions from d e active to the inactive logic state.
  • a logic circuit is responsive to the shifted enable signal and to a second input clock signal.
  • the second input clock signal has periodic clock cycles. In each of the clock cycles, the second input clock signal has the second logic state during a first portion of the cycle and transitions to the first logic state during a second portion of the cycle.
  • the logic circuit provides the gated clock signal such that the gated clock signal transitions from the inactive to the active logic state on the first transition of the second input clock signal from the first to the second logic state after the shifted enable signal transitions from the inactive to the active logic state, and that transitions from the active to the inactive logic state on the transition of the shifted enable signal from the active to the inactive logic state.
  • Fig. 1 is a block diagram illustrating a conventional high speed register clocking system.
  • Fig. 2 is a block diagram illustrating a gated clock generation circuit in accordance with the present invention.
  • Fig. 3 is a timing diagram which illustrates the timing of signals which may be provided to, and created by, the circuit of Fig. 2.
  • Fig. 2 illustrates a circuit 50, in accordance with the present invention.
  • the circuit 50 generates a gated clock, CLK .GATED, for clocking data into and/or out of the register 10.
  • Fig. 3 illustrates the timing of the signals provided to, and created by, the circuit 50. It should be noted that the clock signal CKl, shown in Fig. 2 and the waveform of which is shown in Fig. 3, is the same signal as the signal similarly labelled in Fig. 1.
  • a latch 52 receives an enable signal EN' at the data input of the latch 52.
  • the enable signal EN' is asserted in CKl clock period T .
  • enable signal EN' is asserted during the period of clock signal CKl that is previous to the clock cycle in which it is desired to transfer data into register 10.
  • the latch 52 latches the enable signal EN' responsive to rising edges of a clock signal CK2.
  • CK2 has a period identical to the period of CKl, but CK2 is phase-shifted from clock signal CKl by 180°.
  • the latch 52 has the effect of shifting the enable signal EN' by half of a clock period T.
  • the shifted enable signal EN_SH "straddles" the boundary between the CKl clock period T., and CKl clock period T disregard.
  • an AND device 54 receives the clock signal CKl and the shifted enable signal EN_SH.
  • the AND device 54 provides a gated clock signal CK_GATED in response thereto. That is, the shifted enable signal EN_SH is clocked high by the rising edge of clock signal CKl to
  • SUBSTTTUTE SHEET (RULE 26) produce the gated clock signal CK_GATED, and the gated clock signal CK_GATED remains high while bom the shifted enable signal EN_SH and the clock signal CKl remain high.
  • the gated clock signal CK_GATED is provided to die register 10 for clocking data into the register 10 only upon "demand".
  • the circuit 50 provides robust clocking for register 10 even if mere is skew in the clock signals CKl and CK2. While Fig. 2 shows the gated clock signal CK_GATED being provided directly to the register 10, it may be desirable to provide additional drive to the gated clock signal, which can be accomplished by conventional means.
  • clock signal CK2 since only the rising edges of clock signal CK2 are employed in latching the enable signal EN', there is no requirement that the duty cycle of clock signal CK2 have any particular relationship to the duty cycle of clock signal CKl. Furthermore, there is no requirement that clock signal CK2 be precisely 180° out of phase from clock signal CKl. However, the rising edges of clock signal CK2 should not occur while clock signal CKl is in a high state, since this would cause an unwanted glitch in the gated clock signal CK_GATED.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention concerne un circuit d'horloge à la demande. Ce circuit génère un signal d'horloge commandé par porte à la demande. Une entrée de données de circuit de verrouillage reçoit un signal de validation. Une entrée d'horloge reçoit un premier signal d'horloge d'entrée périodique. Une sortie de données de circuit de verrouillage fournit un signal de validation décalé qui passe d'un état logique inactif à un état logique actif lorsque le premier signal d'horloge d'entrée passe pour la première fois du premier état logique au deuxième état logique, après que le signal de validation soit passé de l'état inactif à l'état logique actif. Le signal de validation décalé passe de l'état logique actif à l'état logique inactif lorsque le premier signal d'horloge d'entrée passe pour la première fois du premier état logique au deuxième état logique, après que le signal de validation soit passé de l'état logique actif à l'état logique inactif. Un circuit logique fournit le signal d'horloge commandé par porte de telle sorte que ce signal d'horloge commandé par porte passe de l'état logique inactif à l'état logique actif lorsqu'un deuxième signal d'horloge d'entrée passe pour la première fois du premier état logique au deuxième état logique, après que le signal de validation décalé soit passé de l'état logique inactif à l'état logique actif, et qu'il passe de l'état logique actif à l'état logique inactif lorsque le signal de validation décalé passe de l'état logique actif à l'état logique inactif.
PCT/US1996/008100 1995-05-26 1996-05-24 Circuit pour generer une impulsion d'horloge commandee par porte a la demande Ceased WO1996037954A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019970700563A KR970705233A (ko) 1995-05-26 1996-05-24 요구에 기초한 게이트 클록 발생 회로(circuit for generating a demand-based gated clock)
EP96917876A EP0772909A2 (fr) 1995-05-26 1996-05-24 Circuit pour generer une impulsion d'horloge commandee par porte a la demande

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/451,219 1995-05-26
US08/451,219 US5598112A (en) 1995-05-26 1995-05-26 Circuit for generating a demand-based gated clock

Publications (2)

Publication Number Publication Date
WO1996037954A2 true WO1996037954A2 (fr) 1996-11-28
WO1996037954A3 WO1996037954A3 (fr) 1996-12-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/008100 Ceased WO1996037954A2 (fr) 1995-05-26 1996-05-24 Circuit pour generer une impulsion d'horloge commandee par porte a la demande

Country Status (3)

Country Link
US (1) US5598112A (fr)
EP (1) EP0772909A2 (fr)
WO (1) WO1996037954A2 (fr)

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US5811987A (en) * 1995-06-02 1998-09-22 Advanced Micro Devices, Inc. Block clock and initialization circuit for a complex high density PLD
DE19844936C2 (de) * 1998-09-30 2001-02-01 Siemens Ag Schaltung zur Erzeugung eines Ausgangssignals in Abhängigkeit von zwei Eingangssignalen
US6275081B1 (en) 1999-06-02 2001-08-14 Adaptec, Inc. Gated clock flip-flops
JP3485885B2 (ja) * 2000-12-11 2004-01-13 三洋電機株式会社 半導体集積回路装置の設計方法
KR101074424B1 (ko) * 2004-11-05 2011-10-17 삼성전자주식회사 고속 저전력 클록 게이티드 로직 회로
TW200703906A (en) * 2005-07-11 2007-01-16 Via Tech Inc Circuit and related method for clock gating
TW200703910A (en) * 2005-07-11 2007-01-16 Via Tech Inc Circuit and related method for clock gating
DE102006004346A1 (de) * 2006-01-30 2007-10-18 Deutsche Thomson-Brandt Gmbh Datenbusschnittstelle mit abschaltbarem Takt
US7849349B2 (en) * 2007-03-28 2010-12-07 Qimonda Ag Reduced-delay clocked logic
US7902878B2 (en) * 2008-04-29 2011-03-08 Qualcomm Incorporated Clock gating system and method
KR101252698B1 (ko) * 2009-04-29 2013-04-09 퀄컴 인코포레이티드 클록 게이팅 시스템 및 방법

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US4423337A (en) * 1981-07-13 1983-12-27 Tektronix, Inc. Gate circuit for a universal counter
DE3428393A1 (de) * 1984-08-01 1986-02-13 Siemens AG, 1000 Berlin und 8000 München Taktgesteuerte kippschaltung
JPS6264116A (ja) * 1985-09-13 1987-03-23 Nec Ic Microcomput Syst Ltd マスタ−スレ−ブ型フリツプフロツプ
JPS6295017A (ja) * 1985-10-21 1987-05-01 Nec Ic Microcomput Syst Ltd マスタ・スレーブ形フリツプフロツプ回路
JPH0611132B2 (ja) * 1986-12-24 1994-02-09 株式会社東芝 同期回路
JPH02246610A (ja) * 1989-03-20 1990-10-02 Fujitsu Ltd マスタ・スレーブ型ｄフリップフロップ回路
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JP2621993B2 (ja) * 1989-09-05 1997-06-18 株式会社東芝 フリップフロップ回路
JPH0793558B2 (ja) * 1989-12-15 1995-10-09 安藤電気株式会社 タイミング信号遅延回路
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Also Published As

Publication number Publication date
WO1996037954A3 (fr) 1996-12-27
EP0772909A2 (fr) 1997-05-14
US5598112A (en) 1997-01-28

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