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WO1996037950A1 - Circuits de retour couples par canaux - Google Patents

Circuits de retour couples par canaux Download PDF

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Publication number
WO1996037950A1
WO1996037950A1 PCT/US1995/014933 US9514933W WO9637950A1 WO 1996037950 A1 WO1996037950 A1 WO 1996037950A1 US 9514933 W US9514933 W US 9514933W WO 9637950 A1 WO9637950 A1 WO 9637950A1
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Prior art keywords
ccsc
gate
channel
circuit
substrate
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PCT/US1995/014933
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English (en)
Inventor
Charles F. Neugebauer
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Arithmos Inc
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Arithmos Inc
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Priority to PCT/US1995/014933 priority Critical patent/WO1996037950A1/fr
Priority to AU46385/96A priority patent/AU4638596A/en
Publication of WO1996037950A1 publication Critical patent/WO1996037950A1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/005—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices

Definitions

  • the present invention relates to electronic circuits. Specifically, the present invention relates to amplifiers that have channel coupled feedback circuits to perform signal processing functions.
  • Feedback is an important aspect of many signal pro ⁇ cessing circuits.
  • feedback consists of comparing the actual output of the system with the desired output and making corrections accordingly.
  • the output voltage of the amplifier should be a multiple of the input voltage. Therefore, in a feedback amplifier, the input voltage is compared with an attenuated version of the output voltage.
  • Negative feedback is the process of coupling the output voltage of an amplifier back in such a way as to cancel some of the input voltage. While negative feedback lowers the gain of the amplifier, it serves to improve other characteristics of the amplifier, such as freedom from distortion and non-linearity, flatness of response and predictability.
  • Figure 2 shows a conventional inverting, fixed-gain amplifier circuit having a resistor (9) in the feedback loop. Based upon the facts that (a) the amplifier (10) adjusts its output so as to make the voltage difference between its inputs equals zero and (b) the inputs of the amplifier draw virtually no current, the following relationship is evident:
  • the voltage gain of the amplifier (V out /V in ) is equal to the ratio of the two resistors (-R- j /R . Therefore, one can change the gain of an inverting, fixed-gain amplifier by altering the resis ⁇ tivity of the feedback resistors. See Horowitz and Hill, pp. 177-178.
  • the inverting amplifier shown in Figure 2 is a useful device for analog signal processing.
  • An analog system carries signals in the form of voltages, currents, charg ⁇ es, etc., that are continuous functions of a continuous time variable.
  • Some typical examples of analog signal processors are audio amplifiers and telecommunications systems.
  • each signal is represented by a sequence of numbers or discrete values.
  • a typical example of a digital system is a microprocessor in which the computations are done in terms of "Is" and "0s" .
  • analog signal processing systems were not widely implemented using monolithic integrated circuit (IC) technology, particularly metal- oxide semiconductor (MOS) technology, primarily because most analog signal processing circuits require precise passive components, such as resistors and capacitors. Monolithically fabricating an absolute precision resistor or capacitor is still difficult given the capability of current IC fabrication technology.
  • IC integrated circuit
  • MOS metal- oxide semiconductor
  • FIG. 3 shows a switched capacitor circuit that is equivalent in function to the inverting, fixed- gain amplifier of Figure 2.
  • the accuracy of switched capacitor circuits relies primarily upon the ratios of monolithic capacitors, rather than the precision of each capacitor individually.
  • the matching of two identical capacitors within the same die area of most MOS ICs can be highly accurate and can be in the range of 0.1 - 1%. Therefore, the accuracy of analog processing circuits using switched capacitors can be improved over circuits using monolithic resistors.
  • Monolithic capacitors generally can be classified into either of two types depending upon the host material for the thermally grown silicon dioxide dielectric layer: (1) capacitors formed on heavily doped crystalline silicon ( Figure 4) or (2) capacitors formed on poly-crystalline silicon (polysilicon) ( Figure 5) .
  • Conventional switched capacitor circuits are currently fabricated in special complementary metal-oxide semicon- ductor (CMOS) fabrication processes that have special fabrication steps required to implement accurate capaci ⁇ tors.
  • CMOS complementary metal-oxide semicon- ductor
  • the capacitor shown in Figure 4 is manufactured by growing a thin oxide over the top of the silicon crystal and diffusing either n+ or p+ ions through the thin oxide into the silicon crystal (20) . After this heavy (ion) diffusion step, a conducting layer of either metal or polysilicon (19) is placed on top of the thin oxide.
  • the diffused capacitor plate requires an extra lithography step. This extra lithography step can adversely impact yield and hence result in a higher fabrication cost.
  • the bottom (diffusion) electrode (20) has a large non-linear capacitance (voltage coefficient) due to coupling to the substrate (21) (also known as the bulk) .
  • the substrate (21) also known as the bulk
  • Gregorian and Temes p.89.
  • This heavy diffusion-to- substrate back plate also has a junction leakage current associated with it. Id.; Gray and Meyer, Analysis and Design of Analog Integrated Circuits. John Wiley & Sons (1984), p. 148. Therefore, in order to achieve accurate analog processing, the voltage on the diffusion electrode (20) cannot be permitted to float, or parasitic capaci ⁇ tance problems and leakage induced drift will be signifi- cant.
  • a thin oxide must be grown on top of the polysilicon layer (24) .
  • Growing a thin oxide on top of polysilicon leads to accuracy and yield problems, because the granularity of the polysilicon surface presents a poor oxidation host surface.
  • a thicker oxide layer is grown on top of the polysilicon layer to help overcome the granularity prob- lem. But the capacitance per unit area of the capacitor is reduced when the insulating layer is thickened, thereby effectively increasing the size of the capacitors required to implement a desired function.
  • top electrode (23) is metal or polysilicon. If metal is used, metal ions can diffuse into the thin oxide layer, thereby reducing the insulating properties of the oxide layer. Also, using metal as an electrode leads to accuracy problems because the conductance of the metal electrode is effectively increased by the amount of metal interconnect (22) that is bonded to the capacitor.
  • both the top and bottom electrodes (23, 24) are poly- silicon
  • the cost of manufacturing the IC will be in ⁇ creased. Since an extra mask step is necessary to add the second polysilicon layer, a lower IC yield can be expect ⁇ ed.
  • one object of the present invention is to provide for mono ⁇ lithic electronic amplification circuits that have feed ⁇ back and analog signal processing functions that do not require the construction of monolithic resistors or thermally-grown capacitors.
  • a second object of the present invention is to provide accurate analog signal processing circuits that can be fabricated in conventional digital processes, thereby eliminating the need for specialty fabrication processes for many signal processing functions and conse ⁇ quently decreasing the cost of manufacturing these cir ⁇ cuits.
  • a third object of the present invention is to in- crease the accuracy of many analog processing circuits by eliminating the need for monolithic passive components, such as capacitors and resistors.
  • a fourth object of the present invention is to in ⁇ crease the integration density of many analog signal processing circuits by eliminating the need for resistor and capacitor components. Increasing circuit density will serve to reduce silicon requirements to implement many circuit functions and thereby reduce manufacturing costs for these circuits.
  • a fifth object of the present invention is to provide analog signal processing circuits that can replace conven ⁇ tional switched capacitor circuits and can be monolithi ⁇ cally integrated on the same substrate as high density digital CMOS circuitry. Other objects of the present invention will become apparent as the description proceeds.
  • the present invention relates to the novel technology of channel coupled feedback circuits for making accurate and reliable signal processing circuitry.
  • channel coupled feedback circuits circuit functions previously performed by switched capacitor or resistor components can be implemented in conventional digital IC fabrication processes that do not require or provide for a special capacitor or resistor layer.
  • many analog and digital signal processing functions that are currently capable of monolithic integration can now be implemented solely with semiconductor devices using the present invention, thereby completely eliminating the need for passive components, such as capacitors and resistors for these circuit functions.
  • an inverting, fixed-gain amplifier is con ⁇ structed solely with field effect transistors (FETs) .
  • channel coupled feedback technology used in the present invention is characterized by (a) one or more channel reset device(s) (1) that serve to fix the amount of charge in the channel during the computation phase, and (b) two or more channel coupled semiconductors (CCSCs) (3) that perform the signal pro ⁇ cessing function in conjunction with (c) a means (5) for sensing charge transfer within the channel, which means may also maintain the surface voltage of the channel constant.
  • the CCSCs (3) are preferentially FETs and are electronically connected or coupled to each other and to the channel reset device(s) (1).
  • the channel reset device(s) (1) preferably are FETs, but can be any means for controlling the flow of charge into the channel.
  • the means (5) for sensing the charge transferred within the channel and for maintaining the surface voltage of the channel constant is preferentially an operational ampli- fier.
  • signal processing operations are per ⁇ formed in the present invention by setting the channel to a fixed reset voltage having a fixed amount of charge.
  • An input signal (6) is applied to one or more of the CCSCs (3) which will cause charge to be transferred under the CCSCs within the channel if the input signal differs from the reset voltage.
  • channel coupled semiconductor devices can perform many feedback and signal processing functions, including but not limited to, fixed- gain, sample and hold, addition, subtraction, offset compensation, integration, differentiation, analog-to- digital conversion, digital-to-analog conversion, switch- able gain, ladder filtering and linear transform computa ⁇ tion.
  • channel coupled feedback operation can be summarized as follows.
  • a reset signal is applied to the channel reset device(s) , so as to allow charge to fill the channel from a charge source.
  • the surface potential of the channel is fixed at a desired level during this phase.
  • the reset signal Upon the removal of the reset signal, the channel is disconnected from the charge source.
  • the channel reset device is one FET.
  • a reset voltage is applied to the gate of the channel reset FET permitting the substrate under the FET gate to become conductive.
  • a post-reset voltage is applied to the gate, causing the channel reset FET to become non-conductive and to act as a barrier preventing charge from moving either into or out of the channel.
  • the input signal (e.g., a voltage) to be processed is applied to the gate of at least one of the channel coupled semiconductors within the channel.
  • the channel coupled semiconductors are FETs. Applying the input signal to the gate of one of the FETs causes the amount of charge under the gate of that FET to change, which change is proportional to the input signal voltage applied to the gate and the area of the gate. The charge is transferred to or from the substrate underneath the gates of the other FET(s) within the channel.
  • a device to sense the charge movement within the channel preferably an operational amplifier, a variety of analog and digital signal processing functions are possi ⁇ ble.
  • These channel coupled semiconductors are preferen ⁇ tially employed to perform the signal processing functions normally associated with conventional feedback functions that previously have been constructed with passive compo ⁇ nents, such as capacitors or resistors.
  • Applicant has therefore invented a channel coupled feedback technology that can be used to implement a variety of feedback and signal processing functions in commodity digital IC fabrication processes.
  • the need for precision passive components is avoided and the cost of implementing circuit functionality is reduced.
  • Circuits constructed according to the present invention will also serve to increase the integration density of most analog signal processing circuits, thereby reducing the silicon area necessary to implement these circuit functions. Further, since many commodity digital processes have well controlled transistor fabrication steps, the accuracy of many analog signal processing circuits can be improved.
  • Figure 1 is a block diagram of channel coupled feed ⁇ back circuits constructed according to the present inven ⁇ tion.
  • Figure 2 is a schematic of a conventional inverting, fixed-gain amplifier implemented with resistors.
  • Figure 3 is a schematic of a conventional inverting, fixed-gain amplifier implemented with switched capacitors.
  • Figure 4 is a cross-section of a conventional mono- lithic capacitor having a diffusion bottom electrode (20) and either a metal or polysilicon top electrode (19) .
  • Figure 5 is a cross-section of a conventional mono ⁇ lithic capacitor having a polysilicon bottom electrode (24) and either a metal or polysilicon top electrode (23) .
  • Figure 6 is a schematic of an inverting, fixed-gain amplifier implemented with the channel coupled feedback technology of the present invention.
  • Figure 7 is a clock diagram appropriate to implement the circuit of Figure 6.
  • Figure 8 is a top view of a layout of the circuit of Figure 6.
  • Figure 9 is a top view of a second layout of an inverting fixed gain amplifier constructed according to the present invention.
  • Figure 10 is a schematic of the circuit of Figure 6 with a conceptual physical cross section of the channel coupled semiconductors.
  • Figure 11 is an electron well diagram of the circuit of Figure 10 in the reset phase of the circuit operation.
  • Figure 12 is an electron well diagram of the circuit of Figure 10 in the post-reset phase of the circuit operation.
  • Figure 13 is an electron well diagram of the circuit of Figure 10 in the signal processing or computation phase of the circuit operation.
  • Figure 14 is a simplified functional equivalent circuit of the circuit shown in Figure 6.
  • Figure 15 is a schematic of the circuit of Figure 6 that has been constructed with "unit gates.”
  • Figure 16 is a schematic of an inverting, fixed-gain amplifier constructed according to the present invention having two FETs (122, 124) to decouple the gates of FETs
  • Figure 17 is a schematic of a non-inverting, fixed- gain amplifier constructed according to the present invention.
  • Figure 18 is a schematic of an offset compensated, 5 inverting, fixed-gain amplifier constructed according to the present invention.
  • Figure 19 is a schematic of an offset compensated, sample and hold circuit constructed according to the present invention.
  • Figure 20 is a schematic of an addition circuit constructed according to the present invention.
  • Figure 21 is a schematic of a subtraction circuit constructed according to the present invention.
  • Figure 22 is a schematic of an inverting, offset 15. compensated integrating amplifier constructed according to the present invention.
  • Figure 23 is a clocking scheme appropriate to imple ⁇ ment the circuits of Figures 22 and 24.
  • Figure 24 is a schematic of an inverting, offset 20 compensated differentiating amplifier constructed accord ⁇ ing to the present invention.
  • Figure 25 is a schematic of a fully differential amplifier constructed according to the present invention.
  • Figure 26 is a digital-to-analog converter construct- 25 ed according to the present invention.
  • Figure 27 is a logic diagram that is appropriate to generate the clocking scheme to implement the circuit of Figure 26.
  • Figure 28 is a block diagram of a successive approxi- 30 mation analog-to-digital converter constructed according to the present invention.
  • Figure 29 is a schematic of a digital to analog converter combined with a comparator that can implement an analog-to digital converter constructed according to 35 Figure 28.
  • Figure 30 is a switchable gain, inverting amplifier constructed according to the present invention that can be used in an automatic gain control system.
  • Figure 31 is an analog pixel matrix that is imple- mented with channel coupled semiconductors.
  • Figure 32 is a flow chart for the manufacture of an inverting, fixed-gain operational amplifier according to the present invention.
  • channel coupled feedback circuits that can be used to implement a variety of analog and digital signal processing functions.
  • the operation and effect of channel coupled feedback circuits can be understood by an analysis of the preferred embodiment, e.g., an inverting, fixed-gain amplifier constructed according to the present invention, as shown in Figure 6.
  • the circuit of Figure 6 can perform the same signal processing function as the conventional circuits shown in Figures 2 and 3,
  • a monolithic inverting, fixed-gain amplifier constructed with channel coupled semiconductors does not require monolithic resistive elements (8, 9) as in Figure 2 or well-matched monolithic capacitors (14, 16) fabricated with a special process having two capacitor electrode layers as in Figure 3.
  • the functional ⁇ ly equivalent circuit shown in Figure 6 can be constructed entirely in a conventional digital IC fabrication process designed to implement FETs only.
  • An inverting, fixed-gain amplifier can be construct- ed, for example, with as few as three channel coupled semiconductors ("CCSCs").
  • the channel coupled semiconductors are, in fact, channel coupled FETs, in which all three FETs share a common channel.
  • FET channel reset device
  • This device (30) essential ⁇ ly performs a switching function at one end of the chan ⁇ nel. When the switch (channel reset device) is closed, charge * is conducted either into or out of the channel, depending upon the surface voltage of the channel, in order to achieve potential equilibrium within the channel.
  • the switch may be opened, thereby fixing the amount of charge within the channel.
  • the channel reset device may be connected to the channel at any point along the channel.
  • charge reset device (30) utilized is not essential to practice the invention. Any device that permits switching control to a source of charge is appropriate for use with the present invention.
  • CCD CCD
  • T- gate T-gate
  • one terminal of FET (30) is electroni ⁇ cally connected to V cs (29) , which connection provides a supply of charge for the channel.
  • V cs represents a channel set voltage.
  • the channel reset device(s) is (are) con- nected to V cs , which preferably is a small positive voltage, but those skilled in the art will recognize that a variety of voltage sources can be used to supply charge to the channel, including electrical ground.
  • the reader will note that the IC designer has great latitude in deciding how many channel reset devices to provide for the channel, the type of device to be used to perform the switching function, the position along the channel to connect the channet reset device and the voltage source that is connected to the channel by the channel reset device(s).
  • applicant uses one FET (30) to perform the switching means and FET (30) is connected to a small positive voltage, V cs (29) , to supply charge to the channel.
  • the gate of the channel reset FET (30) is controlled by the phi clock signal.
  • An appropriate clocking scheme for the circuit of Figure 6 is shown in Figure 7.
  • the clocking scheme is comprised of two non-overlapping clocks (phi and ph2) .
  • phi is high
  • a reset voltage is applied to the gate of the channel reset FET (30) , which reset voltage in turn permits electrons to flow into or out of the channel through FET (30) .
  • phi is low
  • a post-reset voltage is applied to the gate of the channel reset FET (30) , thereby preventing the flow of electrons into or out of the channel.
  • a zero voltage signal is appropriate for the second phase of phi.
  • FET (30) serves to conduct electrons into or out of the channel during the reset phase and then acts as an electron barrier during the signal processing or computation phase, thereby maintaining a constant or fixed amount of charge in the channel during the signal process- ing or computation phase.
  • three channel coupled semiconductors, FETs (31) , (32) and (33) share the common channel and the substrate regions of the channel FETs are electronically connected or coupled so that charge can move freely between the substrate regions beneath the FETs.
  • the substrate underneath the gate of a FET is a lightly doped silicon crystal. Acting as a true semiconductor, when a zero voltage is applied to a gate on the surface of a lightly doped p-type silicon crystal, electrons are not conducted within the substrate. There ⁇ fore outside of the channel, no voltage is applied to the lightly doped substrate and thus, no electrons are con- ducted. Thus, lightly-doped p-type silicon with no voltage applied to it acts as an insulator.
  • the means (37-39) for electronical ⁇ ly connecting the substrates can be, for example, either a heavily doped ion diffusion implant, polysilicon, metal interconnect, a charge-coupled device (CCD) or an addi ⁇ tional FET between the two FETs to be connected, wherein the additional FET is biased to be conductive.
  • CCD charge-coupled device
  • the channel is comprised of (a) the semiconductor substrate regions underneath the gates of the channel coupled semiconductors that are inverted when the threshold voltage of the device is applied to the gate and (b) the means for electronically connecting the inverted substrate regions.
  • the channel is connected to the channel reset device (s), which channel reset device(s) also can connect the channel to a voltage (charge) source during the reset phase.
  • the layout of the semiconductor substrate regions and the connection means are not essential to practice the invention, nor is the order in which the semiconductor substrates are connected within the channel.
  • the applicant uses FETs to perform the feedback or signal processing functions.
  • a FET is defined as a device having a metal or polysilicon gate and heavy (ion) diffusion implants for the drain and source terminals.
  • the means (38, 39) for electronically connecting any two FETs within the channel, and for that matter the means (37) for connecting a FET within the channel to the channel reset device(s), is the heavy (ion) diffusion implant.
  • the two FETs to be electronically connected may share a heavy diffusion implant, wherein this implant serves, for example, as the drain of one FET and the source of the second FET. Therefore, the implant acts as means for conducting charge from the inverted substrate region of one FET to the inverted substrate region of the second FET.
  • the essential function of the channel coupled FET in the preferred embodiment of the present invention is the use of the gate of the FET and the lightly-doped substrate underneath the gate in a manner that is functionally equivalent to a capacitor.
  • the source and drain implants of the FETs are merely used as means for electronically connecting or coupling the substrates underneath the FETs.
  • a channel coupled semiconductor device is comprised of a gate separated from the lightly doped silicon crystal (substrate) by a silicon dioxide layer (insulator) .
  • the lightly doped silicon crystal substrate conducts only when a voltage is applied to the surface of the substrate.
  • a channel coupled semicon ⁇ ductor is a device having at least (a) a gate constructed of a conducting material, preferably polysilicon, (b) a lightly doped silicon crystal substrate and (c) an oxide (insulating) layer separating the gate and the substrate.
  • the oxide (insulating) layer is preferably silicon diox ⁇ ide, although those skilled in the art will recognize that other materials may be used for the insulating layer, such as Si 3 N 4 .
  • the substrates of the channel coupled semiconductors can be connected by, for example, diffusion (ion) implants, polysilicon, metal, a CCD, or some combination of these elements.
  • FIG. 16 shows a top view of a layout for Figure 6.
  • the solid line blocks represent the gates of the channel coupled semiconductors (41-43) and the channel reset device (40) .
  • block (41) represents the gate of FET (31) in Figure 6.
  • the dashed line structure (44) represents the channel, which is a combination of (a) lightly doped substrate and thin oxide underneath the gates and (b) heavy (ion) diffusion.
  • the solid lines represent standard electrical connections (wires) which may be metal, polysilicon or a heavy (ion) diffusion, for example.
  • Figure 9 shows a different layout for a fixed-gain amplifier that is equivalent in function to the circuit of Figure 6.
  • a channel reset device (52) has been connected to the substrate region of the channel coupled semiconductor whose gate (50) is connected to the output of the amplifier (56) .
  • gates (50, 51) have been switched in order from the location in Figure 8.
  • the arrangement and the location of the channel coupled semiconductors, the channel reset device(s) and the amplifier is within the discretion of the IC designer.
  • additional semiconductors, FETs or even passive components can be used to modify the func- tionality of the circuit without departing from the spirit of the invention.
  • the reader will note that the IC designer has great flexibility, for example, in deciding the number of channel coupled semiconductors to use in the channel, the material to be used to electronically connect the substrate regions, the arrangement of channel coupled semiconductors within the channel, and the order in which the semiconductor substrates are connected.
  • the gate of FET (31) can be connected to V ref in one phase and to V in (the input signal to be processed) in the second phase.
  • the gate of FET (32) is connected to the inverting (-) input of the operational amplifier (35) .
  • the gate of FET (33) is connected to the output terminal of the amplifier (35) .
  • the gates of FETs (32) and (33) are connected through switch (34) during the reset phase when phi is high.
  • the design of the operational amplifier (35) is not essential to practice the present invention.
  • Many conventional operational amplifier designs are appropriate for use with the present inven ⁇ tion.
  • the designs for a variety of operational amplifiers appropriate for use with the present invention can be found both in Gregorian and Temes and in Allen and Holberg.
  • the IC designer has great flexibility in choos ⁇ ing the design of the operational amplifier to maximize desired performance characteristics, such as power, slew rate, accuracy, settling rate, etc.
  • the amplifier is an inverting, fixed-gain high voltage amplifier capable of amplifying a video image input signal into a high voltage output signal, which output signal can be driven onto a liquid crystal display.
  • non-inverting (+) input of the amplifier (35) is connected to a reference voltage (V ref ) in the present example.
  • V ref reference voltage
  • the non-inverting input can also be connected to some other voltage that is between the power supply rails for the amplifier.
  • FIGS 10-13 the operation of the channel coupled semiconductors in an inverting, fixed-gain amplifier system is best understood by examining electron well diagrams of the channel during each phase of the signal processing operation.
  • the circuit of Figure 6 has been redrawn in Figure 10 to show the substrate regions of the channel coupled feedback circuits.
  • Figures 11, 12 and 13 show electron well diagrams for the reset, post-reset and computation phases, respectively. While not wishing to be bound by theory, applicant believes the operation and effect of channel coupled semiconductors can be best understood by analyzing how charge moves within the channel during the reset, post-reset and signal processing operation phases of the device. All four figures (10-13) should be viewed togeth ⁇ er.
  • the channel reset FET (70) is pulsed by the phi signal (shown in Figure 7) , so as to allow charge to flow into or out of the channel. Ph2 is low during this phase.
  • a reference voltage (V ref ) is applied to FET gate (71) .
  • the channel reset FET (70) is pulsed so as to provide a barrier to the movement of electrons into or out of the channel, preferably by applying a zero volt signal to FET gate (70), as is shown in Figure 7.
  • FET gate (70) both phi and ph2 are low. Therefore, the channel becomes electronically isolated from the charge source, V cs , with a fixed amount of charge within the channel and has a common channel gate voltage of V ref .
  • the input signal (V in ) is applied to the gate of FET (71) .
  • This operation is performed when phi is low and ph2 is high.
  • V in is a lower voltage than V ref , thereby causing electrons to be forced out of the substrate region immedi ⁇ ately underneath FET gate (71) .
  • the dashed section (91) under FET gate (71) indicates the amount of electrons forced from the substrate region by the application of V in .
  • the gain of the amplifier system of Figure 6 can be calculated by conceptually treating FETs (31) and (33) as capacitors.
  • the channel coupled semiconductors are acting electronically in a manner similar to MOS capacitors, in which the light (ion) diffusion underneath each gate acts as one electrode and the polysilicon gate acts as the second electrode.
  • a functionally simplified equivalent of the circuit of Figure 6 is shown in Figure 14.
  • the variable capacitor C4 (102) indicates the non-linear parasitic capacitance of the channel charge regions to the bulk used in the present invention. But since C4 is kept at a constant voltage during the signal processing or computation phase by the operation of the amplifier (105) , the parasitic capaci- tance of C4 (102) is not noticeable and thus non-linearity is not a concern.
  • the amount of charge (91) forced out from the substrate region (63) underneath FET gate (71) is equal to C-* . (V in -V ref ) , wherein Ci is the gate oxide capacitance of FET (71) . Since the amount of charge forced from underneath FET gate (71) i ⁇ equal to the amount of new charge transferred to the substrate (67) underneath FET gate (73), the following relationship results:
  • the intrinsic gate oxide capacitance of a FET is: C - e ox A/1 (4) , where e ox is the permittivity of silicon dioxide (approxi ⁇ mately 0.35 pF/cm) ; A is the area of the top electrode (the gate) and 1 is the thickness of the silicon dioxide layer.
  • e ox is the permittivity of silicon dioxide (approxi ⁇ mately 0.35 pF/cm)
  • A is the area of the top electrode (the gate)
  • 1 is the thickness of the silicon dioxide layer.
  • Gregorian and Temes, p. 69. This relationship can be employed to adjust the gate oxide capacitance of the FETs used in the present invention.
  • the FETs are physically located close to each other; thus, manufacturing variability between transistors should be low. Therefore, e ox and 1 can be expected to be approxi ⁇ mately equal for each FET in the channel.
  • the ratio of the areas of FET gates can be a well controlled parameter in most digital fabrication process ⁇ es, highly accurate fixed-gain amplifiers are possible using the present invention.
  • the reader will note that the area of the gate (72) connected to the inverting (-) input terminal (75) of the operational amplifier (78) is not included in the gain calculation. Since the charge underneath this gate is kept constant during the reset, post-reset and computation phases, this gate does not play a role in adjusting the gain of the system. Thus, the designer may want to make the area of gate (72) as small as possible to minimize the silicon wafer area necessary to implement each signal processing function. But for design purposes, the size of the gate connected to the amplifier input should be correlated to the amplitude of the input signal. Simply stated, for large amplitude input signals gate (72) should be large and conversely, for small amplitude input signals gate (72) can be made small.
  • gate (72) The necessity for adjusting the size of gate (72) is based " upon the amount of time the amplifier takes to settle after the input signal has been applied to gate (71) .
  • a negative input signal is initially applied to the channel coupled semiconductor(s) , the surface voltage of the channel will fall until the proper amount of charge has been transferred from the substrate region (63) underneath (input) gate (71) to the substrate region
  • the FETs of this example are similar to substrate-to-polysilicon MOS capacitors, the performance of the present channel coupled semiconductors does not suffer from the non-linear voltage coefficient of such capacitors. Since the operational amplifier holds the surface voltage of the channel at a constant level, the channel-to-substrate parasitic capacitance is not problem- atic. Thus, the "capacitance" of the channel coupled semiconductors used according to the present invention is first order linear.
  • the accuracy of the circuit shown in Figure 6 can be improved using various design refinements.
  • the gate perimeter ratio of FETs (31) and (33) is an important consideration because the FETs are communicating between the edges of the gates.
  • the edges of the gates are subject to random variation.
  • the shape of the gates should be square.
  • the relative error of channel coupled feedback circuits can also be minimized by ratioing the gates of the CCSCs.
  • a common technique for increasing the accuracy of tradi ⁇ tional monolithic capacitor ratios is to connect identi- cally sized smaller capacitors ("unit capacitors”) in parallel to construct a larger capacitor.
  • unit capacitors identically sized smaller gates (and the sub ⁇ strates underneath the gates) can be connected in parallel to construct larger “capacitors.”
  • perimeter ratioing and unit capacitors to improve the accuracy of analog processing circuits employ ⁇ ing capacitors, see Gregorian and Temes, pp. 90-93; McCreary, Matching Properties, and Voltage and Temperature Dependence of MOS Capacitors, IEEE J. Solid-State Cir ⁇ cuits. SC-16, 608-618 (1981) .
  • Channel coupled feedback circuits can be constructed with "unit gates" to minimize the effects of manufactur ⁇ ing variation. That is, identically sized gates can be connected to form the channel coupled semiconductors.
  • each of gates 110-113, 115 is an identically sized square gate. Gates (110-113) are connected to the input signal and the substrate regions underneath those gates are connected to form the channel. Those skilled in the art will recognize that a wide variety of circuit designs and layouts can be implemented using "unit gates” without departing from the spirit of the present invention.
  • two or more additional FETs can be added to the circuit of Figure 6.
  • applicant employs the use of transistors, although a device having just an overlapping gate and a semiconductor substrate (no addi- tional source or drain implants) is sufficient for this decoupling function.
  • FETs (122) and (124) have been added between channel FETs (121)/ (123) and (123)/(125).
  • the gates (127, 128) of FETs (122, 124) are held at a constant voltage throughout the reset, post- reset and computation phases. In this case, the constant voltage is the high rail of the power supply, V dd .
  • FETs (122) and (124) are n-FETs, a high voltage on the gate makes the n-FET conductive. Therefore, FETs (122) and (124) allow charge to pass underneath the gates, but remove the parasitic (sidewall) capacitance between FETs (121) , (123) and (125) .
  • channel coupled semiconducting One additional design consideration when using channel coupled semiconducting according to the present invention is that the input and output voltage ranges of channel coupled feedback devices are limited by the need to keep channel charge under all FETs in the channel. If the input signal is driven below the charge source voltage plus the characteristic transistor threshold, V cs +V ⁇ , then the channel underneath the input FET has no charge beneath it, thus changing the influence the input voltage has on the rest of the circuit drastically.
  • V cs is a low voltage (possibly electrical ground) and V ⁇ is typically less than a volt, the restrictions on input and output ranges are noticeable but not a substantial hindrance in most circuit designs.
  • inverting, fixed-gain amplifier described herein can be used to amplify any input signal regardless of whether the signal is characterized as an "analog" or a "digital" signal.
  • teachings provided with regard to the present preferred embodiment are applicable to the additional examples and are incorpo ⁇ rated into all of the additional examples.
  • Example 1 Non-Inverting, Fixed-Gain Amplifier
  • a non-inverting, fixed-gain amplifier can be constructed according to the present invention.
  • the clocking of switches (131) and (132) has been swapped.
  • the clocking scheme shown in Figure 7 also is appropriate to operate this non-inverting amplifier.
  • the use of FETs (135, 137) is optional and at the discretion of the designer.
  • a second (optional) channel reset device (139) has been included.
  • switch (149) is added and is controlled by the ph2 clock of Figure 7.
  • Switch (150) is also added and is controlled by the phi clock ' of Figure 7.
  • the drain of switch (150) is connected to the gate of FET (147) and the source of switch (150) is connected to V ref .
  • Example 3 Offset Compensated Sample and Hold
  • the inverting, fixed-gain amplifier of the preferred embodi ⁇ ment can also function as a sample and hold circuit.
  • the sample and hold periods of the circuit operation can be adjusted by changing the widths of the phi and ph2 clocks, while maintaining the non-overlapping phases.
  • the offset compensated, inverting, fixed-gain amplifier of Figure 18 can also perform the offset compensated, sample and hold function.
  • Figure 19 shows a simple offset compen ⁇ sated sample and hold circuit constructed with fewer components than the previous examples. This circuit also can be implemented using the non-overlapping clocks of Figure 7. When phi is high, gate (155) acquires voltage V in + V offset . When ph2 is high, the output voltage is therefore
  • V off ⁇ et V in .
  • a circuit for adding input signals can be constructed according the present invention and is shown in Figure 20.
  • n input signals may be added. Any linear combination of the input signals can be made by adjusting the area ("capacitance") of gates (174-176) .
  • the output voltage in this example will be equal to - [Al(VI - V ref ) + A2(V2 - V ref ) + . . . + An(VN - V ref )] /An+1.
  • a subtraction circuit can be constructed by inverting the clock phase of the input signal(s) (180, 181) to be subtracted. For simplicity, the subtraction of two input signals is shown in Figure 21. But as in Figure 20, the array of input signals can be increased by adding addi ⁇ tional gates and the designer is free to choose the number of inputs to be subtracted.
  • an inverting, integrating offset compensated amplifier constructed according to the present invention is shown.
  • the reader will note that the construction of the components for the inverting, inte ⁇ grating offset compensated amplifier is similar to an inverting, fixed-gain, offset compensated amplifier. The only differences are that FET (194) is connected to the ph2 clock, and the reset and offset compensation signals are controlled by ph3 and ph4, which act as global reset signals.
  • the clocking scheme shown in Figure 23 is appropriate to operate this integrating amplifier.
  • FET (194) should be constructed, and ph2 chosen, such that an electron barrier is created in the channel underneath FET (194) when V ref is applied to the gate of FET (193) .
  • FET (194) also serves to decouple FET (193) from FET (195) , because FET (194) is being driven by an external voltage source.
  • a non-inverting, offset compensated integrating amplifier can also be constructed according to the teach ⁇ ing in Example 1 by swapping the clock signals to switches (190) and (191) .
  • Example 7 An Inverting. Offset Compensated Differentiating Amplifier
  • inverting, offset compen ⁇ sated differentiating amplifier constructed according to the present invention is shown.
  • the construction of the inverting, offset compensated differentiating amplifier is similar to the inverting, fixed-gain amplifier shown in Figure 16.
  • additional gates are added.
  • V ouc can be connected to the gate of FET (209) when ph2 is high.
  • phi high and ph2 is low
  • the gate of FET (209) is connected to V ref .
  • the clocking scheme in Figure 23 is appropriate to implement this example.
  • FET (208) should be constructed so that an electron barrier is created in the channel underneath FET (208) when V out is applied to the gate of FET (207) .
  • FET (208) also serves to decouple FET (207) from FET (209) , because FET (208) is being driven by an external voltage source.
  • FET (208) is being driven by an external voltage source.
  • All transistors can be p-FETs and the computation charge can be holes instead of electrons.
  • the circuits thus described have only been single-sided. A fully differential fixed gain inverting amplifier is shown in Figure 25.
  • Example 8 Digital-to-Analog Converter A digital-to-analog converter (DAC) can be construct ⁇ ed according to the teachings of Example 4, the addition circuit. Referring to Figure 26, the reader will note the similarities to Figure 20.
  • a DAC may be structured to convert a digital word using a weighted array of capaci ⁇ tors. The output of the array of capacitors is sensed by an amplifier to generate the analog signal.
  • Figure 26 shows a 3-bit DAC constructed according to the present invention. As is standard for a weighted array of capacitors, the most significant bit of the digital word is applied to the largest gate (236) and the least significant bit is applied to the smallest gate
  • the logic of Figure 27 selects which transition direction (either up or down) the input gates of the weighted capacitor array are driven during the computation phase of the circuit.
  • the transition direction depends on the digital input word of the DAC.
  • This DAC can, of course, be expanded to convert larger digital words by adding progressively larger gates to the weighted array. Unit gates as shown in Figure 15 can also be used to implement this DAC. Further, offset compensation can be added to improve the accuracy of this circuit as was taught in Example 2. Those skilled in the art will recognize that this DAC is simply one illustra ⁇ tion of a DAC that can be implemented with channel coupled semiconductors and that numerous variations in the design and layout can be made to tailor the DAC to the intended performance specifications.
  • Example 9 Analog-to-Digital Converter
  • a successive approximation analog-to-digital convert ⁇ er can be constructed using components previously described in Examples 3 and 8.
  • Figure 28 shows a block diagram of a conventional successive approximation ADC. See e.g., Gregorian and Temes, pp. 420-425.
  • the DAC block (248) can be implemented with the DAC described in Example 8.
  • the Sample and Hold block (246) can be implemented with the sample and hold circuit described in Example 3.
  • the comparator (249) , successive approximation shift register (250) and switch logic (247) all can be imple- mented with conventional circuits.
  • FIG. 29 A logic circuit that is appropriate for generating the clock signals to switches (259-264) is shown in Figure 27.
  • the circuit of Figure 29 is a cotn- bined DAC and comparator that compares the digital word input with the input voltage, V in .
  • the comparator (266) is used to determine whether the surface voltage has been raised above V ref during the computation phase.
  • the channel surface voltage is not kept constant during the perform ⁇ ance of the signal processing operation.
  • Switchable Gain Amplifier The unit gate configuration of Figure 15 can be modified to provide a switchable gain amplifier.
  • switches (278-280) have been added that allow the number of gates in the array to be added during the computation phase.
  • the clock scheme of Figure 7 is appropriate to clock the phi and ph2 switches.
  • Switches (278-280) may be controlled by signals generated from a switch logic circuit. Once again, the designer has great latitude in determining the signals to be generated depending upon the application and the function and performance desired.
  • the switchable gain amplifier of Figure 30 can serve as the basis for an automatic gain control (AGC) system by adding a comparator function (298) to generate the switch logic signals (299) .
  • AGC automatic gain control
  • the comparator (298) and switch logic (299) functionality can be implemented with conven ⁇ tional circuits, thereby permitting a channel coupled feedback AGC system.
  • an analog pixel matrix for computing the linear transform of a matrix of analog values can also be constructed according to the present invention.
  • the channel FETs are set to a fixed charge and the sense amplifier senses charge transferred within the channel. Further details for constructing a linear computation circuit can be found in United States Patent Application, Serial No. 08/186,372.
  • Figure 32 shows a flow chart of a method that may be used to fabricate channel coupled feedback circuits. This method is merely one illustration and those skilled in the art will recognize that a variety of additions and modifi ⁇ cations may be made to this protocol.
  • channel coupled feedback technology that can be used to implement a variety of signal processing functions.
  • Those skilled in the art will recognize that the present channel coupled feedback technology can be used to implement other signal process ⁇ ing circuitry in which passive components, such as capaci ⁇ tors or resistors, are necessary using previous circuit designs, including signal processing circuits that have not been explicitly disclosed herein.
  • the present invention therefore provides the advanta ⁇ geous feature that monolithic circuit functionality, previously requiring passive components, can now be implemented solely with semiconductors, preferably FETs. Since these circuit functions only require FETs, conven ⁇ tional digital IC fabrication processes can be used that are less expensive than the special fabrication processes currently required to fabricate accurate monolithic capacitors and resistors. Because capacitors and resis- tors are not required, integration density of equivalent circuit functionality is improved, thereby reducing silicon requirements and further reducing the cost of implementing the desired circuit functionality. Also, since the surface of the channel is maintained at a constant voltage in most of the examples provided, the channel coupled semiconductors do not experience the first order non-linearity problems of substrate-to-polysilicon MOS capacitors.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

On décrit une technologie de retour à couplage par canaux pour mettre en ÷uvre plusieurs fonctions de traitement des signaux analogiques et numériques dans un procédé de fabrication de circuits intégrés numériques à polysilicium unique. On construit les transistors à effet de champ avec un canal commun, les régions de substrat desdits transistors à effet de champ étant électroniquement connnectées dans le canal. Ceci permet à une quantité fixe de charge de circuler librement dans le canal en réponse à l'application du signal à traiter. La détection de la charge transférée dans le canal lorsque le signal d'entrée est appliqué rend possible plusieurs fonctions de traitement du signal. Avec des transistors à effet de champ on construit entièrement des amplificateurs à gain fixe, des amplificateurs à décalage compensé, des intégrateurs, des différenciateurs, des convertisseurs analogique-numérique, des convertisseurs numérique-analogique, des amplificateurs à gain commutable, des systèmes de commande automatique de gain et des circuits de calcul de transformations linéaires, ce qui permet d'éliminer les composants passifs pour la plupart des fonctions de traitement du signal.
PCT/US1995/014933 1995-05-24 1995-05-24 Circuits de retour couples par canaux Ceased WO1996037950A1 (fr)

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PCT/US1995/014933 WO1996037950A1 (fr) 1995-05-24 1995-05-24 Circuits de retour couples par canaux
AU46385/96A AU4638596A (en) 1995-05-24 1995-05-24 Channel coupled feedback circuits

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PCT/US1995/014933 WO1996037950A1 (fr) 1995-05-24 1995-05-24 Circuits de retour couples par canaux

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6694128B1 (en) 1998-08-18 2004-02-17 Parkervision, Inc. Frequency synthesizer using universal frequency translation technology

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2200684A1 (fr) * 1972-09-25 1974-04-19 Rca Corp
EP0072741A2 (fr) * 1981-08-14 1983-02-23 American Microsystems, Incorporated Etage intégrateur à gain programmable comportant des moyens pour éliminer la tension résiduelle d'erreur
EP0169754A1 (fr) * 1984-06-26 1986-01-29 Thomson-Csf Comparateur analogique à transfert de charge, et dispositifs utilisant un tel comparateur
US4631739A (en) * 1984-11-28 1986-12-23 Xerox Corporation High dynamic range charge amplifier

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2200684A1 (fr) * 1972-09-25 1974-04-19 Rca Corp
EP0072741A2 (fr) * 1981-08-14 1983-02-23 American Microsystems, Incorporated Etage intégrateur à gain programmable comportant des moyens pour éliminer la tension résiduelle d'erreur
EP0169754A1 (fr) * 1984-06-26 1986-01-29 Thomson-Csf Comparateur analogique à transfert de charge, et dispositifs utilisant un tel comparateur
US4631739A (en) * 1984-11-28 1986-12-23 Xerox Corporation High dynamic range charge amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6694128B1 (en) 1998-08-18 2004-02-17 Parkervision, Inc. Frequency synthesizer using universal frequency translation technology

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