[go: up one dir, main page]

WO1996031038A1 - Technique de transmission de donnees, circuit emetteur/recepteur correspondant et unite de traitement de signaux - Google Patents

Technique de transmission de donnees, circuit emetteur/recepteur correspondant et unite de traitement de signaux Download PDF

Info

Publication number
WO1996031038A1
WO1996031038A1 PCT/JP1996/000746 JP9600746W WO9631038A1 WO 1996031038 A1 WO1996031038 A1 WO 1996031038A1 JP 9600746 W JP9600746 W JP 9600746W WO 9631038 A1 WO9631038 A1 WO 9631038A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
signal
transmission
data
reference clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP1996/000746
Other languages
English (en)
Japanese (ja)
Inventor
Tomonori Sekiguchi
Yoshinobu Nakagome
Takeshi Sakata
Takayuki Kawahara
Katsutaka Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of WO1996031038A1 publication Critical patent/WO1996031038A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L2007/047—Speed or phase control by synchronisation signals using special codes as synchronising signal using a sine signal or unmodulated carrier

Definitions

  • the present invention relates to a data transmission method, a transmission / reception circuit device and a signal processing device used for the same, and more specifically, to a central processing unit (CPU) and a main memory.
  • the present invention relates to a configuration of an input / output circuit unit and a configuration of a signal transmission unit of a circuit device in a signal processing device in which the circuit device is connected by a transmission line such as a bus.
  • LSI large-scale integrated circuit
  • DRAM Synchronous Random Access Memory
  • the signal processing device such as a work station or a personal computer using the LSI may not be able to operate at high speed. It is difficult to increase the speed of an LSI chip level to the speed of an LSI chip level with the following reasons.
  • a pulse signal based on a non-return, zero (NRZ) code is used for signal transmission between the LSI chips constituting the circuit device of the signal processing device as described above. If the wavelength of the harmonic component contained in this pulse signal becomes as short as the wiring on the board, the above wiring will behave as a distributed constant line, and the signal will be sent to the wiring end, branch, or LSI package.
  • Parasitic inductance ⁇ Remarkable reflections occur due to parasitic canon capacitance, and ringing and other waveform distortions occur in the pulse waveform. This waveform distortion causes difficulty in increasing the speed.
  • the LSI 172 has an internal circuit 178, which is the original functional circuit, and an output circuit 176, which converts the output of the internal circuit into a signal suitable for the transmission line 171. It has an input circuit 177 that converts the signal received from the line into a signal suitable for the processing of the internal circuit 179.
  • FIG. 18 shows the transmitting (output) circuit used.
  • the transmission circuit 180 has an output stage 181, driving circuits 182 and 183 each including a pMOS transistor and an nMOS transistor, and an output control circuit 1884.
  • IV 11 to IV 15 indicate an inverter circuit
  • NAND 2 indicates a NAND circuit
  • NOR indicates a NOR circuit.
  • the output control circuit 184 puts the output Out into a high impedance state regardless of the value of the input signal In when the signal D0e has a low level. When the signal Doe is at a high level, the same signal as the input signal In is output.
  • the size of the transistor of the internal circuit 178 in the preceding stage that generates the input signal In is small, and the size of the transistor in the output stage 181 is large. Inverter trains with progressively larger transistor sizes are used.
  • Figure 19 shows a simulated transmission waveform when using the transmission circuit shown in Fig. 18.
  • the power supply voltage is V dd power, '1.5 V, V ss power,' 0 V.
  • the transmission line has a characteristic impedance of 50 ⁇ and a length of 2 cm. At the end, the voltage V tt is 0.75 V and the resistance R tt is 50 ⁇ .
  • the inductance L of the knockout was 10 nH and the capacitance C was 5 pF.
  • the output resistance of the output circuit is about 22 ⁇ , and a plus / minus 0.4 V amplitude is obtained for a load of 25 ⁇ .
  • Waveforms I029 and ⁇ 030 at the transmitting end and the receiving end when a rectangular wave having a period of 1 Ons was transmitted from the output circuit are shown. This means that data "0, 1, 0, 1" is transferred at a period of 5 ns.
  • the reflection at the transmitting end and receiving end is large, and large ringing is occurring.
  • the margin for the voltage V tt at the minimum point of the waveform due to the ringing at the rise of the signal is 0.22 V, which is 55% of the amplitude of 0.4 V on one side. . If this minimum falls below the voltage V tt, the receiver will incorrectly determine that it has received two pulses. Therefore, if the margin is small, the reliability in transmitting a high-speed signal decreases.
  • a memory LSI is often used in the module configuration shown in FIG. 20 (a.
  • the memories are connected by a common memory bus 207.
  • the equivalent circuit of Fig. 20 (a) is shown in Fig. 20 (b).
  • One memory 2 0 One memory 2 0
  • a plurality of memory elements 201-1 to 210-7 are connected via one bus 207.
  • Memory elements 201-1 to 210-7, and 204 are LSI chips.
  • the end of the bus 207 is connected to the terminal power supply (voltage V tt) by the terminal resistor R tt.
  • the internal configuration of the memory elements 201 to 211 is the same, only the internal configuration of the memory elements 201 to 7 is shown for simplicity.
  • the case where the input and output terminals are independent is shown, but when the input and output terminals are common, the parasitic capacitance of the terminals becomes large, and the waveform disturbance becomes larger.
  • the received waveform of the simulation result when pulse transmission is performed using the circuit 180 in FIG. Figure 21 shows this.
  • a rectangular wave with a period of 10 ns is transmitted from LSI 208 and the transmission end of LSI208, LSI210-1 — 1, 20
  • the waveforms at the receiving end of 1 1 4 and 2 0 1-7 are
  • skew between the clock and data is also a problem in high-speed data transmission.
  • clock and data transmission in conventional data transmission are performed without terminating the data transmission line 221, and the voltage on the line is from V dd to V ss. Can swing up.
  • the clock and data supplied to each of S 1 2 2 3 — 1, 2 2 3 — 2 ⁇ 2 2 3 — 8 are transmitted in the same direction.
  • Skew due to the propagation delay on the transmission line because the data on the data transmission line 222 and the clock on the clock transmission line 222 are transmitted in opposite directions.
  • the relative ratio of the skew to the clock cycle increases.
  • 2 2 4 — 1... 2 2 4 — 8 is a transmission latch
  • 2 2 5 — 1... 2 2 5 — 8 is a reception latch
  • Reference numeral 6-8 denotes a CMOS inverter type transmission circuit
  • reference numeral 227-7-1 ... 22 7-8 denotes a CMOS inverter type reception circuit.
  • a technique using a ramba interface shown in 23 is known.
  • the Lannos interface is described in detail in Published Patent Publication No. 5-507734.
  • 2 3 3 — 1,... 2 3 3 — 8 is an LSI
  • 2 3 4 1 1... 2 3 4 — 8 is a transmission latch
  • 2 3 5 — 1... 2 3 5 — 8 is a reception latch
  • 2 3 6 — 1 ⁇ 2 3 5 — 8 are NMOS open drain type transmission circuits
  • 2 3 7 — 1 •• 2 3 7 — 8 are differential type reception circuits
  • 2 3 8 are Indicates the clock source.
  • the clock line 2332 is folded back and distributed, and one is used as a transmission clock, and the other is used as a reception clock.
  • data transmission is performed between the master 2 3 3-1 and a plurality of slaves 2 3 3-2... 2 3 3-8, and no data transmission is performed between the slaves.
  • slave 2 3 3 _ 8 transmits data in synchronization with the transmission clock
  • master 2 3 3-1 transmits data in synchronization with the transmission clock.
  • Data in synchronization with Upon receipt the data and clock will be transmitted to the left.
  • the data and clock are transmitted to the right. Therefore, the clock and data are always transmitted in the same direction, and the skew is reduced.
  • this solution has the problem of increasing the number of clock terminals.
  • this interface terminates the data transmission line and uses an active-low type small-amplitude interface using an open drain for the transmission circuit. Interface is used. For this reason, the high level of the signal becomes a constant value at the termination voltage V tt, but the low level depends on the device characteristics of the pull-down nMOS (2 3 3-1 2 3 3-8). You will be affected by fluctuations and changes. In order to suppress this effect, the driving power of the pull-down nMOS is controlled by feeding a low level voltage to the node, but the control circuit becomes complicated and the chip There is a problem that the area increases.
  • a main object of the present invention is to provide a data transmission method capable of performing high-speed and high-accuracy data transmission between circuit devices constituting a signal processing device, and a transmission / reception circuit device for implementing the method. That is. In particular, for signal processing devices such as work stations and personal computers. In data transmission between LSIs constituting a circuit device, a data transmission method that suppresses the ratio of harmonic components contained in a data transmission waveform, converts the transmission waveform into a signal that is less likely to be disturbed, and transmits the signal.
  • the purpose of the present invention is to provide a transmitting circuit and a receiving circuit device used for the above.
  • a second object of the present invention is to provide a circuit device having a transmission circuit and a reception circuit for performing data transmission with low noise by reducing a change in power supply current per unit time with low bias. It is.
  • a third object of the present invention is to provide a circuit device having a transmission circuit and a reception circuit for reducing a skew between a clock signal and a data signal, which is a problem in high-speed data transmission. And.
  • a fourth object of the present invention is to provide a circuit device having a transmission circuit and a reception circuit capable of transmitting with a large margin with respect to an output level in a small-amplitude interface.
  • a fifth object of the present invention is to provide a signal processing device capable of efficiently transmitting input / output signals of a circuit device for processing a plurality of data having different data transmission speeds through a single transmission line.
  • the equipment is to be provided.
  • a data transmission method is characterized in that a signal level of one or a plurality of digital data (hereinafter simply referred to as data) signals to be transmitted is fixed in a transmission unit
  • the data signal has the same cycle as the reference clock signal, and the amplitude is determined by the information of the data signal.
  • the reference clock signal and the modulation data signal are converted to a signal (hereinafter referred to as “modulation data”) representing a value smaller or larger than the amplitude of the signal, and transmitted to a receiving unit via a transmission line.
  • modulation data a signal representing a value smaller or larger than the amplitude of the signal
  • the receiving unit detects the difference between the amplitude of the modulation data received from the transmission line and the amplitude of the reference clock, and demodulates the signal into the original binary data signal.
  • the transmission circuit device is a reference clock signal generating means for generating a reference clock signal that is a sine wave having a constant period.
  • a data signal source for inputting the data signal to be transmitted, and the data signal to be transmitted having the same phase and period as the reference clock signal, and having the same amplitude as the information of the data signal to be transmitted.
  • a synchronous amplitude modulation circuit for converting the amplitude into a sine wave or a signal approximating a sine wave having a smaller or larger amplitude than the sine wave amplitude of the reference clock signal and the synchronous amplitude modulation circuit
  • a transmission circuit which has an output terminal for outputting the modulated data which is the output of the reference signal and the reference port to the transmission line.
  • the receiving circuit device provides the modulated data A receiving terminal that receives the reference clock and a reference clock; a comparator (detector) that compares the modulation data from the receiving terminal with the amplitude of the reference clock to determine the magnitude of the reference clock; And a demodulator that converts the output of the device into the original digital data signal.
  • a signal processing device is configured by connecting the above-mentioned plurality of receiving circuit devices and transmitting circuit devices via a transmission line.
  • the receiving circuit device and the transmitting circuit device include a case where the transmitting circuit and the receiving circuit are both provided.
  • the transmission circuit device and the reception circuit device are each configured by a single LSI together with an internal circuit that processes binary data.
  • the modulation circuit outputs a sine wave synchronized with the data to be transmitted and the level of the clock signal external to the SI as described above. According to this information, the signal is converted into a sine wave having a level larger or smaller than the level of the reference signal.
  • the sine wave is not limited to a strict sine wave, but is a waveform having a high similarity to the sine wave, for example, a waveform having a small harmonic component.
  • the transmission / reception circuit device is not particularly limited, but includes a circuit element configured by an LSI, for example, a memory, a micro processor, a control circuit, and the like.
  • the waveform of the transmitted data signal becomes a waveform approximating a sine wave with few harmonics, so that the transmission line branches from the transmission waveform.
  • the use of the data transmission method, transmission and reception circuit device according to the present invention enables highly reliable and high-speed data transmission, especially in high-speed data transmission.
  • FIGS. 1 (a) and 1 (b) are waveform diagrams for explaining the configuration and operation principle of a transmitting and receiving apparatus for implementing an embodiment of a data transmission method according to the present invention, respectively.
  • FIG. 2 is a circuit diagram of the transmission circuit device of FIG.
  • FIGS. 3 (a) and 3 (b) are plots each showing a configuration of a sinusoidal clock generating means used in the above embodiment.
  • FIG. 5 is a diagram and a waveform diagram for explaining the operation thereof.
  • FIG. 4 is a circuit diagram of the receiving circuit of FIG.
  • FIG. 5 is a timing chart showing the operation of one embodiment of the transmitting and receiving circuit device according to the present invention.
  • FIG. 6 is a block diagram showing a transmission circuit model for explaining the effect of the transmitting and receiving circuit device according to the present invention.
  • FIG. 7 is a diagram showing transmission / reception waveforms of one-to-one transmission showing simulation results using the circuit model of FIG.
  • FIG. 8 is a block diagram showing a transmission circuit model for explaining the effect of the transmitting and receiving circuit device according to the present invention.
  • FIG. 9 is a diagram showing transmission / reception waveforms of one-to-many transmission showing a simulation result based on the circuit model of FIG.
  • FIGS. 10 (a) and 10 (b) are a circuit diagram of another embodiment of the transmission circuit device according to the present invention and a truth table for explaining the same, respectively.
  • FIG. 11 is a block diagram showing a transmission system for explaining another embodiment of the data transmission method according to the present invention.
  • FIG. 12 is a block diagram showing a configuration of a computer which is an embodiment of the signal processing device according to the present invention.
  • FIG. 13 is a block diagram showing a configuration of a computer which is another embodiment of the signal processing device according to the present invention.
  • FIG. 14 is a diagram illustrating a waveform of a signal used in the signal processing device of FIG. 13 and a diagram illustrating a frequency domain of the signal.
  • FIG. 15 is a circuit diagram of a filter used in the signal processing device of FIG.
  • FIG. 16 is a waveform diagram for explaining the operation of the signal processing device of FIG.
  • FIG. 17 is a block diagram showing the configuration of a conventional pulse data transmission device.
  • FIG. 18 is a circuit diagram of a transmission circuit in a conventional pulse data transmission device.
  • FIG. 19 is a waveform diagram showing transmission and reception waveforms of a conventional pulse data transmission device.
  • FIGS. 20 (a) and (b) are a perspective view showing a main memory and a bus wiring model of a general signal processing device, respectively, and an equivalent circuit diagram thereof.
  • FIG. 21 is a waveform diagram showing transmission / reception waveforms of a conventional pulse data transmission device.
  • FIG. 22 is a block diagram showing the configuration of a conventional data transmission device.
  • FIG. 23 is a block diagram showing the configuration of another conventional data transmission device.
  • FIGS. 1 (a) and (b) show the data according to the present invention, respectively.
  • FIG. 2 is a waveform diagram for explaining the configuration and operation principle of an embodiment of a transmitting and receiving circuit device for implementing a data transmission method.
  • the transmission circuit device 1 composed of an LSI is transferred from the transmission circuit device 1 composed of a plurality of LSIs to the modulated data D 1 synchronously modulated to 2 -1... 2-8 and the reference clock.
  • C k 1 is transmitted via transmission lines 3-1 and 3-2, respectively. Since the plurality of receiving circuit devices 2-1-2-8 perform the same operation, the data transmission (one-to-one transmission) between the transmitting circuit device 1 and the receiving circuit device 2-1 will be described below. In the figure, only one transmission line 3-1 is shown, but multiple transmission lines may be used in parallel.
  • the transmission lines 3-1 and 3-2 have substantially the same electrical characteristics, wiring patterns, and loads.
  • the clock transmitting terminal 5 of the transmitting circuit device 1 and the clock receiving terminal 6 of the receiving circuit device 2-1 are connected to each other by a transmission line 3-2.
  • the data transmission terminal 7 of the transmission circuit device 1 and the data reception terminal 8 of the reception circuit device 2-1 are connected by the transmission line 3-1.
  • Both ends of the transmission lines 31 and 3-2 are connected to a fixed terminal potential V tt by a resistor R tt.
  • the transmission lines 3-1 and 3-2 are composed of micro strip planes with a multilayer substrate to control the characteristic impedance, and are configured with the same wiring pattern. . For this reason, transmission lines 3-1 and 3-2 are almost equally affected by noise and signal delay. Therefore, the relative magnitude relationship between the reference clock C kl and the modulation data D 1 can be transmitted without being affected.
  • the transmission circuit device 1 has a transmission circuit 9.
  • the transmission circuit 9 receives the sine-wave clock V ddq and the norm-wave clock C kt via the transmission lines 3-3 and 3-4, respectively, and receives an internal circuit (not shown).
  • the data D t1 to be transmitted is converted into modulated data D 1 by the synchronous amplitude modulation.
  • the clock C kt is a system clock added from an external clock source that is also provided outside the LSI chip of the transmission circuit device 1, and is an internal circuit in the transmission circuit device 1. In addition, it controls the operation timing of the internal circuit.
  • the clock Vddq has almost the same phase as the clock Ckt.
  • the clock Vddq is applied to the clock transmission terminal 5 via the fixed resistor 10 (resistance value Rc1). Therefore, the clock C k1 is obtained by dividing the voltage V ddq of the sine wave clock by the parallel connection resistance R tt, 2 of the termination resistance and the fixed resistance 11 (resistance value R c 1). It is a wave signal. This signal is used as the reference clock Ct1.
  • a clock V ddq is applied to the data transmission terminal 7 via a variable resistor 10 (resistance value R dl).
  • the signal D1 at the data transmission terminal 7 is a sine wave signal obtained by dividing the voltage of the clock Vddq by Rtt / 2 and the resistance 10 (resistance Rd1).
  • the resistance value R dl of the variable resistor 10 is varied by the control circuit 12 according to the data D t1 which is the output of the internal circuit.
  • the amplitude of the sine wave data D 1 can be changed in magnitude compared to the amplitude of the reference clock C kt.
  • the amplitude is modulated to be larger or smaller than the amplitude of the reference clock in accordance with the information of the data Dt1, that is, the two values of "1" and "0". Is defined as synchronous amplitude modulation.
  • FIG. 1B shows an example in which the data D t 1 has the information power ⁇ ′′ 0, 1, 1, 0, ′.
  • the modulation data D 1 transmitted from the transmission circuit 9 is shown.
  • the receiving circuit device 2-1 has the receiving circuit 13-2.
  • the receiving circuit 13-2 receives the modulated data D2 and the reference clock Ck2 subjected to the synchronous amplitude modulation from the terminals 8 and 6 via the transmission lines 3-1 and 3-2, respectively. These are compared by the comparators 14 and 11, and the comparison result is latched by the latch circuit 15-1 to demodulate the original data Dt1. If necessary, these are converted to NRZ signals.
  • FIG. 2 is a circuit diagram of the transmission circuit device 1 of FIG.
  • the transmission circuit device 1 is configured by a single LSI chip.
  • the LSI chip has an internal circuit 20 and a transmission circuit 9 to which NRZ code data D t1 output from the internal circuit 20 is input. Further, the DC power supplies V dd and V ss, the sine wave clock V ddq, and the clock C kt having a rectangular pulse waveform are supplied to the LSI chip 1.
  • a clock C kt and DC power supplies V dd and V ss are applied to the internal circuit 20. Since the clock C kt determines the timing of the circuit operation, it is sufficient if the timing can be determined using the sine-wave shaped clock C kt, When specifying timing at both the rising edge and the falling edge of the clock, it is more efficient to use a pulse-shaped clock. It becomes.
  • the data Dt1 processed by the internal circuit 20 is an NRZ code synchronized with the clock Ckt.
  • the transmitting circuit 9 has an analog switch in which an nMOS transistor (Mnl, Mn2, Mn3) and a pMOS transistor (Mp1, p2, M3) are connected in parallel. H 2 1 2 2 and 2 3 are provided.
  • the analog switch functions as the resistors 10 and 11 in FIG. 1, and modulates the data Dtl into the synchronous amplitude-modulated data D1.
  • analog switch 21 is based on reference clock C In order to obtain k 1, a clock V ddq is received at its source (drain) terminal, and a reference clock C k1 is output from its drain (source) terminal. It is composed of a transistor Mn1 and a pMOS transistor Mp1.
  • a voltage V dd is applied to the gate electrode of the nMOS transistor Mnl, and a fixed potential such as an installation potential is applied to the gate electrode of the pMOS transistor Mp1. Therefore, the transistors Mnl and p1 of the analog switch 21 function as a kind of resistance element having a predetermined on-resistance determined by the gate width, the gate length, and the like. And outputs a reference clock C k1 having an amplitude smaller than the clock V dd.
  • the EXNOR circuit 24 receives the clock Ckt of the pulse wave and the output signal Dt1 of the internal circuit 20, and outputs the exclusive output G2 of the exclusive OR of the signal clocks Ckt and Dt. Out.
  • Analog switches 22 and 23 are analog switches 21. Similarly, the nMOS transistor (Mn2, 3) and the pMOS transistor (Mp2, 3) are connected in parallel, and the source (drain) of each transistor is connected.
  • Clock V ddq is input to the electrodes, and synchronously modulated data D1 is output from the drain (source) electrode of each transistor.
  • the output of the circuit 1 24 is applied to the gate electrode of the transistor M n 2, and the output of the EXNOR circuit 24 is applied to the gate electrode of the transistor M p 2.
  • the inverted signal is applied from the inverter IV 1, a fixed potential voltage V dd is applied to the gate electrode of the transistor Mn 3, and the gate of the transistor M p 3 is applied.
  • the fixed electrode is applied with a fixed ground voltage V ss.
  • the MOS transistors ( ⁇ ⁇ 1 ⁇ ⁇ ⁇ 3, p 1 ⁇ ⁇ ⁇ 3) constituting the analog switches 21, 22 and 23 are connected to external LSIs. Since this is a part of the transmission circuit affected by manufacturing variations in the circuit, the gate length is made longer than that of the MOS transistor used in the internal circuit 20 to improve the characteristics. The effect of variation can be reduced.
  • FIGS. 3 (a) and 3 (b) are a block diagram showing a configuration of a clock generator for generating the clocks Ckt and Vddq, respectively, and a waveform diagram for explaining the operation thereof. is there.
  • the devices that generate the clocks C kt and V ddq are It is mounted on the same board 30 together with the LSI of the transmission circuit device 1.
  • the device for generating the clock C kt comprises a crystal oscillator 31, and the device for generating the clock V ddq adds the output of the crystal oscillator 31 to the low-pass filter 32.
  • the output of the mouth filter 32 is defined as a clock V ddq.
  • FIG. 4 is a circuit diagram of one embodiment of the receiving circuit device according to the present invention.
  • a single LSI chip a receiving circuit 13 having a differential amplifier 41 and latches 42-1, 42-2, and an output D of the receiving circuit 13 are provided. It has an internal circuit 4 3 that processes r 2.
  • the differential amplifier 41 detects the potential difference between the received reference clock C k 2 and the data signal D 2 subjected to the synchronous amplitude modulation, and detects the subsequent latch circuits 42 1 and 4 2 —
  • the differential amplifier 41 supplies an nMOS transistor Mn4 receiving a sine-wave reference clock Ck2 to its gate electrode and a data signal D2.
  • N MOS transistor M n5 received at the gate electrode and n MOS transistor! Load MOS transistors connected to Vln 4 and 5
  • the nMOS transistors Mn6 connected in common to the source electrodes of the nMOS transistors Mn4 and Mn5.
  • the differential amplifier 1 is connected between the power supply voltage V dd and the fixed potential V ss, and is connected to the reference clock C k from the drain electrode of the transistor Mn5. Outputs an output signal corresponding to the potential difference between D2 and data signal D2.
  • the latch circuits 42-1 and 42-2 are composed of an nMOS transistor (Mn7 power, Mnl 2) and a pMOS transistor (Mp7 ka to Mpl It consists of a CMOS transistor gate circuit composed of 2) and an inverter circuit (IV4 ... IV6).
  • the gate electrode of the transistor Mp7, Mn8, Mn9, Mnl0, Mp11, Mp12 receives the signal of the reference clock Ck2.
  • the signal is supplied via an amplification circuit 44 for amplification and shaping and a delay circuit 45.
  • the gate electrodes of transistors Mn7, p8, Mp9, p10, Mn11, and Mn12 have a signal obtained by inverting the output of delay circuit 45 by inverter IV7.
  • FIG. 5 is a waveform diagram for explaining the operation of the transmitting circuit and the receiving circuit of the first embodiment.
  • the reference numerals used in FIGS. 1, 2 and 4 are used for the description.
  • the sine wave clock Vddq is a sine wave of amplitude Vpa oscillating around a fixed voltage Vtt.
  • the sine wave clock Vddq is applied to the reference clock terminal 5 of the transmission circuit 9 through the analog switch 21.
  • the gates of the transistors Mnl and Mp1 are biased to the voltages Vddq and Vss, respectively, and the analog switch 22 is always on. Accordingly, reference clocks C kl and C k2 of sine waves appear at the clock transmission terminals 5 and 6, and the amplitude V ck of the reference clocks C kl and C k2 changes the amplitude V pa of the analog switch 21.
  • the voltage is divided by the on resistance R 1 and the parallel connection of the terminating resistance R tt.
  • Vck Vpa- (Rtt / 2) / (Rl + Rtt / 2)
  • the amplitude V on when the analog switch 22 is on is determined by the on-resistance R 2 of the analog switch 22 and the resistance R 23 of the parallel connection of R 3.
  • R 2 3 R 2R 3 / (R 2 + R 3)
  • the on-resistance of the analog switch is set to R3> R1> R23 in order to satisfy Von> Vck> Voff.
  • the amplitude of the sine wave of the data D1 can be made larger or smaller than the clock Ck1 by turning on / off the analog switch 22. .
  • the data Dt to be transmitted by the NRZ code and the modulation are determined by using the voltage difference between the clock Ck1 and the data D1.
  • the following control is performed to correspond the data D 1.
  • “1” represents V dd
  • “0” represents V ss.
  • An EXNOR circuit 24 is used to perform the above control.
  • the circuit 24 outputs "1" when the two inputs Ckt and Dt1 match, and outputs "0" when they differ.
  • the receiving circuit 2 compares and amplifies the reference clock Ck2 (same as clock Ckl) and data D2 (same as data D1) received by the differential amplifier 41.
  • An output signal Dm corresponding to the potential difference supplied to the transistors Mn4 and Mn5 is output.
  • This output signal D m is a rectangular NRZ code as shown in FIG.
  • the output signal D m is demodulated into an NRZ code according to the definition (assignment) of the correspondence between the synchronous amplitude modulation wave and the NRZ code.
  • the receiving clock Ckr for latching the demodulated signal amplifies the reference clock Ck2 by the amplifier circuit 44 and delays the reference clock Ck2 by the delay circuit 45. This is the signal that was sent.
  • the reference clock Ck2 is amplified and shaped by the amplifier circuit 44, and is formed into a rectangular pulse wave as shown by a clock Ckr in FIG.
  • the reception clock C kr that determines the timing of the latch circuit 42 is formed by using a rectangular signal obtained by shaping a sine wave into the reception circuit C kr. The timing of 2 can be determined accurately.
  • the receiving clock Ckr is 90 degrees (1 degree) with respect to the output signal Dm to form the latch timing of the subsequent latch circuit by the delay circuit 45. 4 cycles) The signals are out of phase. Using the receiving clock C kr, the output signal D m is latched by the latches 42-1 and 42-2 and output as a demodulated signal Dr 2.
  • the latch circuits 4 2-1 are connected to the inverter circuits IV 3, IV 4 and the The output signal D m is latched by a positive feedback path composed of the transistors M n8 and M p8.
  • the latch circuits 42 and 22 output the output signal D m by a positive feedback circuit composed of inverter circuits IV 5 and IV 6 and the transistors M n 11 and p 11. Latch.
  • each latch circuit is connected to the first-stage switch (Mn7, Mp7, n10, Mp10), the positive feedback switch (Mn8, Mp8, n 11, p 11) and switches (n 9, M p 9, M nl 2, p 12) of the output stage, and a latch circuit 4 2 — at each timing.
  • the switch 1 and the latch circuits 4 2-2 are configured so that the switches in each stage operate alternately.
  • the latch circuits 42-1 and 42-2 are configured to perform the latch operation and the output operation alternately, and perform high-speed operation.
  • the demodulated output signal Dr 2 is supplied to the internal circuit 43 of the LSI 40, and the internal circuit 43 performs predetermined processing.
  • the power supply voltage V dd and the ground potential V ss are applied to the internal circuit 43, and a pulse clock signal C kt (not shown) is supplied to the internal circuit 43 to determine the operation timing of the internal circuit 43.
  • MOS transistors (Mn4—Mn6, Mp4, Mp5) that make up the analog switch are affected by manufacturing variations between external LSIs.
  • MOS transistor used for internal circuit 40 because it is a part of the receiving circuit By making the gate length longer than that of a resistor, it is possible to make it less susceptible to characteristic variations.
  • Fig. 6 shows a model for one-to-one transmission by the data transmission device of this embodiment.
  • the clock transmitting terminal 62 of the transmitting circuit device 61 and the clock receiving terminal 64 of the receiving circuit device 62 are connected by a transmission line 66.
  • the data transmission terminal 63 of the transmission circuit device 61 and the data reception terminal 6 of the reception circuit device 62 are similar.
  • 4 is connected by a transmission line 67.
  • the transmission lines 66 and 67 are terminated at Vtt by the terminating resistor Rtt.
  • Block 9 is the transmitting circuit shown in FIG. 2, and block 13 has the same configuration as receiving circuit 13 shown in FIG.
  • FIG. 7 shows a simulation waveform of the signal transmission device model of FIG.
  • the simulation conditions are the same as in Fig. 19 of the conventional example.
  • a reference clock Ck9 and modulation data D9 are obtained, respectively.
  • the waveform is not disturbed, and the magnitude relation of the voltage between the clock Ck10 and the data D10 is determined. It is kept. From the waveform Dr10 of the received data Dr10, it can be seen that the transmitted data is correctly demodulated.
  • FIG. 8 shows a model when one-to-many transmission is performed by the data transmission device of another embodiment.
  • 81 indicates the LSI chip of the transmitting circuit device
  • 82-1, ..., 82-7 indicates the LSI chip of the receiving circuit device
  • the clock terminal and the data terminal are They are connected to independent transmission lines 86 and 87, respectively.
  • the ends of the transmission lines 86 and 87 are connected to a terminating power supply V tt by terminating resistors R tt.
  • R tt terminating resistors
  • FIG. 9 shows a simulated waveform of the signal based on the transmission device model of FIG.
  • the simulation conditions are the same as in FIG. 20 of the conventional example.
  • C kl 1, C k 12, C kl 5, C kl 8 and D ll, D 12, D 15 D 18 are circuit devices 8 1, 8 2 — 1, 8 2 -48, respectively.
  • the simulation clock waveform of reference clock and modulation data of 2-7 is shown.
  • the transmission waveform is not disturbed, and the magnitude relationship between the clock and the data voltage is maintained.
  • the demodulated data of the receiving circuit device is also demodulated like the transmitted data.
  • the following effects can be obtained.
  • the re-data transmission is performed using a sine wave or a waveform close to the sine wave
  • the received waveform has less disturbance. Since the sine wave remains the sine wave even if it is shifted in phase, even if multiple reflections occur at the branch of the transmission line, the parasitic element, or the like, the waveform is not disturbed.
  • the amplitude-modulated signal changes with time and contains some harmonics because it is not a perfect sine wave, but its proportion is small compared to a pulse wave.
  • the disturbance of the received waveform is caused by the difference between the reflection of the fundamental wave and the subharmonic wave or the difference in the phase shift
  • the synchronous amplitude modulated wave is compared with the pulse wave.
  • the disturbance of the waveform is reduced.
  • the data information "1" and "0" are represented by the difference between the reference clock and the modulation data
  • the transmission of the reference clock and the modulation data even if multiple reflections occur on the transmission line. If the line is set to the same conditions, the reference clock and the modulation data are reflected in the same manner, and the voltage difference is transmitted while being preserved, so that accurate data transmission can be achieved. Wear.
  • the current change per unit time is small. This is because there are few harmonics with respect to the pulse wave and the voltage changes slowly. Therefore, the current change for driving the external load is small, and the noise due to the current change generated by the inductance of the power supply terminal is reduced.
  • the sine wave V ddq is divided to generate the reference clock C k1 and the data D 1 so that the phases match.
  • the transmission circuit is composed of elements arranged in the same LSI chip, the characteristics of the elements are not affected by variations between the LSI elements, and the characteristics of the elements are not affected.
  • Data transmission can be performed without being performed. Since the reference clock Ck1 and the data D1 are generated in the transmission circuit 9 in the same LSI, the amplitude difference between the reference clock Ckl and the data D1 depends on the element characteristics in the same LSI. It is determined . Therefore, even if the device characteristics differ among the LSIs due to manufacturing variations and temperature changes during operation, the magnitude difference between the amplitude of the reference clock Ck1 and the amplitude of the data D1 is not significant. Gives no gag. On the other hand, in general, the variation of the device characteristics in the same LSI is very small as compared with the variation between the same LSIs. Data transmission that is difficult to receive is possible.
  • FIGS. 10 (a) and 10 (b) show a circuit diagram of another embodiment of the transmission circuit device according to the present invention and a truth table for explaining the operation of the circuit, respectively.
  • a transmission circuit for transmitting data using a synchronous amplitude modulation signal and a transmission circuit for transmitting data using an NRZ code are provided, and both circuits are switched and used as necessary.
  • fast data When transmission is required, the transmission line is terminated, a synchronous amplitude modulation signal is transmitted, and the disturbance of the transmission waveform is suppressed to improve reliability. If low-speed data transmission is sufficient, Can transmit the NRZ code without terminating the transmission line, and can reduce the power consumed by the terminating resistor.
  • the LSI chip 100 of the transmission circuit device includes, in addition to the internal circuit 101 receiving the power supply voltage V dd and the ground potential V ss and operating with the NRZ code, a transmission circuit 1 0 2, and the transmission circuit 102 has analog switches 21, 22, 23 and a switching control circuit 103 for switching between synchronous amplitude modulation and NRZ code.
  • the same components as those in the circuit of FIG. 2 such as the analog switch are denoted by the same reference numerals, and detailed description is omitted.
  • the drain) electrode is supplied with a sine wave clock V ddq and an analog switch 21, and a sine wave reference clock C k 21. From the analog switches 22 and 23, a modulated data signal subjected to synchronous amplitude modulation or an output signal D21 based on an NRZ code is selectively output.
  • the switching control circuit 103 receives a clock signal Ckt from the outside of the LSI 100 and data output from the internal circuit 101.
  • a logic gate EXNOR 2 receiving the data signal D t 21 1, an AND circuit AND 1 receiving the control signals A me and D oe 1, an OR circuit OR receiving the data signal D t 21 1 and the control signal A me AND a circuit AND AND circuit AND 2 that receives the output signals of EXNOR 1 and EXNOR 2, AND circuit AND 3 that receives the control signal D oe 1 and the output signal of the OR circuit, and receives the inverted signal of the control signal D oe 1 and the output of the OR circuit It is composed of NOR circuit NOR1.
  • the output signal G 21 of the AND circuit AND 1 is supplied to the gate electrode of the transistor Mn 21, and the inverted signal is supplied to the transistor Mp 21.
  • the output signal G22 of the AND circuit AND2 is supplied to the gate electrode of the transistor n22, and its inverted signal is supplied to the gate electrode of the transistor Mp22.
  • the output signal G 23 of the AND circuit AND 3 is supplied to the gate senile pole of the transistor Mn 23, and its inverted signal is supplied to the gate electrode of the transistor Mp 23.
  • the output signal G 24 of the NOR circuit NOR 1 is an nMOS transistor M n having its source / drain path connected between the data transmission terminal 104 and the ground potential V ss. Connected to 24 gate electrodes.
  • the switching control circuit 103 switches the operation mode using the control signal D 0 e 1 and the control signal A me signal. Switching control circuit based on the truth table shown in Fig. 10 (b) Will be described.
  • the signal A me is used to switch between the synchronous amplitude modulation signal and the NRZ code.
  • the signal A me is "1”
  • the data G 21 becomes “1” and the switch 21 is always turned on, and the clock C kt is added to the data G 22 because the AND circuit AND 2 is opened.
  • the output using the EXNOR of Dt21 and Dt21 is transmitted, and the output G24 is set to "0", and the transistor Mn24 is always off, so that the synchronous amplitude modulation circuit is activated.
  • the operation of the circuit is the same as the operation of the circuit of FIG.
  • An analog switch included in the output stage of the synchronous amplitude modulation circuit has an on-resistance set as in the first embodiment.
  • the control signal A me of this embodiment is an enable signal for controlling the activation and deactivation of the transmission circuit 102, and is used when the transmission circuit 102 is applied to a dynamic RAM. Can be formed based on the write enable signal and CAS signal, and also can be formed from a signal that enables output to the outside of the LSI 100. . Further, the control signal A me has a function as a mode signal for selecting whether to transmit the output signal D 21 as an amplitude-modulated signal or as an NRZ code.
  • the mode is determined in advance before mounting on a board or the like, and a constant potential is applied as the control signal Ame.
  • the transmission circuit 102 of the present embodiment has a function of making the transmission end impedance
  • the transmission circuit 102 is connected to the transmission line 110 as shown in FIG.
  • Each LSI (circuit device) 1 1 1... 1 1 8 has both a receiving circuit 1 19 and a transmitting circuit 1 20, and the clock and data transmitting and receiving terminals can be shared. Wear .
  • One of the LSIs connected to the transmission line 110 performs transmission, and the other LSI sets the signal D0e1 to "0" and sets the transmission circuit 120 to a high impedance state. To receive. Further, even in this case, it is possible to perform transmission using the NRZ code. Since the transmission circuit 120 is configured to have a high impedance in this way, the transmission terminal and the reception terminal can be shared, and the number of LSI bins can be reduced. High-density mounting is possible.
  • the MOS transistors Mn21-Mn23, Mp21-Mp23, and Mn24 that constitute the analog switch are related to external LSIs. Since the variation in device characteristics affects the performance, the gate length is made larger than that of the M0N transistor used in the internal circuit 101, so that the device is less affected by the device variation. A highly reliable output circuit can be constructed. ⁇ Example 3>
  • FIG. 12 is a block diagram showing the configuration of an embodiment of the signal processing device according to the present invention.
  • the transmission / reception circuit device of the present invention is applied to signal transmission of a bus in a computer which is a signal processing device.
  • the computer 120 has an SRAM (statistic) for temporarily storing data such as a micro processor (MPU) 121 and a processor 121 on a node.
  • DRAM Dynamic Random Access Memory
  • External storage devices such as disk 124 and display 125 are connected.
  • the components described above, that is, the circuit devices, are connected by a node 126, a memory node 127, and an I bus 128, respectively.
  • High-speed data transmission is performed between the processor 122 and the cache 122, but since the cache 122 is composed of a small number of SRAMs, the data transmission form is the processor. In many cases, one-to-one transmission is performed by directly connecting the satellites 122 and the SRAMs 122 via the nodes 126. Therefore, even at the time of high-speed data transmission, the disturbance of the transmission waveform is smaller than that of the bus, so that data transmission by the normal NRZ code can be used. However, high-speed data transmission between processor 122 and SRAM 122 is required. Therefore, the sweater transmission method according to the present invention is used.
  • the present invention When the synchronous amplitude modulation according to the present invention is used, a steady quiescent current flows through the terminating resistor R tt as shown in FIG. 1, so that the present invention can be applied from the viewpoint of consuming power. It is also possible to adopt signal transmission based on normal NRZ signals without using data transmission. In addition, when the NRZ code is used for high-speed data transmission and a terminating resistor is used, there is little difference from the synchronous amplitude modulation according to the present embodiment from the viewpoint of power consumption. Therefore, the data transmission method according to the present invention is performed.o
  • the memory bus 127 is used to configure the main memory with a large number of DRAMs. It becomes a bus transmission via.
  • the data transmission method of the present invention is used to improve the reliability of data transmission. .
  • the memory bus 127 is connected to the IZO bus 128 via a bus adapter 127, and is connected to the device (disk 122) on the bus 120. , Display 125, etc.) operate at a relatively low speed, so data transmission using normal NRZ code is used.
  • a part of the computer system shown in Fig. 12 can be composed of the mounting board (motherboard) shown in Fig. 20. In this case, the noise in FIG. 20 corresponds to the memory cell 127 shown in FIG.
  • FIG. 13 is a block diagram showing the configuration of another embodiment of the signal processing device according to the present invention.
  • data of a plurality of systems having different transmission speeds are frequency-multiplexed and transmitted to a bus in a computer which is a signal processing device, and the synchronous amplitude modulation of the present invention is applied to the transmission.
  • the computer includes a processor 131, a main memory controller 132, a disk device 1333, a display device 134, and a And a bus 135 for transmitting data between the circuit devices.
  • the input / output unit of each circuit device is provided with a transmission circuit and a reception circuit that perform synchronous amplitude modulation and demodulation according to the present invention.
  • the main controller 1311 which is the internal circuit of the processor 1311 inputs and outputs multiple (three in the figure) pulse data of different processing speeds.
  • the transmission / reception circuits 1311 and 12 received the data from the bus 1335 and the modulation section 1311 to 13, respectively, which synchronously amplitude-modulates and multiplexes the output data of the above three systems and outputs them to the path 135. It has demodulation units 13 1-4 that receive, separate, and convert three modulated data with different transmission speeds to digital data.
  • 1 3 1 — a, 1 3 1 _ b, 1 3 1 — c are all synchronous amplitude modulators, 1 3 1 — d, 1 3 1 — e, 1 3 1 — f are non-synchronous modulators
  • the filters, 1 3 1 — 6 are decoders.
  • the memory control unit 132 has an internal circuit, a main memory 132-1, and a transmission / reception circuit 132-2.
  • the transmission / reception circuit 1 3 2 — 2 includes a modulator section 13 2-a for synchronizing and amplitude-modulating a series of output data and outputting the result to the bus 13 5, and a modulation section for the driver 13 2 7. It has band-pass filters 13 2 -d and demodulators 13 2 -6 which receive the received modulation data and convert it to digital data.
  • the disk unit 13 3 has a disk controller 13 3-1 as an internal circuit and a transmitting and receiving circuit 13 3-2 having a transmitting and receiving circuit 13 3-2.
  • Modulators 13 3-b and 13 3-7 which perform synchronous amplitude modulation and output to bus 13 5, respectively, receive the received modulated data, and convert it to digital data.
  • Bandwidth filter 1 3 3-e and decoder 1 3 3-6 are provided.
  • the display device 134 has a transmission / reception circuit 134-4 as an input / output circuit.
  • the transmitter / receiver circuits 1 3 4-2 are modulator sections 1 3 4-b and 1 3 4-7, which modulate a series of output data with synchronous amplitude and output them to the bus 13 5. And a band-pass filter 134-f for receiving the received modulated data and converting the data into data, and a demodulator for a decoder 134-16.
  • Transmission lines 135 are parallel lines, each having a reference clock transmission line and a data transmission line. Although not shown, a reference clock generation circuit is provided in each of the circuit devices S 13 1,.
  • Fig. 14 (a) shows the sine wave of the reference clock used for data transmission at three transmission speeds of the signal processing device of Fig. 13.
  • the order in which the operation speed of each circuit device is slow is the order of the disk device (FD) 133, the display control device (DCR) 134, the main memory (MM) 132, and the reference clock.
  • the frequency of the shock is assigned.
  • Figure (b) shows the frequency range assigned above.
  • a disk device (FD) 133 may have about 20 MHz to 30 MHz
  • a display controller (DCR) 134 may have about 50 MHz to 100 MHz.
  • Approximately 150 Hz to 300 Hz is divided by the memory (MM) 13 32.
  • FIG. 15 is a circuit diagram showing the configuration of the above bandpass filter.
  • the non-linear filter is configured by combining a low-nos filter 150 L and a high-no filter 150 H.
  • the mouth filter 150 L and the noise filter 150 H are respectively composed of two capacitors (C, C 1, C 2) 15 1 a to 15 1 c and 2 It is composed of two resistance elements (R, Rl, R2) 152a to 152c and an op-amp (OP) 1553a to 1553b.
  • the operational amplifier 1 is connected from the input terminal 154 b via two equal capacitors 15 1 c connected in series. A signal is input to 53b, and a part is negatively fed back from the output terminal 1555b to the input of the op-amp 1553b. It is also connected to the middle of two capacitors 15 1 c via a resistor 15 2 b.
  • the cut-off frequency f 0 of the noise filter 150 H is 2 ⁇ C ⁇ -C 2 R
  • FIG. 16 is a timing chart showing an operation example of the CPU transmitting circuit in FIG. 13.
  • the modulator 1 3 1 — a, b, and c have NRZ code data S 1, S 2, and ⁇ ⁇ in order of frequency.
  • the signal of S3 is subjected to synchronous amplitude modulation using the sine waves of frequencies f1, f2, and f3 in Fig. 14, respectively.
  • Modulation data f ml, f m2 and f m 3 are obtained. These modulation data f ml, f m2, and f m3 are frequency-multiplexed by a multiplexing circuit 135 and transmitted as a signal to a bus 135. Conversely, circuit device 1 3 2
  • the circuit 1 3 1 — 3 demodulation unit 1 3 1 — 4 band pass filter 1 3 1 — d, f, and c separate these components and use the NRZ code according to the decoda 1 3 1 — 6.
  • the signal processing device (computer) includes a multiplexing device, and a plurality of circuit devices and CPUs having different operation speeds. Since signals are multiplexed and transferred between devices, a signal of a device with a low operating speed and a signal of a device with a high operating speed can exist on the same bus at the same time. Therefore, a plurality of devices having different operation speeds can use the same bus without the bus being occupied by a device having a low operation speed and the operation of another device being prevented. Yes The system can be sped up.
  • the multiplexing circuit can be realized by a wire-OR circuit, and the frequency separation is configured by a simple filter as shown in Fig. 15. Therefore, it can be easily formed on LSI.
  • the reference clock As the reference clock, a sine wave or a pulse waveform other than a waveform approximating it can be used. In this case, although some problems remain in the high-frequency distortion, the reference clock Ck1 and the modulation data D1 are obtained from the external clock Vddq, so that the reference clock Ck1 and the modulation data Dk1 are obtained. It is easier to synchronize D 1. Furthermore, since the external clock V ddq force, the reference clock C k1, and the modulation data D 1 are formed by using circuit elements arranged in the same LSI, the characteristics of the LSI are reduced. It is less susceptible to variations and allows accurate data transmission without being affected by variations in the characteristics of circuit elements.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

Cette invention a pour objet la mise en ÷uvre de transmission de données à grande vitesse par réduction de la distorsion du signal survenant lors d'une transmission de signaux de données numériques binaires sur une ligne de transmission. On transmet un signal sinusoïdal d'horloge de référence (Ckl) en l'associant à un signal de données (Dl) modulé en amplitude de manière synchrone. Ces signaux modulés sont démodulés après réception, selon le signal d'horloge reçu afin d'obtenir les données de base (Dr2). Dans le cadre de la modulation en amplitude synchrone, on module une onde sinusoïdale (Vddq), présentant les mêmes phase et période que celles du signal d'horloge de référence (Ckl), afin d'obtenir une amplitude supérieure ou inférieure à celle du signal (Ckl), en fonction des renseignements (1, 0) fournis par les données numériques. Il est possible d'utiliser ce procédé de transmission de données entre le microprocesseur et l'unité de stockage d'un ordinateur.
PCT/JP1996/000746 1995-03-24 1996-03-22 Technique de transmission de donnees, circuit emetteur/recepteur correspondant et unite de traitement de signaux Ceased WO1996031038A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP7/65442 1995-03-24
JP6544295 1995-03-24
JP7/99201 1995-04-25
JP9920195 1995-04-25

Publications (1)

Publication Number Publication Date
WO1996031038A1 true WO1996031038A1 (fr) 1996-10-03

Family

ID=26406585

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1996/000746 Ceased WO1996031038A1 (fr) 1995-03-24 1996-03-22 Technique de transmission de donnees, circuit emetteur/recepteur correspondant et unite de traitement de signaux

Country Status (1)

Country Link
WO (1) WO1996031038A1 (fr)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19707668A1 (de) * 1997-02-26 1998-08-27 Alsthom Cge Alcatel Verfahren zum Prüfen von Taktpfaden und Netzelement zur Durchführung des Verfahrens
US6081550A (en) * 1997-02-26 2000-06-27 Alcatel Method of testing clock paths and network elements for carrying out the method
WO2003013091A1 (fr) * 2001-07-27 2003-02-13 The Pulsar Network, Inc. Dispositif permettant d'extraire un signal d'horloge et un signal de donnees numeriques d'un signal porteur a modulation d'amplitude dans un recepteur, le debit de symboles coincidant avec la frequence porteuse ou representant la moitie de celle-ci
US6965262B2 (en) 1999-10-19 2005-11-15 Rambus Inc. Method and apparatus for receiving high speed signals with low latency
US7093145B2 (en) 1999-10-19 2006-08-15 Rambus Inc. Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals
US7161513B2 (en) 1999-10-19 2007-01-09 Rambus Inc. Apparatus and method for improving resolution of a current mode driver
US7269212B1 (en) 2000-09-05 2007-09-11 Rambus Inc. Low-latency equalization in multi-level, multi-line communication systems
US7292629B2 (en) 2002-07-12 2007-11-06 Rambus Inc. Selectable-tap equalizer
US7362800B1 (en) 2002-07-12 2008-04-22 Rambus Inc. Auto-configured equalizer
US8861667B1 (en) 2002-07-12 2014-10-14 Rambus Inc. Clock data recovery circuit with equalizer clock calibration
JP2020036130A (ja) * 2018-08-28 2020-03-05 帝人株式会社 通信システム

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61245658A (ja) * 1985-04-24 1986-10-31 Hitachi Ltd デ−タ・クロツク併用伝送方式
JPS6290045A (ja) * 1985-10-16 1987-04-24 Kokusai Denshin Denwa Co Ltd <Kdd> Ｆｄｍａ通信方式における周波数割当方式
JPS62180643A (ja) * 1986-02-05 1987-08-07 Hitachi Ltd パルス伝送方式
JPH0337747A (ja) * 1989-07-05 1991-02-19 Hitachi Ltd 記憶装置制御装置、ディスクキャッシュ方式およびディスクキャッシュシステム
JPH04160840A (ja) * 1990-10-24 1992-06-04 Terumo Corp データ通信装置
JPH0514279A (ja) * 1991-07-08 1993-01-22 Nippon Telegr & Teleph Corp <Ntt> 光配線方式

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61245658A (ja) * 1985-04-24 1986-10-31 Hitachi Ltd デ−タ・クロツク併用伝送方式
JPS6290045A (ja) * 1985-10-16 1987-04-24 Kokusai Denshin Denwa Co Ltd <Kdd> Ｆｄｍａ通信方式における周波数割当方式
JPS62180643A (ja) * 1986-02-05 1987-08-07 Hitachi Ltd パルス伝送方式
JPH0337747A (ja) * 1989-07-05 1991-02-19 Hitachi Ltd 記憶装置制御装置、ディスクキャッシュ方式およびディスクキャッシュシステム
JPH04160840A (ja) * 1990-10-24 1992-06-04 Terumo Corp データ通信装置
JPH0514279A (ja) * 1991-07-08 1993-01-22 Nippon Telegr & Teleph Corp <Ntt> 光配線方式

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19707668A1 (de) * 1997-02-26 1998-08-27 Alsthom Cge Alcatel Verfahren zum Prüfen von Taktpfaden und Netzelement zur Durchführung des Verfahrens
US6081550A (en) * 1997-02-26 2000-06-27 Alcatel Method of testing clock paths and network elements for carrying out the method
US8634452B2 (en) 1999-10-19 2014-01-21 Rambus Inc. Multiphase receiver with equalization circuitry
US7626442B2 (en) 1999-10-19 2009-12-01 Rambus Inc. Low latency multi-level communication interface
US6965262B2 (en) 1999-10-19 2005-11-15 Rambus Inc. Method and apparatus for receiving high speed signals with low latency
US7093145B2 (en) 1999-10-19 2006-08-15 Rambus Inc. Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals
US7124221B1 (en) 1999-10-19 2006-10-17 Rambus Inc. Low latency multi-level communication interface
US7126408B2 (en) 1999-10-19 2006-10-24 Rambus Inc. Method and apparatus for receiving high-speed signals with low latency
US7161513B2 (en) 1999-10-19 2007-01-09 Rambus Inc. Apparatus and method for improving resolution of a current mode driver
US9998305B2 (en) 1999-10-19 2018-06-12 Rambus Inc. Multi-PAM output driver with distortion compensation
US9544169B2 (en) 1999-10-19 2017-01-10 Rambus Inc. Multiphase receiver with equalization circuitry
US7456778B2 (en) 1999-10-19 2008-11-25 Rambus Inc. Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals
US7269212B1 (en) 2000-09-05 2007-09-11 Rambus Inc. Low-latency equalization in multi-level, multi-line communication systems
WO2003013091A1 (fr) * 2001-07-27 2003-02-13 The Pulsar Network, Inc. Dispositif permettant d'extraire un signal d'horloge et un signal de donnees numeriques d'un signal porteur a modulation d'amplitude dans un recepteur, le debit de symboles coincidant avec la frequence porteuse ou representant la moitie de celle-ci
US6771712B2 (en) 2001-07-27 2004-08-03 The Pulsar Network, Inc. System for extracting a clock signal and a digital data signal from a modulated carrier signal in a receiver
US7508871B2 (en) 2002-07-12 2009-03-24 Rambus Inc. Selectable-tap equalizer
US8861667B1 (en) 2002-07-12 2014-10-14 Rambus Inc. Clock data recovery circuit with equalizer clock calibration
US7362800B1 (en) 2002-07-12 2008-04-22 Rambus Inc. Auto-configured equalizer
US7292629B2 (en) 2002-07-12 2007-11-06 Rambus Inc. Selectable-tap equalizer
JP2020036130A (ja) * 2018-08-28 2020-03-05 帝人株式会社 通信システム
WO2020044583A1 (fr) * 2018-08-28 2020-03-05 帝人株式会社 Système de communication
CN112585893A (zh) * 2018-08-28 2021-03-30 帝人株式会社 通信系统

Similar Documents

Publication Publication Date Title
US9076551B2 (en) Multi-phase ground-referenced single-ended signaling
US20020171453A1 (en) Differential amplifier circuit capable of accurately amplifying even high-speeded signal of small amplitude
US6249164B1 (en) Delay circuit arrangement for use in a DAC/driver waveform generator with phase lock rise time control
US7352755B2 (en) Network interface card (NIC) with phase lock rise time control generating circuit
US20020152340A1 (en) Pseudo-differential parallel source synchronous bus
KR20110119744A (ko) 차동 드라이버를 위한 고속 공통 모드 피드백 제어
KR20210020584A (ko) 클럭 신호에 동기되는 신호 생성 회로 및 이를 이용하는 반도체 장치
TW302443B (fr)
WO1996031038A1 (fr) Technique de transmission de donnees, circuit emetteur/recepteur correspondant et unite de traitement de signaux
CN109300493B (zh) 纹波补偿器、数据驱动电路及半导体器件
TW546816B (en) Input/output interface and semiconductor integrated circuit having input/output interface
KR100423898B1 (ko) 크로스오버 성능이 개선된 유니버셜 시리얼 버스 저속트랜시버
US8242811B2 (en) High-bandwidth on-chip communication
US9449676B2 (en) Driver circuit
US9478264B2 (en) Integrated circuits and semiconductor systems including the same
WO2019191455A1 (fr) Système de récupération de données d&#39;horloge programmable (cdr)
CN100449935C (zh) 低电压差分信号环形压控振荡器
US5525914A (en) CMOS driver circuit
CN100536335C (zh) 恒定延迟零待机差分逻辑接收机及方法
TW201603487A (zh) 半導體裝置之接收器電路
US20220208253A1 (en) Systems and methods for common gate input buffers
JP5034797B2 (ja) シリアルインターフェース回路及び電子機器
US12101135B2 (en) Noise mitigation in single-ended links
US6154066A (en) Apparatus and method for interfacing integrated circuits having incompatible I/O signal levels
US20230298644A1 (en) Data sampling circuit and data transmitter circuit

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase