WO1996030833A1 - Electronic data storage devices and methods of manufacture and testing thereof - Google Patents

Abstract

A method for providing sub-word write capability in partial memory systems with means for retaining the integrity of the memory architecture between manufacturing stages comprising: testing integrated circuits to determine the location of row or column failures, determining which of the said integrated circuits have coincident row or column failures, and arranging an appropriate number of integrated circuits which do not contain coincident row or column failures in a group to form a set suitable for use in a memory system.

Description

Electronic data storage devices and methods of manufacture and testing thereof.

This invention relates to electronic data storage devices and, in particular, to a method for providing sub-word write capability in partial memory systems with means for retaining the integrity of the memory architecture between manufacturing stages. It finds application in memory systems where memory circuits are arranged in a matrix

of rows and columns and permits such memory systems to use partially working memory

circuits in which defective rows, columns or bits in the main memory circuit are replaced

by good rows, columns or bits in a supplementary memory device or devices (hereinafter

called the substitute store).

In the semiconductor industry, solid state memory devices are fabricated as dice on

wafers of silicon, with each die containing a memory array. These dice are tested and the

dice which can be made to work perfectly are packaged for use. Faulty dice may be graded

according to the degree of functionality they retain and some of these faulty dice may be

sold as partially working memory devices, known as 'partials'. The partials have a value

considerably lower than that of the prefect die, yet in most cases have only a small

proportion of defective memory locations. For this reason, a number of schemes have been

developed for returning partial memory systems to full functionality by replacing the

defective memory locations with good locations from a separate memory device (a

substitute store).

Most memory systems employ a word size (which is the number of bits that can be read

or written concurrently) that is much larger than the number of bits available from each

memory die. For example, a group of eight 4-bit wide memory dice may be configured as

a 32-bit wide memory system.

Previously, partial memory systems employing a discrete substitute store have been incapable of providing the facility of writing to a subword. for example a 16-bit write to a

32-bit wide memory system, or byte write capability in a 32-bit wide memory. The reason

for this inability to write to a subword is that the substitute store is normally 4 or more bits

wide, but does not have the capability of writing to only a single bit. All four bits must be

written to when one bit is written to.

The invention will be particularly described with reference to the accompanying

drawings, in which:

Figure 1 shows a 4-bit wide substitute store used in a 32-bit wide SIMM module

composed of eight 4-bit wide partials; and

Figure 2 shows a method for storing the sorted devices to ensure that set integrity is

retained.

Referring now to Figure 1 and considering, in particular, the situation arising from

device numbers #1, #3, #5 and #7 all having a defective row at row address 300H, a partial

memory control device would rectify these rows by routing these four data bits to the

substitute store, #S. In this situation, a 32-bit wide write to the main memory, that is to

devices #1 through to #8 can work perfectly, but if it is desired to write to only the first byte

(that is to devices #1 and #2) at this address 300H, the partial memory controller will have

to write to only one bit in the substitute store. Hitherto, this could be accommodated by

reading the four bits from #S, changing one of the bits and writing the four bits back to the

substitute store #S.

Simply writing one bit without first reading the other three bits would corrupt those

other three bits in the substitute store at this location. The result of this would be that when

the whole 32-bit word is read later, three bits would contain the wrong data. Unfortunately in most applications, there is insufficient time for a read, modify, write cycle to take place.

This problem of corrupting the substitute store in subword writes is inherent to partial

memory systems using a discrete substitute store that does not have the capability of

writing to individual bits.

According to the present invention there is provided a method of extending the usable

architecture of an integrated circuit memory system comprising testing integrated circuits

to determine the location of row and column failures, determining which of the said

integrated circuits have coincident row or column failures, wherein an appropriate number

of integrated circuits which do not contain coincident row or column failures are connected

in a group to form a set suitable for use in a memory system.

There is further provided an electronic data storage device comprising a plurality of

collocations of electronic data storage means arranged in a matrix of rows and columns,

addressing means adapted to select sets of said electronic data storage means for

simultaneous storage of a plurality of data bits therein, at least one of said plurality of

collocations having faulty data storage means at at least one location selectable by said

addressing means in which the addressing means is adapted to divert data addressed to said

location to a functionally operational location on a substitute collocation of electronic data

storage devices.

A method of manufacturing an electronic storage device in accordance with a particular

embodiment of the invention may be separated into a number of stages. In the first stage,

the partials, including the substitute store where this is a partial, are tested to obtain a list

of defective rows, colu ins or bits. The partials are then sorted, in a second stage, into sets

corresponding to a full-word wide set of devices, for example the nine partials for the main memory and the substitute store in Figure 1. Within the set there are subsets where the

number of subsets is equal to the full word width divided by the width of the smallest

writeable subword required plus one. That is:

Number of sets for one module = ((Full word width)/( width of smallest writeable subword) + 1).

The sets are initially empty, but either as each device is tested, or as each device is

selected from a set of tested devices, it is added to a set only if none of its defective rows,

columns or bits (depending on what unit the partial memory controller must identify), is

in any other set for that module.

Preferably, sets for a plurality of memory modules will be sorted simultaneously,

otherwise when all the sets for one module are almost full, many devices may have to be

rejected before one is found that meets the set acceptance criteria.

Preferably, also, the sorting is carried out on an automatic device handler attached to

the test system, but may be carried out by manual operators prompted by a suitable

computer-controlled prompting arrangement.

In the third stage of the assembly process, the sorted chips are placed into a physical

medium that retains the integrity of the set and ensures there is no mixing of devices either

between sets or between modules. For example, in a manufacturing process producing the

memory module described in Figure 1, the nine chips may be placed in order in a tube. The

assembly machine would be programmed to place all nine chips from that tube onto the

same memory module and in a specific order. It would not be necessary to label the tube

unless this was required for other reasons, such as identifying the module.

A manufacturer may place more than one set in a tube, so long as each set is handled correctly by the automatic equipment.

A similar assembly system can be instated using memory chips held in trays.

Where the memory chips are mounted on to a long or continuous tape for assembly

purposes, one or more memory chips are marked so they can be identified in the assembly

process, either electronically, magnetically or optically. In this instance the production

equipment will be programmed either to request an operator intervention in the case where

it requires the marked memory device, for example for the first position on the module, but

does not read a marking on the device presented on the tape, for example where the

equipment has dropped a device it attempted to pick up for placement. The operator would

progress the assembly equipment to the next marked device on the tape, and recycle the

module being assembled at the time of the intervention, along with its supposed set of

devices. Another alternative would be for the operator to pick up the part and place it

manually, or to present it to the equipment.

It will be appreciated that various modifications may be made to the above described

embodiments within the scope of the present invention. For example, in other

embodiments of this invention the last partial in the set is marked, or a predetermined

partial within each set is marked.

Although the invention has been described with reference to semiconductor memory

devices, it is also applicable to other forms of memory device in which memory storage

elements are addressed in the form of a matrix of rows and columns. In particular, it may

be applied to optical memory systems such as holographic memories.

Claims

Claims

1. A method of extending the usable architecture of an integrated circuit memory system

comprising testing integrated circuits to determine the location of row and column failures,

determining which of the said integrated circuits have coincident row or column failures.

characterised in that an appropriate number of integrated circuits which do not contain

coincident row or column failures are connected in a group to form a set suitable for use

in a memory system.

2. A method of retaining the integrity of a memory system architecture comprising

arranging integrated circuits into groups, affixing the integrated circuits in order onto a

packaging device, and marking a predetermined one of the integrated circuits in each of the

said groups to enable subsequent identification of each of the said groups.

3. A method of retaining the integrity of a memory system according to claim 2,

characterised in that the first or last integrated circuit in each group is marked.

4. A method of retaining the integrity of a memory system according to claim 2.

characterised in that the packaging device is a tape carrier.

5. An electronic data storage device comprising a plurality of collocations of electronic

data storage means arranged in a matrix of rows and columns, addressing means adapted

to select sets of said electronic data storage means for simultaneous storage of a plurality

of data bits therein, at least one of said plurality of collocations having faulty data storage

means at at least one location selectable by said addressing means characterised in that

said addressing means is adapted to divert data addressed to said location to a functionally

operational location on a substitute collocation of electronic data storage devices.