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WO1996023264A1 - Architecture permettant d'obtenir un interpolateur efficace - Google Patents

Architecture permettant d'obtenir un interpolateur efficace Download PDF

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Publication number
WO1996023264A1
WO1996023264A1 PCT/US1996/000747 US9600747W WO9623264A1 WO 1996023264 A1 WO1996023264 A1 WO 1996023264A1 US 9600747 W US9600747 W US 9600747W WO 9623264 A1 WO9623264 A1 WO 9623264A1
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WIPO (PCT)
Prior art keywords
input data
register
bit
data word
input
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Ceased
Application number
PCT/US1996/000747
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English (en)
Inventor
Paul Asher Kline
Dirk Anderson Bell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qorvo US Inc
Original Assignee
Watkins Johnson Co
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Filing date
Publication date
Application filed by Watkins Johnson Co filed Critical Watkins Johnson Co
Priority to EP96902734A priority Critical patent/EP0812439A4/fr
Publication of WO1996023264A1 publication Critical patent/WO1996023264A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/17—Function evaluation by approximation methods, e.g. inter- or extrapolation, smoothing, least mean square method

Definitions

  • This invention relates generally to the field of digital filters used for digital signal processing and communications.
  • it pertains to a digital architecture for performing high-speed interpolation of oversampled signals without relying upon multipliers, and by using filter coefficients that are powers of two.
  • a communication system In general, the purpose of a communication system is to transmit information-bearing message signals from a source to a user destination.
  • a communication system generally consists of three basis components: transmitter, channel, and receiver.
  • the transmitter has the function of processing the message signal into a form suitable for transmission over the channel. This processing of the message signal is referred to as modulation.
  • modulation In any communication system, the "channel bandwidth" defines the range of frequencies that the channel can handle for the transmission of signals with satisfactory fidelity. Channel bandwidth is important because, for a prescribed band of frequencies characterizing a message signal, the channel bandwidth determines the number of such message signals that can be multiplexed over the channel. In other words, for a prescribed number of independent message signals that have to share a common channel, the channel bandwidth determines the band of frequencies that may be allotted to the transmission of each message signal without discernible distortion.
  • Analog and digital transmission methods are used to transmit a message signal over acommunication channel.
  • the use of digital methods offers several operational advantages over analog methods, including but not limited to: increased immunity to channel noise and interference, flexible operation of the system, and a common format for the transmission of different kinds of message signals.
  • the task of creating wideband communication channels often involves producing a frequency-division multiplexed (FDM) wideband signal from input narrowband baseband signals.
  • the input signals may comprise many voice channels with bandwidths of only a few kilohertz, which prior to transmission are combined into a wideband signal spanning many megahertz.
  • FDM frequency-division multiplexed
  • the process of increasing the sample rate is typically performed by "interpolating" the sampled information in one or more stages. At each stage of interpolation, a higher sample rate is achieved by effectively inserting one or more zero samples between each incoming sample of the incident lower-rate data stream. Following this zero-padding operation, the data stream is filtered in order to suppress spurious signal energy created by the zero-padding. This filtering has often been performed using finite impulse response (FIR) digital filters.
  • FIR finite impulse response
  • the conventional hardware implementation of an FIR digital filter utilizes delay units, multipliers, and adders.
  • multipliers often occupy a relatively large circuit area, which tends to increase the cost of the filter.
  • cost is often not the only significant factor of interest, and operational speed may often be of even greater significance at the high sample rates required during the later stages of interpolation.
  • the maximum sample rate is often determined by the speed of the multipliers. Accordingly, to improve operational speed and reduce cost, it is desirable to eliminate multipliers from FIR filters.
  • the present invention comprises an efficient architecture for interpolating oversampled data, such as a stream of digitized voice data.
  • the efficient interpolator includes an input divider circuit, which receives an input data word over an input data line.
  • a register is provided for latching the divided input data word from the divider.
  • the divided input data word is added within a summer to the previously latched data word from the register, thereby forming a summed data word.
  • a multiplexer produces an interpolated output by multiplexing the summed data word with the input data word.
  • the register is latched at a first clock rate, and the multiplexer is clocked at twice the first clock rate.
  • the efficient interpolator architecture allows interpolation to be performed in the absence of multipliers, and simultaneously allows filtering to be achieved using coefficients equivalent to powers of two. This enables the interpolator to be realized inexpensively, and renders the interpolator particularly suitable for implementation within integrated circuits.
  • FIG. 1 shows a simplified block diagrammatic representation of the architecture of an interpolator using a conventional 3-tap filter.
  • FIG. 2 shows a block diagram of the architecture of an interpolator of the present invention.
  • FIG. 3 depicts a specific hardware realization of an interpolator of the present invention.
  • FIG. 4 is a block diagram of an interpolator network designed to interpolate by a factor of thirty two.
  • FIG. 5 is a block diagram of a specific hardware implementation of an interpolating filter which does not require an output multiplexer.
  • the low-pass filter employed to obtain y LP (k) is typically realized using two distinct filters.
  • a first filter, characterized by impulse response h e (k) is applied to the samples of the sequence x(k); and a second filter, having an impulse response h 0 (k), is also utilized to filter the samples of x(k).
  • h e (k) h(2k)
  • h 0 (k) h(2k+ l)
  • FIG. 1 a simplified block diagrammatic representation is provided of the architecture of a 3-tap interpolating filter 10 designed to effect the zero padding and low-pass filtering operations described above.
  • the interpolating filter 10 includes a switch 14, which alternately couples the even, i.e., y LP (2p), and odd, i.e., y LP (2p+ l), low-pass filtered samples to the filter output.
  • the input sample sequence is provided to an input shift register 18, which stores consecutive input samples x(p) and x(p-l).
  • Input register 18 provides the sample x(p) to first and second multipliers 20 and 22, and provides the sample x(p-l) to a third multiplier 24.
  • the "even” filter coefficients h e (0) and h e (l) are stored within a first filter register 28, and are respectively provided to the multipliers 20 and 24.
  • the "odd” filter coefficient, h o (0) is stored within a second filter register 32 connected to multiplier 22.
  • the scaled sample values x(p) and x(p-l) produced by multipliers 20 and 24 are summed within adder 36, which produces the "even" low-pass filtered output samples y LP (2p).
  • the "odd” low-pass filtered output samples, y L p(2p+ 1), are produced by multiplier 22.
  • the complete low-pass filtered output sequence is obtained by toggling the switch 14 between the outputs of adder 36 and multiplier 22.
  • FIG. 2 a block diagram is provided of the architecture of the interpolating filter 100 of the present invention.
  • the interpolating filter 100 is seen to not include any digital multipliers, thereby enabling cost-effective integrated circuit implementation.
  • the input sample sequence x(m) impressed upon input terminal 102 is received by a divide-by-two circuit 104.
  • the divided samples of the input sequence are sequentially latched, at the clock rate of the input sequence x(m), by a register 108.
  • Each consecutive pair of divided samples, i.e. , x(m)/2 and x(m-l)/2, are combined within adder 112.
  • the output of adder 112 forms the "even" terms of the interpolated output sequence applied to a first input terminal 114 of the multiplexing output switch 116.
  • FIG. 3 there is shown a specific hardware realization of an interpolating filter 200 of the present invention.
  • the filter 200 processes the 14-bit samples comprising the input sequence x(n).
  • the thirteen most significant bits (MSBs) of each 14-bit input sample are simultaneously clocked, at the input sample rate f s , into a 13-bit register 204.
  • the 13-bit register 204 will generally be comprised of a set of thirteen D-type flip-flops, each of which latches one of the thirteen MSBs of each input sample.
  • the thirteen MSBs of each pair of consecutive samples are added within 13-bit adder 208, and the 14-bit result provided to an output multiplexer 212.
  • the multiplexer 212 operates to produce the output sequence y LP (m) by multiplexing, at the output sample rate of twice f detox the sequence of 14-bit values from the adder 208 with the 14-bit input sequence x(n).
  • the "even" output sample component associated with a given input sample is output by the filter 200 before the corresponding "odd” sample component.
  • the filter 200 is seen to be capable of being realized very efficiently, in that it requires only a register comprised of 13 flip-flops, a 14-bit adder, and a multiplexer.
  • the filter 200 may be described as functioning as a 3-tap finite impulse response (FIR) half-band filter having coefficients of 1/2, 1, 1/2.
  • FIR finite impulse response
  • the filter network 300 is comprised of a set of five serially-connected interpolation-by-two filters of the present invention (see, e.g. , FIG. 3).
  • the filter network 300 may be included within, for example, a digital transmitter disposed to convert multiple low data rate, oversampled, narrowband input sequences into a high data rate, wideband output sequence. For example, in a specific embodiment input data having a baseband bandwidth of approximately 14 kHz is applied at a rate of 960 Ksps to the network 300.
  • each interpolation-by-two stage provides a low-pass filtering function characterized by a -3 dB frequency of approximately 14 kHz, passband ripple of less than approximately 0.25 dB, and image rejection on the order of 67dB.
  • the filter 400 processes the 14-bit samples comprising the input sequence x(n) of sample rate f s .
  • the bits of each 14-bit input sample are simultaneously clocked, at a rate of 2f s , into a 14-bit register 404.
  • the 14-bit register 404 will generally be comprised of a set of fourteen D-type flip-flops, each of which latches one of the bits of each input sample.
  • the fourteen bits of each pair of consecutive samples are added within 14-bit adder 408, and the 14 MSBs from the result of each addition comprise the output of the filter 400.
  • the output of the filter 400 may be represented as:
  • the filter 400 may be described as functioning as a 3-tap finite impulse response (FIR) half-band filter having coefficients of 1/2, 1, 1/2, which is disposed to operate upon a zero-padded sample sequence (i.e. , one "padding" zero per sample). While the present invention has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

L'invention concerne une architecture efficace pour un interpolateur (100) de traitement de données suréchantillonnées. L'interpolateur (100) comprend un circuit diviseur d'entrée (104) qui reçoit un mot de données par une ligne d'entrée de données. Un registre (108) verrouille le mot divisé de données reçu du diviseur (104). Le mot divisé de données est additionné dans un totaliseur (112) à un mot divisé verrouillé de données reçu du registre afin de former un mot totalisé de données. Un multiplexeur (116) produit une sortie interpolée en multiplexant le mot totalisé de données avec un mot de données d'entrée. Dans un mode préféré de réalisation, le registre (108) est verrouillé à une première cadence d'horloge et le multiplexeur (116) est rythmé à une cadence égale à deux fois la première cadence d'horloge. Cette architecture efficace de filtrage permet d'effectuer des interpolations sans multiplicateurs et en utilisant des coefficients de filtrage équivalents à la puissance deux. On peut ainsi réaliser un interpolateur (100) économique et on obtient un filtre qui convient particulièrement aux circuits intégrés.
PCT/US1996/000747 1995-01-26 1996-01-22 Architecture permettant d'obtenir un interpolateur efficace Ceased WO1996023264A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP96902734A EP0812439A4 (fr) 1995-01-26 1996-01-22 Architecture permettant d'obtenir un interpolateur efficace

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37845795A 1995-01-26 1995-01-26
US08/378,457 1995-01-26

Related Child Applications (2)

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US09/077,354 A-371-Of-International US6255096B1 (en) 1995-11-23 1996-11-22 Synthetic mammalian α-n-acetylglucosaminidase and genetic sequences encoding same
US09/836,613 Division US20030039643A1 (en) 1995-11-23 2001-04-17 Synthetic mammalian alpha-N-acetylglucosaminidase and genetic sequences encoding same

Publications (1)

Publication Number Publication Date
WO1996023264A1 true WO1996023264A1 (fr) 1996-08-01

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WO (1) WO1996023264A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2116668C1 (ru) * 1997-02-24 1998-07-27 Военная академия связи Сплайн-интерполятор
RU2120137C1 (ru) * 1997-01-23 1998-10-10 Военная академия связи Интерполятор
DE19741427A1 (de) * 1997-09-19 1999-04-15 Siemens Ag Linearer Interpolator zur Interpolation eines abgetasteten Signals und Interpolationsverfahren

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4101964A (en) * 1976-01-08 1978-07-18 The United States Of America As Represented By The Secretary Of The Army Digital filter for pulse code modulation signals
US5369606A (en) * 1992-09-14 1994-11-29 Harris Corporation Reduced state fir filter
US5390674A (en) * 1993-12-30 1995-02-21 Advanced Technology Laboratories, Inc. Ultrasonic imaging system with interpolated scan lines
US5473381A (en) * 1993-08-07 1995-12-05 Goldstar Co., Ltd. Apparatus for converting frame format of a television signal to a display format for a high definition television (HDTV) receiver

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4783698A (en) * 1987-04-13 1988-11-08 Technology Inc., 64 Interpolator for compressed video data
US5043932A (en) * 1989-10-30 1991-08-27 Advanced Micro Devices, Inc. Apparatus having modular interpolation architecture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4101964A (en) * 1976-01-08 1978-07-18 The United States Of America As Represented By The Secretary Of The Army Digital filter for pulse code modulation signals
US5369606A (en) * 1992-09-14 1994-11-29 Harris Corporation Reduced state fir filter
US5473381A (en) * 1993-08-07 1995-12-05 Goldstar Co., Ltd. Apparatus for converting frame format of a television signal to a display format for a high definition television (HDTV) receiver
US5390674A (en) * 1993-12-30 1995-02-21 Advanced Technology Laboratories, Inc. Ultrasonic imaging system with interpolated scan lines

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0812439A4 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2120137C1 (ru) * 1997-01-23 1998-10-10 Военная академия связи Интерполятор
RU2116668C1 (ru) * 1997-02-24 1998-07-27 Военная академия связи Сплайн-интерполятор
DE19741427A1 (de) * 1997-09-19 1999-04-15 Siemens Ag Linearer Interpolator zur Interpolation eines abgetasteten Signals und Interpolationsverfahren
DE19741427C2 (de) * 1997-09-19 1999-07-22 Siemens Ag Linearer Interpolator zur Interpolation eines abgetasteten Signals und lineares Interpolationsverfahren

Also Published As

Publication number Publication date
EP0812439A1 (fr) 1997-12-17
EP0812439A4 (fr) 1999-12-08

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