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WO1996017379A1 - Procede et systeme de production d'un dispositif a circuit integre permettant une tension elevee de seuil d'oxyde epais utilisant des elements d'espacement en oxyde - Google Patents

Procede et systeme de production d'un dispositif a circuit integre permettant une tension elevee de seuil d'oxyde epais utilisant des elements d'espacement en oxyde Download PDF

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Publication number
WO1996017379A1
WO1996017379A1 PCT/US1995/013138 US9513138W WO9617379A1 WO 1996017379 A1 WO1996017379 A1 WO 1996017379A1 US 9513138 W US9513138 W US 9513138W WO 9617379 A1 WO9617379 A1 WO 9617379A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
field
oxide layer
oxide
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1995/013138
Other languages
English (en)
Inventor
Raymond Holzworth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of WO1996017379A1 publication Critical patent/WO1996017379A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Definitions

  • the present invention is directed toward an improvement in an integrated circuit and more particularly to a device which provides for high field threshold voltage for programming.
  • the system should be simple to implement and cost effective.
  • the system should also be one that can be utilized effectively as the device sizes becomes smaller.
  • the present invention addresses such a need.
  • a method and system for providing high field threshold voltage integrated circuit device comprises depositing an oxide layer over a nitride layer of the integrated circuit. The oxide layer is then etched to the top of the nitride layer such that oxide portions are located on the side thereof.
  • a field implant region is provided in the well area of the integrated circuits. The field implant region is spaced from a source/drain region of the nitride layer by the oxide portions.
  • the field implant region is spaced away from the source/drain region of the device. In so doing, the breakdown voltage of the parasitic transistors associated therewith are significantly increased.
  • Figure 1 is a flow chart showing a conventional method for producing an integrated circuit.
  • Figure 2 is a diagram of the integrated circuit device produced in accordance with the system of Figure 1.
  • Figure 3 is a diagram of a portion of the integrated circuit device of Figure 1.
  • Figure 4 is a diagram showing the P* region and N * region of the integrated circuit device of Figure 1.
  • Figure 5 is a flow chart showing a method for producing an integrated circuit device in accordance with the present invention.
  • Figures 6A-6E are diagrams of the integrated circu device in accordance with the present invention at vario stages of its function.
  • the present invention relates to an improvement in integrated circuit device with a high field threshold voltag
  • the following description is presented to enable one ordinary skill in the art to make and use the invention provided in the context of a particular application and i requirements.
  • Various modifications to the preferr embodiments will be readily apparent to those skilled in t art, and the generic principles defined here may be applied other embodiments.
  • the present invention is n intended to be limited to the embodiments shown, but is to accorded the widest scope consistent with the principles a novel features disclosed herein.
  • Figure 1 is a flow chart for producing an integrat circuit in accordance with the prior art.
  • Figure 2 is diagram of an integrated circuit 10 produced in accordan with the flow chart of Figure 1. Accordingly, referring Figure 2, the nitride portion 12 of IC 10 is masked and etch via steps 30 and 32 of Figure 1. Thereafter a photoresi material associated with the process is stripped, via step 3 The field implant 16 is provided via step 36. Finally, t field oxide portion 18 is provided via step 38.
  • EPROMS, EEPROMS and EPALS oftentimes require a high voltage (between 12 and 18 volts) to operate. However parasitic transistors, due to proximity, are created between N * source drain regions 14 to the P* field implant region as illustrated in Figure 3.
  • the breakdown voltage of these parasitic transistors at device sizes of .0001 cm or smaller decreases.
  • the breakdown voltage can be as low as 10 volts. If the breakdown voltage of these parasitic transistors is that low then the IC cannot be programmed because the breakdown voltage is less than the programming voltage.
  • FIG 4 what is shown is a diagram showing the P * field, the field implant and N * of the source/drain field of the device.
  • the breakdown voltage is dependent upon the amount of dopant in each field. As has been above-mentioned, the breakdown voltage utilizing conventional methods is decreased as the device becomes smaller because of the P * field of the field oxide region an N* field of the source/drain region of the device are close together.
  • the present invention provides a system and metho pulling the field away from the source drain region of th device with oxide spacers.
  • Figure 5 shows a flow chart of a method fo producing a integrated circuit with a high field threshol voltage in accordance with the present invention.
  • Figure 6A 6E are diagrams showing the formation of an integrated circui in accordance with the present invention that correspond t the flow chart of Figure 5.
  • the nitride layer 10 of IC 100 is masked and etched via steps 202 and 204 of Figur 5. Thereafter a photoresist material 104 associated with th process is stripped, via step 206.
  • An oxide layer 102 (between 1000 and 4000 A) is the deposited over the nitride layer 101 via step 208 ( Figure 6A) .
  • the oxide layer 102 is then etched back to form oxide spacer 106 on the edge of the nitride layer 101 via step 210 (Figur 6B) .
  • photoresist layer 104 protect the unimplanted area.
  • dopant is implanted via step 21 to form the field implant region 108 ( Figure 6C) .
  • this field implant region 108 is spaced away from th source/drain region 114 of the device by the spacers 106.
  • the oxide spacers 106 can be removed by utilizing a solvent such as a hydroxide fluoride (HF) via step 218, right after a photo resist strip 104 via step 216 ( Figure 6D) . Thereafter, a field oxide region 110 ( Figure 6E) is provided adjacent to the source/drain region 114 via step 220. As an alternative, the oxide spacers 106 can be consumed by a growing field oxide region 110 over the field implant region 108.
  • a solvent such as a hydroxide fluoride (HF) via step 218, right after a photo resist strip 104 via step 216 ( Figure 6D) .
  • a field oxide region 110 ( Figure 6E) is provided adjacent to the source/drain region 114 via step 220.
  • the oxide spacers 106 can be consumed by a growing field oxide region 110 over the field implant region 108.
  • a spacer is provided that increases the breakdown voltage characteristic of the parasitic transistors formed in the integrated circuit device. Accordingly, through the use of the present invention, integrated circuits become smaller, higher breakdown voltages on such devices can be maintained.
  • This present invention has been described in terms of EPALs, EPROM and EEPROM's.
  • EPALs E-programmable gate arrays
  • EPROM EPROM
  • EEPROM's electrically erasable programmable read-only memory

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Procédé et appareil de production d'un dispositif à circuit intégré permettant une tension élevée de seuil d'oxyde épais par réduction au minimum des transistors parasites s'y trouvant. Dans ce système, une couche d'oxyde est ménagée sur le transistor. La couche est ensuite gravée jusqu'à la partie supérieure de la couche de nitrure, permettant ainsi d'utiliser des parties d'oxyde situées sur ses côtés en tant que masque, lorsque la couche implantée est apportée. Ces parties d'oxyde sont utilisées afin d'espacer la couche implantée sous l'oxyde épais à l'opposé de la région source-drain du dispositif, et par conséquent la tension de claquage est efficacement augmentée.
PCT/US1995/013138 1994-11-28 1995-10-18 Procede et systeme de production d'un dispositif a circuit integre permettant une tension elevee de seuil d'oxyde epais utilisant des elements d'espacement en oxyde Ceased WO1996017379A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US34517894A 1994-11-28 1994-11-28
US08/345,178 1994-11-28

Publications (1)

Publication Number Publication Date
WO1996017379A1 true WO1996017379A1 (fr) 1996-06-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1995/013138 Ceased WO1996017379A1 (fr) 1994-11-28 1995-10-18 Procede et systeme de production d'un dispositif a circuit integre permettant une tension elevee de seuil d'oxyde epais utilisant des elements d'espacement en oxyde

Country Status (1)

Country Link
WO (1) WO1996017379A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0239384A2 (fr) * 1986-03-27 1987-09-30 Advanced Micro Devices, Inc. Procédé pour isoler les dispositifs semi-conducteurs dans un substrat
US4965221A (en) * 1989-03-15 1990-10-23 Micron Technology, Inc. Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions
US5196367A (en) * 1991-05-08 1993-03-23 Industrial Technology Research Institute Modified field isolation process with no channel-stop implant encroachment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0239384A2 (fr) * 1986-03-27 1987-09-30 Advanced Micro Devices, Inc. Procédé pour isoler les dispositifs semi-conducteurs dans un substrat
US4965221A (en) * 1989-03-15 1990-10-23 Micron Technology, Inc. Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions
US5196367A (en) * 1991-05-08 1993-03-23 Industrial Technology Research Institute Modified field isolation process with no channel-stop implant encroachment

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
R. MARTIN: "REDUCED DOPING ADJACENT FIELD IMPLANT", XEROX DISCLOSURE JOURNAL, vol. 12, no. 5, STAMFORD, CONN US, pages 249 - 250, XP000050034 *
R. MARTIN: "SPACER FOR IMPROVED LOCAL OXIDATION PROFILE", XEROX DISCLOSURE JOURNAL, vol. 12, no. 5, STAMFORD, CONN US, pages 251 - 253, XP000110800 *

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