WO1996005657A1

WO1996005657A1 - Electronic counter device

Info

Publication number: WO1996005657A1
Application number: PCT/GB1994/001744
Authority: WO
Inventors: Christopher William Haythornthwaite; David William Clark; Ian David Griffiths
Original assignee: GENESIS GROUP Ltd
Current assignee: GENESIS GROUP Ltd
Priority date: 1993-02-03
Filing date: 1994-08-09
Publication date: 1996-02-22
Anticipated expiration: 1997-02-09

Abstract

An electronic counter device ('e.c.d.') comprising: (i) a counter input for receiving data representing successive counts; (ii) means for accumulating the counts received through said input; (iii) at least one count display for displaying the accumulated count or a value derived therefrom; (iv) an electronic non-volatile memory; (v) means for storing the accumulated count in the electronic non-volatile memory in response to recognition of data or signals resulting from one or more external predetermined events, for example power failure; the counter device thereby being adapted to emulate a conventional electromechanical counter and thus affordss in use, a relatively more secure, tamper-proof replacement therefor.

Description

pi FΓ.TRONIC COUNTER DEVICE

Field of the Invention

This invention relates to an electronic counter device suitable for use as a replacement for the electro-mechanical counters currently used in gaming machines, vending machines, product counting on production lines, and the like.

Background to the Invention

An example of the type of machine currently employing electro¬ mechanical counters is the gaming machine which is generally provided with one or more counters or meters to enable the operation of the machine to be monitored. For example, the numbers of coins or tokens of specified types inserted into the machine can be recorded, together with numbers of coins or tokens paid out in prizes. This information can be used to assess the profitability of the machine, and its pay-out ratio for example. With the increasing sophistication of the machines, there is a need for more detailed information to be recorded. In addition, it is increasingly necessary to take measures against fraud by tampering with the operation of the machine and the meters.

While electronic counter devices or meters can provide a greater amount of stored information on the operation of the gaming machine in which they are installed, they can be more open to tampering for fraudulent purposes, and there is a risk of data loss in the event of a power failure unless costly solutions such as uninterruptible power supplies are used.

Further, while electronic counter devices offer the possibility of downloading data to an external device such as a monitoring computer, such a facility also offers another opportunity for fraud.

The present invention seeks, in its various aspects, to provide an electronic counter device which overcomes these disadvantages.

Summary of the Invention

According to one aspect of the invention, an electronic counter device comprises a counter input for receiving an electrical signal representing successive counts, means for accumulating the counts received at said input, display means for displaying the count or a value derived therefrom, a clock for outputting the current date and time, a non-volatile memory, and means for storing the instantaneous count, date and time in the non-volatile memory in response to detection of any one of a plurality of predetermined events.

The predetermined events include: an attempt to download data to the counter with the incorrect protocol; an input signal rate exceeding the specified rate; and a loss of system power supply for more than a predetermined period, for example 500ms. The display may also include a plurality of dedicated icons to indicate events such as those specified above and detection of tampering.

Preferably, the counter device comprises means for separately accumulating a plurality of counts. Thus, all the accumulated counts are stored in the non-volatile memory along with the date and time in response to detection of any of the predetermined events.

Another aspect of the invention provides an electronic counter device in data communication with an external device, the counter device comprising means for receiving data representing counts and for accumulating values derived from the counts, and communication means for transmitting data to and receiving data messages from the external device, the data messages comprising data representing counts or data relating to the derivation of values from the counts, the external device being arranged to transmit discrete data messages to the counter device continually with a time interval therebetween no greater than a predetermined value and the external device and counter device being arranged to perform at least one handshake therebetween in association with the transmission of each data message, the failure of any handshake interrupting repetition of the data messages, thereby indicating an error.

The handshake preferably comprises the transmission by one device of a predetermined value, followed by the return by the other device within a predetermined time limit of a predetermined response value. Preferably, for each data message, the handshake comprises performance by the counter device of a checksum calculation on the data message and transmission of the result to the external device. Brief Description of the Drawings

In the drawings, which illustrate one example of a counter device of the invention:

Figure 1 is a block circuit diagram of a counter device;

Figure 2 is a diagram illustrating the relative clock and data pulse timings in accordance with standard protocol;

Figure 3 is an expanded section of the diagram of Figure 2; and

Figure 4 is a flow chart illustrating the operation of the counter device in accordance with the second aspect of the invention.

Detailed Description of the Illustrated Embodiments

The counter device comprises five count input ports la to le, each having its respective input buffer 2a to 2e through which counts are input to a microcontroller 3 as pulses complying with the specification set out in the Table below.

Table: Standard Count Input Electrical Specifications

PARAMETER UNITS VALUE RANGE

Max. ON input voltage V 0.6 5%

Min. OFF input voltage V 3.6 5%

Max. Input Frequency Hz 3.0

Max. ON time ms 190

Min. ON time ms 165

Min. OFF time ms 165

Max. Rise/fall time ms 0.4

Max. switch bounce time ms 2

Count accuracy (counts lost) 0 0

Count Range (max digits) 8 -

The microcontroller 3 outputs values related to the counts to a display 4, for example a 40 digit, 7 segment LCD display, capable of displaying an 8-digit value for each of the five inputs.

The microcontroller is supplied with operating power via a power supply unit 5, which also removes excessive interference from the input supply, for example voltage spikes, caused by the proximity of other electro-mechanical components of the host machine. The power supply unit also detects a failure in the supply and enables a battery backup support 6 to maintain operation of the counter device for a sufficient time to permit the counts to be stored for retrieval when power is restored. A non-volatile memory, for example in the form of an Electrically-Erasible Programmable Read Only Memory or EEPROM 7, is used to store the counts, or the related values, together with time and date in the event of a power failure, loss of communications or detection of any attempt to tamper with the counter device by downloading incorrect data. The EEPROM having a limited capacity, it is used as a ring buffer, with the oldest data overwritten by the newest.

A bidirectional serial channel 9 provides an alternative communication with the computer in the host machine or with an external device.

This is subject to a secure communications protocol, described hereinafter with reference to Figure 4.

Figures 2 and 3 illustrate a simple serial protocol designed to be driven from existing meter drive circuitry common to all types of gaming machines, for example. Up to 5 internal counters and 3 external satellite counters may be addressed, but only one count can be added to any counter at any time. Connection is made between the existing +12V and two counter inputs. The first input is used as a twin edge clock source and a source of ground potential, while the second input is the data stream and also provides a ground potential. Both inputs are used as the current feedback sense path. When the device is not in use, the two inputs are both inactive, open circuit and are pulled high by resistors (not shown) in the device. To begin a meter count or test cycle, two synchronisation pulses are sent by driving both inputs low simultaneously with a pulse timing indicated in Figures 2 and 3. The inputs are then driven low simultaneously for a minimum period of 40ms and a maximum period of 45ms. This period between the end of the synchronisation pulses and the start of the clocking cycle is called the start period. The low to high transition of the first input (designated as the clock signal) causes the level on the output designated as the data output to be read into the device approximately 5ms later (this settling time allows for systems where these outputs cannot change simultaneously). Thereafter, each change in the state of the clock input marks the next data bit to be read. If the voltage level at the second input (designated data input) is low between 4ms and 8ms after the appropriate clock edge has changed, then the data bit will be deemed to be set (i.e. logical TRUE or 1), and if the data input voltage is high at this time, then the data bit is deemed to be clear (i.e. logical FALSE or 0). There is a maximum time period between active edges of the data clock of 20ms, and any interval longer than this constitutes a timeout. If a timeout does occur, the current data frame is ignored, and a new data frame cannot start until the synchronisation pulses and start period as hereinbefore defined have been received.

The data input after the start period has ended has the following significance:

1. Three data bits giving the meter number to be actioned. The least significant bit is transmitted first. 2. A test meter bit. If this bit is set, the addressed meter requested is tested and returns the normal fire current if it is present and working correctly, but the meter is not pulsed. If this bit is cleared, the meter is pulsed as normal.

3. A parity bit. This bit is set if an odd number of the three data bits and the test meter bit described in 1 and 2 are set.

After the trailing edge of the third clock pulse J (Figure 2), both inputs are driven low for at least 105ms to confirm this transaction. The meter load is developed across the +12V DC line and the inputs allowing the current to be sensed at the host system. If the meter circuit detects that a test phase has been initiated, it will increase the supply load during this test phase by the equivalent amount of the mechanical metering system, if the metering system is functioning correctly. If the host is issuing a meter count message, then an increase in the supply current equivalent to the normal mechanical metering system will be simulated by this meter. This will be sensed by the host in the same way that mechanical meter integrity is checked.

When the current sense pulse ends, or after 106ms if detection by the host system is not possible, the inputs return to their inactive high state and any active supply load will be removed. The timing relationship between the inputs is shown in Figures 2 and 3. The maximum current drawn by the counter device during non-pulse periods will be less than 1mA. During active pulse or test periods it is the same as for a mechanical meter. Data is valid between 4ms and 8ms from the point at which the clock input voltage is at 50% of its maximum value on the rising or falling clock edge. The input circuit is arranged to reject spikes of up to 2ms, and by inference will also delay the clock edge by up to 2ms. The clock and data transmissions should therefore be as near as possible coincident, or the clock should lag the data transmission by no more than^' 2ms. The interval between each successive cycle, defined as the time between the start of two successive start periods, must not be less than 300ms.

A higher level method of data exchange between a host computer and the counter device of the invention is set out in the flow chart shown in Figure 4. The connection 9 (Fig 1) between the host computer and the counter device can use 2 TTL compatible signal lines (and a common ground) to transfer data. One line is data received (DRX) and the other is data transmitted (DTX). Data is suitably transmitted in a serial format in accordance with the data timing protocol of RS232C (but with TTL voltage levels as per RS423). Alternatively, communication with an internal device can be by optical or radio coupling.

In this embodiment of the invention, although the value displayed by the counter device for each counter may be a simple count, it may alternatively be a value derived therefrom. For example, if each count represents number of a particular value of coin paid into the gaming machine, a separate counter display for each input may show the total monetary value of each type of coin, with another counter indicating the aggregate value of all the coins, for example.

A transaction will be initiated by the host computer by transmitting SOH (OlHex) to the counter device, which will respond within a predetermined period with a VERIFY byte which is generated randomly or pseudorandomly. If the VERIFY byte is received, the host computer returns a KEY byte which it generates from the VERIFY byte by any suitable encoding algorithm. The counter device compares the returned KEY byte with the VERIFY byte it sent using the same stored algorithm, and if the KEY byte is correct, the counter device responds with ACK (06Hex). If the KEY is wrong, the counter device does not return ACK and so the host computer returns to the sign-on error handler. The counter device is arranged to flag an error if, say, two wrong KEY bytes are received consecutively, and to close down and ignore all further serial input for a predetermined period, for example one hour. The sign-on error handler permits only three attempts at signing on, for example.

The host computer maintains a timer which will ensure that a message is sent at regular predetermined intervals, for example of three seconds, whether or not the counter needs to be addressed. This will make it very difficult to tamper with the system, since both the host computer and the counter device will detect a break in communications, and can thus give an indication of an attempt to tamper with the system.

The message timer will be reset after ACK has been received, and the host computer will then check to see if a message needs to be sent to the counter device. If not, it checks that a message has been sent within the previous three seconds (or whatever the maximum interval set is to be). If no message has been sent within this period, the host computer initiates the sign on procedure by sending SOH.

If a message is pending, the host computer sends the data byte to the counter device, for example in the form previously described in which the three least significant bits give the address of the meter to be incremented and the remaining bits constitute the data.

On receipt of this message, the counter device calculates the check sum of this message and transmits that check sum to the host computer. If the host computer confirms that this check sum is correct, it transmits ETX (03Hex) to the counter device, which responds by transmitting EOT (04Hex) to the host computer. If the host computer receives EOT within the specified response time, it resets its message timer and restarts the main loop. If the received check sum is incorrect, the host computer transmits NUL (OOHex) to the counter device, and after receiving EOT from the counter device, resets the message timer and resends the message to the counter device.

If at any time during this transaction the host computer does not receive a handshake message within the response period set, it transmits nothing for one second and then executes a suitable communications time out error handler and initiates the sign on loop by sending SOH. The one second delay allows the counter device to attempt to recover from the partial message transaction, and to set an internal software flag to record the aborted message transaction.

If there is no new message to send in the main loop, the process repeatedly returns to the main loop start until three seconds have elapsed from the sending of the last message, when there is a return to the sign on procedure. To enhance security of the encoding algorithm, it is preferable to remain in the message loop and test the integrity of the counter device repeatedly without changing any data. This is done by sending a blank message, for example instructing the counter device to add 0 to any counter address.

It will be seen from Figure 4 that two alternative routes are available, depending upon whether data is to be sent to the counter device or whether it is to be downloaded from the counter device. If readback is selected, the testing by means of the checksum is not required. Instead, the request for readback either elicits the required data, in which case there is a return to the main loop start after resetting the message timer, or no data is received, in which case the communications time-out error handler will cause a return to the sign-on procedure.

Although communication of the count data between the computer in the host machine and the counter device has been described, it will be understood that the same method of data transfer can be used between an external device, such as a temporarily-connected monitoring computer, and the counter device. Some of the data bits in each byte may be reserved to signal to the counter device that data is to be returned to the monitoring computer, and to indicate which data is required to be sent. This would permit downloading of count data from the counter device to the external computer and the downloading of scaling factors from the external computer to the counter device, permitting values to be ascribed to each count. For example, a coin-operated machine may be adapted to accept a new coin, and the counter device can be modified in this way to register the aggregate value of that type of coin inserted. So, if the coin has a value of 50 units, the counter relating to that coin can be incremented by 50 each time a coin is inserted in the machine and a single count is passed to the counter device.

Claims

1. An electronic counter device ("e.cd") comprising:

(i) a counter input for receiving data representing successive counts;

(ii) means for accumulating the counts received through said input;

(iii) at least one count display for displaying the accumulated count or a value derived therefrom;

(iv) an electronic non-volatile memory;

(v) means for storing the accumulated count in the electronic non- volatile memory in response to recognition of data or signals resulting from one or more external predetermined events, for example power failure;

the counter device thereby being adapted to emulate a conventional electromechanical counter and thus affords in use, a relatively more secure, tamper-proof replacement therefor.

2. . An e.cd. as claimed in Claim 1 which further comprises a clock for out-putting the current or relative date and time, wherein the date and time are recorded in non-volatile memory along with the accumulated count(s) in response to detection of any one of a plurality of predetermined events.

3. An e.cd. as claimed in Claim 1 or Claim 2 in which the e.cd. is in intelligent data communication with a device external to the counter, and further comprising communication means for transmitting data to and receiving data messages from the external device, the data messages comprising data representing counts or data relating to the derivation of values from the count, the external device being arranged to transmit discrete data messages to the counter device continually with a time interval therebetween no greater than a predetermined value and the external device counter device being arranged to perform at least one handshake therebetween in association with the transmission of each data message, the failure of any handshake interrupting repetition of the data messages, thereby indicating an error.

4. An e.cd. as claimed in Claim 3 wherein the handshake comprises the transmission by either the counter device or the external device of a predetermined value, followed by the return by the other device within a predetermined response value.

5. An e.cd. as claimed in Claim 3 or Claim 4 wherein for each data message, the handshake comprises performance by the counter device of a checksum calculation on the data message and transmission of the result back to the external device.

6. An e.cd. as claimed in any of Claims 1 to 5 wherein the device is adapted to separately accumulate and store in non-volatile memory a plurality of counts.

7. An e.cd. substantially as herein described with reference to and as illustrated in any appropriate combination of the accompanying drawings.