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WO1995005679A1 - Transistors bipolaires et leur procede de fabrication - Google Patents

Transistors bipolaires et leur procede de fabrication Download PDF

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Publication number
WO1995005679A1
WO1995005679A1 PCT/GB1994/001787 GB9401787W WO9505679A1 WO 1995005679 A1 WO1995005679 A1 WO 1995005679A1 GB 9401787 W GB9401787 W GB 9401787W WO 9505679 A1 WO9505679 A1 WO 9505679A1
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WO
WIPO (PCT)
Prior art keywords
base
collector
emitter
mask
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/GB1994/001787
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English (en)
Inventor
Peter Fred Blomley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
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Filing date
Publication date
Priority claimed from GB939317054A external-priority patent/GB9317054D0/en
Priority claimed from GB939325754A external-priority patent/GB9325754D0/en
Application filed by Individual filed Critical Individual
Priority to GB9507916A priority Critical patent/GB2288069B/en
Priority to AU73887/94A priority patent/AU7388794A/en
Publication of WO1995005679A1 publication Critical patent/WO1995005679A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs

Definitions

  • This invention relates to bipolar transistors especially the devices that are created by means of a Bipolar Complementary Metal-Oxide-Semiconductor (BICMOS) manufacturing process and to a method of making such transistors.
  • BICMOS Bipolar Complementary Metal-Oxide-Semiconductor
  • BICMOS integrated circuit devices comprise of a substrate (normally P type) which carries the N type and P type semiconductors, arranged in different regions so as to define the CMOS and Bipolar devices.
  • a substrate normally P type
  • P type the N type and P type semiconductors
  • Each Bipolar device which has an emitter, base and collector, is limited in performance by the base and collector resistance, ie the resistance between each of the active base and collector regions and their respective contacts.
  • the base and collector resistance in an integrated circuit bipolar device can be reduced by means of a buried layer of a low resistivity material.
  • a buried layer cannot be provided if a simple BICMOS process is to be used to fabricate the device.
  • a bipolar transistor which is fabricated by means of a BICMOS process comprises an active collector, emitter and base respectively connected to collector emitter and base contacts, wherein a material of low electrical resistivity is provided between the collector contact and at least two spaced apart regions of the active collector so as to provide at least two low resistance current paths between the collector contact and the active collector.
  • the invention enables the resistance and capacitance of the bicmos device to be significantly reduced, enabling the device to have a high Ft (transition frequency) , and thus to operate at high frequencies.
  • the device has two regions of the low resistance material which are spaced apart so as to form two shunt regions between which the active collector is interposed, and preferably has two collector contacts each connected to a respective one of the shunt regions .
  • the shunt regions preferably comprise implants in a bed of a semi conductor which constitutes the active collector.
  • the device can be of a relatively simple construction since there is no need for the shunt regions to be formed as a buried layer.
  • each shunt region Preferably a respective collector contact is directly connected to each shunt region.
  • the shunt regions may comprise an n-type semi conductor, which is more heavily doped than the active collector.
  • Such a material is typically referred to as an n+ material.
  • the sub-emitter resistance can also be reduced by means of a p+ material (ie a p-type semi conductor more heavily doped than the base) extending between the active base and the base contact so as to provide a plurality of low resistance current paths between the base contact and the active base (positioned immediately beneath the emitter) .
  • a p+ material ie a p-type semi conductor more heavily doped than the base
  • the p+ material completely surrounds the base region and the n+ material constituting the shunt region surrounds the latter except for a gap through which the p+ material connecting the active base to the base contact extends.
  • platinum disilicide may be formed by depositing platinum on the p and n regions in the silicone substrate in a manner known per se.
  • each shunt region includes an outer zone and an inner zone, which is at least partially surrounded by the outer zone, and which is of a lower electrical resistivity than the outer zone.
  • the material of the inner zone preferably comprises an n type semi conductor which is more heavily doped than the n+ material .
  • the heavier doping can be achieved by means of a greater concentration of atoms of dopant than in the n+ material, or by using a dopant material which, when implanted, makes more charges available for the conduction band of the semi conductors.
  • a semi conductor so doped shall be referred to as an n ⁇ + material .
  • the n++ material may to advantage comprise an n type semi conductor doped with arsenic, and the n+ material preferably comprises an n type semi conductor doped with phosphorus .
  • the transistor is one of a plurality of such transistors on a common substrate which includes a plurality of oxide strips for separating adjacent pairs of the devices, wherein the shunt regions are elongate and extend under said oxide strips substantially parallel thereto, and each collector contact is situated at one end of a respective shunt region.
  • both collector contacts of each device are situated adjacent each other at the same end of their respective shunt regions .
  • a method of introducing into a semi conductor a region of low resistance for use as a shunt region in a bipolar transistor fabricated by means of a BICMOS process comprising the steps of :
  • the material implanted at the second implanting step may be the same as said first dopant material, but preferably comprises a second dopant material different from the first dopant material.
  • the position at which the first and second implantations occur is defined by applying to the semi conductor a mask having a window overlying said position, the mask being capable of withstanding said heating step so that the mask can be used in both implanting steps.
  • the mask comprises a coating of polysilicone.
  • the polysilicone of the mask may to advantage be applied by applying as a coating a layer of polysilicone; coating the polysilicone with a substance which can be cured by electromagnetic radiation; exposing to such radiation, and hence curing, those parts of said substance which are not in the position corresponding to the position in which the window is to be created, and removing said uncured region of the substance and the underlying polysilicone to create said window.
  • the invention avoids the need to apply successive masks to the material, one mask for each implantation.
  • a method of making a transistor comprising the steps Of :
  • the treatment of the substrate includes successively applying thereto the collector, the base and the material to constitute the cover, and then treating the latter to create the emitter, the low resistance material being implanted before the application of the material to constitute the cover.
  • the method includes the steps of attaching a mask to the base at a position overlying the position which, in the finished article, is occupied by the emitter, and implanting the low resistance material by subjecting the base and mask to a particle bombardment, the mask preventing the low resistance material from encroaching on the emitter.
  • the mask is then used to define the position of the emitter in the device. This can be done by applying a coating of a further substance, and then removing the mask to leave a window in the coating which, itself, acts as a further mask.
  • the initial mask may be siiicone nitride
  • the coating may be of silicone oxide formed by placing the mask and surface in a oxidising environment. Since silicone nitride cannot be readily oxidised the oxide coating does not form on the nitride mask which can therefore be removed by a treatment (for example by washing in phosphoric acid) which does not affect the oxide layer.
  • the mask may with advantage include a lateral extension of a different material from the rest of the mask, which extension is removed before the mask is used to define the window so as to ensure that the low resistance material is spaced from the region to be occupied by the emitter.
  • the extension is preferably formed by coating the mask with silicone oxide in such a way that there is a greater thickness of silicone oxide at a side of the mask and on the rest of the mask and then etching by way a thickness of silicone oxide corresponding to the thickness of the oxide on said rest of the mask.
  • the low resistance material is implanted into two regions which flank the base so as to provide two parallel low resistance parts .
  • the low resistivity material comprises a p+ semi conductor.
  • said cover is of polysilicone.
  • Figure 1 is a plan view of a device according co the invention
  • Figure 2 is a diagrammatic partially cut-away view of the device
  • Figure 3 is a diagrammatic sectional side elevation of a modified version of the device
  • Figure 4 is a partially cut away view of the device shown in Figure 3 ;
  • Figure 5 illustrates a number of stages of a process for creating either of the shunt regions used in the device shown in Figures 3 and 4 ;
  • Figure 6 illustrates the number of stages of the process used to implant the p+ material into the device shown in Figures 3 and 4;
  • Figure 7 shows further stages of the process illustrated in Figure 6 ;
  • Figure 8 is a plan view of a plurality of the devices shown in Figures 3 and 4 mounted on a common substrate.
  • the device shown in Figures 1 and 2 comprises an npn-type transistor in which an a strip 1 of n-type semi-conductor overlies a strip 2 of p-type semi-conductor. Strips 2, in turn overlies a bed 4 of an n-type semi-conductor which forms a well which acts as a collector.
  • the device has an emitter which is constituted by an active and a passive emitter.
  • the active emitter which is denoted by the reference number 3
  • the passive emitter is constituted by the remainder of the strip 1.
  • the bed 4 comprises an active and a passive collector, the active collector being the portion of the bed 4 at the interface with the strip, which constitutes the base of the device.
  • the active emitter and collector are those parts of the emitter and collector respectively, which, in use, directly exchange charge carriers with the base .
  • the strip 1 also acts as a protective cover for the active emitter 3.
  • the bed of n-type material 4 is deposited on a substrate 6 of a p-type material, and extends laterally beyond either side of the emitter 3 and base 2.
  • a region 8 of low resistance material In the upper surface of the bed 4 there is provided a region 8 of low resistance material, the region 8 being generally U-shaped when viewed in plan.
  • the material constituting the region 8 is a n-type semi-conductor which is more heavily doped than the material constituting the bed 4, i.e. n+ material.
  • n+ material One example of a dopant for the n+ material is a combination of phosphorous and arsenic.
  • the two spaced apart arms of the U-shaped region 8, respectively referenced 10 and 12 flank a central region of the bed 4 which constitutes the active collector.
  • the arms 10 and 12 extend laterally away from the central region of the bed 4, and make contact with two respective surface strips of n+ material, 14 and 16 respectively connected to collector contacts 18 and 20 (Figure 1) which are, in turn connected to a common connector 22 in the form of a metal strip.
  • collector contacts 18 and 20 Figure 1
  • the arms 10 and 12 also make contact with a ring of p+ material 24 which surrounds the base 2 and connect the base to a base contact 28 which is in turn connected to a metal strip 30 ( Figure 1) .
  • the emitter 1 is similarly connected to a respective contact 32 •which is connected to a connector strip 34.
  • the emitter contact 32, the connector strip 34, the base contact 28 and the base connector strip 30 have all been omitted from Figure 2 for the sake of clarity.
  • a strip oxide, 38 which is doubled back on itself and which separates the connector strips 14 and IS from the emitter 1 and base 2 and their respective contacts and connector strips.
  • the strip 38 includes an inner flange 40 which insulates the emitter from the ring of P+ material 24.
  • electrons passing into the active collector in the bed 4 from the base 2 may travel to the strips 14 and 16 (and thence to the collector contacts 13 and 20) along a relatively low resistance path which passes through the arms 10 and 12. That path is generally indicated by the arrows A and B in Figure 2. Accordingly, the active collector in the bed 4 is connected in parallel to the collector contacts 18 and 20 by material having a relatively low resistance.
  • the presence of the ring 24 of p+ material further reduces the resistance of the device by reducing the sub-emitter resistance (i.e. by facilitating conduction between the base contacts 28 and the base 2) .
  • the device is flanked by two oxide strips 48 which separate the device from other devices (not shown) printed onto the same substrate 6.
  • the modified version of the device also includes a substrate 100 of p type material which carries a bed 102 of n type material.
  • the bed 102 has implanted therein a u shaped shunt region having spaced apart arms 104 and 106 which flank an active collector constituted by the portion of the bed 102 at the interface with a strip of p type semi conductor which constitutes a base 108.
  • the base 108 is in contact with an active emitter 110 formed in the region of the interface between the base 108 and an overlying strip 112 of n type polysilicone which sits on an oxide layer 114, and makes contact with the active emitter 110 through a window in said oxide layer 114.
  • the base 108 is surrounded by an implant 116 of a p+ material which, when viewed in plan, is of a similar shape to the coating 114.
  • the implant 116 provides a low resistance path between the base 108 and a base contact 118 spaced therefrom.
  • the u-shaped collector shunt has an outer zone 120 of n+ material formed by implanting a phosphorus dopant into the bed 102 and an inner zone 122 of n++ material formed by implanting a dopant of arsenic at a concentration 5 x 10 19 atoms per square cm.
  • the inner zone 122 is positioned immediately beneath a layer of field oxide 124 which surrounds the layer 114. Both inner and outer zones extend in a direction substantially parallel to the strip 112 from a region in which they are substantially aligned with the contact 118, to the end of the device at which there are provided two collector contacts 126 and 128 ( Figure 8) which are connected to the inner zone 122.
  • the zones 120 and 122 are created prior to the formation of the base 108, the active emitter 110 and the regions of p+ material 116 on the bed 102. The process of implanting the two zones 120 and 122 will now be described.
  • the bed 102 is coated with a first layer 130 of silicon oxide, formed in situ on the bed 102 by placing the latter in an oxidising environment.
  • a layer 132 of silicone nitride is then applied to the layer 130 by a process of chemical vapour deposition, and a layer 134 of a photo resistive material is subsequently applied by placing a drop of photo resistive material on the layer 132 and then spinning the substrate and the layers on it so as to subject the drop to centrifugal forces which spread it across the layer 132.
  • Ultra violet light is then shone on to the layer 134 through a mask 136 which has openings which define the parts of the layer 134 which are exposed to the ultra violet light. Those parts (referenced 138 and 140) remain on the layer 132 when the remainder of the layer 134 is removed by a process of washing.
  • stage 3 the areas of the layer 132 which are not covered by the parts 138 and 140 are removed by a process of etching with phosphoric acid.
  • the parts 138 and 140 prevent the underlying portions of the layer 132 being removed in this process.
  • the parts 138 and 140 are removed, leaving just two strips of nitride 142 and 144 on the layer 130.
  • a layer 148 of polysilicone is deposited on the strips 142 and 144 and the exposed portions of the layer 130, and the layer 146 is then covered by a further layer 148 of photoresistive material applied in a similar fashion to the layer 134.
  • Stage 5 of the process involves exposing the layer 148 to ultra violet light through a mask 150 having a portion 152 of which casts a shadow over the central portion of the layer 148 (as shown in the drawing relating to stage 5) .
  • the arrangement is then subjected to a chemical treatment which does not remove that portion of the layer 148 which was cured by the ultra violet light, but does remove the central uncured portion of the layer 148 and the corresponding underlying portion of polysilicone. As can be seen from the drawing of stage 5, this leaves a respective exposed portion, 156 and 158 on each of the strips 142 and 144.
  • the whole arrangement is then subjected to a bombardment of phosphorus atoms so as to implant the phosphorus into a region
  • the layer 148 does take up some phosphorus atoms, but prevents any significant amount of phosphorus absorbed into the layer 146. This avoids the risk of phosphorus subsequently contaminating the portion of the bed 102 underlying 146, and hence the active collector, which will subsequently be located in that region.
  • the layer 148 is then washed off and the arrangement is then heated to a temperature of 1100°C and maintained at that temperature, typically, for three hours.
  • the heating causes the phosphorus atoms originally in the region 154 to defuse through part of the bed 102 so as to define the outer zone 120.
  • the layer 146 contains no phosphorus, or at least insufficient amounts of phosphorus, to defuse into, and thus contaminate, the region to be occupied by the active collector in the bed 102.
  • the inner zone 122 of arsenic is implanted by a process of particle bombardment sufficient to provide a concentration of 10 15 arsenic atoms per cm 2 in the region 122.
  • the layer of polysilicone 146 prevents subsequent contamination of the region of the bed 102 to be occupied by the active collector.
  • the layer 146 is then removed, and the region of field oxide 124 is applied in the gaps between the strips of nitride (on which oxide cannot grow), which are then removed, together with the part of the layer 130 underlying the nitride, prior to the creation of the base and the emitter on the bed 102.
  • a further thin oxide layer 159 is then grown on the bed 102 in the region between the areas 124 of field oxide.
  • a p type semi conductor material is then 124 of field oxide.
  • a p type semi conductor material is then created in a region 160 of the bed 102, by implanting a suitable dopant, so that the whole of the bed 102 is covered with silicone oxide .
  • stage 2 of the process a thin layer of polysilicone 162 is deposited on the oxide 159 and 124.
  • a layer 164 of silicone nitride and an overlying layer 168 of polysilicone are then applied to the polysilicon layer 162.
  • a portion of the layer 168 is then cured by exposure to ultra violet light passing through a window in a mask 170 and the layer 168 is then subjected to a washing process which removes just the uncured portions of the photo resistive material to leave a block 172.
  • the material overlying the layer 162 is then subjected to a plasma etching process which removes a predetermined thickness of material (where the cured photo resistive material or silicone nitride) . That thickness corresponds to the thickness of the layer 164 and of the block 172 so that, after said etching, the only nitride left on the layer 162 is a block 174, which is the nitride previously overlaid by the block 172.
  • a layer (not shown) of silicone oxide is then applied to the layer 164 and the block 174.
  • the oxide layer is deposited in such a way that it has a uniform thickness apart from in the region of the side walls of the block 174 in which regions the thickness of the oxide layer is approximately doubled.
  • the oxide layer is then progressively etched away by means of a plasma etching process until the only oxide left on the layer 162 is in the region where the original oxide layer was of increased thickness, ie the sides of the block 174.
  • the remaining oxide defines side extensions 176 and 178 on the nitride block 174.
  • boron atoms are then implanted into the bed 4 by means of particle bombardment so as to provide the p+ region 116, the nitride block 174 and regions of the bed 102 from the boron atoms.
  • the side extensions 176 and 178 are then removed by means of a chemical treatment which does not remove the block 174, and a further layer of oxide 180 is created on that part of the polysilicone layer 162 which is not covered by the block 174.
  • the nitride block 174 is then removed by treatment with phosphoric acid which does not remove the oxide layer 100. Consequently, as can be seen from the illustration of stage 7, the oxide layer 180 includes a window 182 corresponding to the previous position of the block 174.
  • a dry etching process is then used to remove the portion of the polysilicone layer 162 and underlying the window 182. As can be seen, this process does not effect the oxide layer 180. Hydrofluoric acid is then used to remove the layer 180 and the portion of the outside layer 159 within the window 182 to leave the arrangement shown in the stage 9 illustration.
  • a further layer 184 of polysilicone is deposited on the layer 162 and the portion of the region 160 within the window 182.
  • Arsenic atoms are then implanted into the layer 184 to a concentration of 1.2 x 10 16 atoms per cm squared, and the arrangement is then subjected to a process of rapid temperature annealing (RTA) which causes the layers 162 and 184 to merge together and the active emitter 110 to be created at the interface between the polysilicone and the region of p type material 160 some of the polysilicone is subsequently removed to leave the strip 112 which acts as both a passive emitter and a cover for the active emitter 110.
  • RTA rapid temperature annealing
  • the base, collector and emitter contacts are then applied.
  • the base, collector and emitter contacts are then applied.
  • the substrate carries a number of CMOS devices such as n and p channel devices in addition to one or more bipolar transistors.
  • a typical BICMOS device has two distinct regions that define the total base resistance.
  • the first is the "sub emitter” region (intrinsic) which has benefited by using the poly emitter and second extrinsic base region underneath the poly.
  • the sub poly region will only be doped by the base implant to about 1500 ohms per square compared with the contact P+ material of only 150 ohms per square. This high resistance dramatically limits the use of this sub poly base region for interconnecting the various areas of the device.
  • the emitter "cut" or window is directly related to the size of the feature projected from the outline of the emitter UV light mask. This "one to one" relationship between the mask and the emitter window size facilitates the matching of the performance (defined by the matching of the areas of two emitter windows) , of bipolar transistors made in this way.
  • the present process enables this "one to one" approach to be created between UV light mask 170 size and the final emitter window and it also reduces the sub poly resistance from 1500 ohms per square down to 150 ohms per square by the use of a P+ implant .
  • the poly material 162 by the addition of a patterned nitride layer and several extra process stages, is also used to define the emitter window 182.
  • This emitter window is created by locally oxidised (300 Angstroms) (stage 6.2) this poly layer with a patterned layer of nitride to form an etch stop in all areas apart from where the emitter cut through the poly is needed (stage 8) Figure 7.
  • the layer of nitride had been previously etched, o a pattern defined by the emitter mask, on top of the poly-silicon surface.
  • the size of the emitter is still directly related to the size of the nitride pattern which in turn was defined directly by the mask used for the emitter stage.
  • this nitride layer can also be used as the implant mask for the blanket P+ (stage 5.2) .
  • the nitride edges can be covered in a deposited oxide and etched to produce "side walls". These side-walls space the P+ implant around 0.2 micron away from the emitter edge so as to avoid P+N+ tunnelling effects.
  • the P+ implant is now below the over lapping N+ emitter poly and that the emitter size (h) directly relates to the initial mask window size (j) . It should also be noted that one of the final advantages of this approach is the total N+ poly 112 overlap from the emitter window edge acts as a field plate over the sensitive surface regions of the emitter base depletion layer. This field plate avoid leakage and stress problems.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

On fabrique selon un procédé BiCMOS, un transistor bipolaire qui comprend un collecteur actif (4), un émetteur (3) et une base (2) raccordés, respectivement, aux contacts destinés au collecteur, à l'émetteur et à la base. Le fonctionnement du transistor est amélioré grâce à un matériau de faible résistivité électrique qui est placé entre le contact du connecteur et au moins deux régions mutuellement espacées du collecteur actif, de façon à créer au moins deux régions de dérivation (10, 12) espacées l'une de l'autre et entre lesquelles est intercalé le collecteur actif. Les régions de dérivation peuvent être créees par implantation d'un premier matériau dopant dans le semi-conducteur qui est ensuite chauffé de sorte que le dopant se répande dans le semi-conducteur afin de créer une première zone, et par implantation d'un matériau dopant, au même endroit, destiné à créer une seconde zone dont la résistivité est inférieure à celle de la première zone. Le procédé de fabrication de ce transistor consiste à traiter un substrat de façon à créer sur celui-ci un collecteur, une base et un émetteur qui recouvrent le collecteur et la base, ainsi que des contacts électriques respectifs destinés à l'émetteur. Une protection est appliquée sur l'émetteur pendant ou avant ce traitement, mais avant d'appliquer cette protection, un matériau dopant est implanté dans une région adjacente à la base, de façon à créer un chemin de basse résistance entre le contact de la base et une région de la base espacée de celui-ci.
PCT/GB1994/001787 1993-08-17 1994-08-15 Transistors bipolaires et leur procede de fabrication Ceased WO1995005679A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB9507916A GB2288069B (en) 1993-08-17 1994-08-15 Bipolar transistors and method of making the same
AU73887/94A AU7388794A (en) 1993-08-17 1994-08-15 Bipolar transistors and method of making the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB939317054A GB9317054D0 (en) 1993-08-17 1993-08-17 Semi-conductor devices and methods for making same
GB9317054.6 1993-08-17
GB939325754A GB9325754D0 (en) 1993-12-16 1993-12-16 Semiconductor devices and method for making same
GB9325754.1 1993-12-16

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Publication Number Publication Date
WO1995005679A1 true WO1995005679A1 (fr) 1995-02-23

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GB (1) GB2288069B (fr)
WO (1) WO1995005679A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2208265C2 (ru) * 2001-07-09 2003-07-10 Открытое акционерное общество НИИ молекулярной электроники и завод "МИКРОН" СПОСОБ ИЗГОТОВЛЕНИЯ БИПОЛЯРНОГО ТРАНЗИСТОРА В СОСТАВЕ БиКМОП ИС
RU2210838C2 (ru) * 2001-07-09 2003-08-20 Открытое акционерное общество "НИИ молекулярной электроники и завод "Микрон" Структура биполярного транзистора в составе бикмоп ис
RU2368036C1 (ru) * 2008-01-10 2009-09-20 Михаил Иванович Лукасевич Безэпитаксиальная структура биполярного транзистора
EP1702349A4 (fr) * 2003-12-31 2010-09-15 Freescale Semiconductor Inc Procede pour fabriquer un composant a semi-conducteurs, composant a semi-conducteurs forme selon le procede

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FR2088077A1 (fr) * 1970-05-14 1972-01-07 Radiotechnique Compelec
US5183768A (en) * 1989-04-04 1993-02-02 Matsushita Electric Industrial Co., Ltd. Method of fabricating semiconductor device by forming doped regions that limit width of the base
US5208169A (en) * 1991-06-28 1993-05-04 Texas Instruments Incorporated Method of forming high voltage bipolar transistor for a BICMOS integrated circuit

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Publication number Priority date Publication date Assignee Title
DE1943302A1 (de) * 1968-09-04 1970-03-12 Ibm Integrierte Schaltungsanordnung
FR2088077A1 (fr) * 1970-05-14 1972-01-07 Radiotechnique Compelec
US5183768A (en) * 1989-04-04 1993-02-02 Matsushita Electric Industrial Co., Ltd. Method of fabricating semiconductor device by forming doped regions that limit width of the base
US5208169A (en) * 1991-06-28 1993-05-04 Texas Instruments Incorporated Method of forming high voltage bipolar transistor for a BICMOS integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2208265C2 (ru) * 2001-07-09 2003-07-10 Открытое акционерное общество НИИ молекулярной электроники и завод "МИКРОН" СПОСОБ ИЗГОТОВЛЕНИЯ БИПОЛЯРНОГО ТРАНЗИСТОРА В СОСТАВЕ БиКМОП ИС
RU2210838C2 (ru) * 2001-07-09 2003-08-20 Открытое акционерное общество "НИИ молекулярной электроники и завод "Микрон" Структура биполярного транзистора в составе бикмоп ис
EP1702349A4 (fr) * 2003-12-31 2010-09-15 Freescale Semiconductor Inc Procede pour fabriquer un composant a semi-conducteurs, composant a semi-conducteurs forme selon le procede
RU2368036C1 (ru) * 2008-01-10 2009-09-20 Михаил Иванович Лукасевич Безэпитаксиальная структура биполярного транзистора

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GB2288069A (en) 1995-10-04
AU7388794A (en) 1995-03-14
GB2288069B (en) 1998-01-28
GB9507916D0 (en) 1995-06-14

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