WO1994018698A1

WO1994018698A1 - METHOD FOR ELECTRICALLY CONDUCTIVE CONNECTING AND MECHANICAL FASTENING OF ICs ON CONDUCTING PATTERNS OF SUBSTRATES AND THE APPLICATION THEREOF

Info

Publication number: WO1994018698A1
Application number: PCT/NL1994/000031
Authority: WO
Inventors: Hans Peter Peloschek
Original assignee: Individual
Current assignee: Individual
Priority date: 1993-02-09
Filing date: 1994-02-07
Publication date: 1994-08-18
Anticipated expiration: 1995-08-09

Abstract

This method relates to the making of electrically conducting interconnections and simultaneously mechanical fastening of integrated circuits, which are provided with bumps, on substrates with electrically conducting patterns, comprising the use of a soldermaterial as electrical interconnection medium and mechanical fastening material, which consist of a = 85 to 99,5 atomic per cent of indium, b = 0,5 to 11 atomic per cent gallium, c = 0 to 4 atomic per cent copper, and d = 0 to 2 atomic per cent gold whereby a + b + c + d = 100. This method can be used, in general, for the interconnection of bumped chips, but is extraordinary suitable for the interconnection and the fastening of ICs, which in use do not surpass 120 degrees C and whereby the substrate is glass with optically conducting patterns.

Description

Method for electrically conductive connecting and mechanically fastening of ICs on conducting patterns of substrates and the application thereof.

The invention relates to a method for electrically conductive connecting and mechanically fastening of integrated circuit (IC) chips with so-called solder-bumps on electrically conducting patterns of substrates, comprising the use of a soldering material as electrical interconnection and mechanical adhesion medium, which consists of a = 85 to 99,5 atomic percent indium, b = 0,5 to 11 atomic percent gallium, c = 0 to 4 atomic percent copper, and 0 to 2 atomic percent gold, whereby a + b + c + d = 100.

This method is, in general, applicable for the interconnection of IC-chips, but it is particularly useful for the interconnection of ICs, which during operation do not get warmer than approximately 120 degr.C and when the substrate is glass with optically transparent electrically conducting patterns.

REVIEW of the STATE of the TECHNIQUE:

The technique of conductive connecting and at the same time mechanically fastening of an IC-chip on conducting patterns of a substrate is common knowledge in the semiconductor industry, and is called "flip-chip" method.

The process is as follows: At first so-called "(solder-) bumps" are grown on the interconnection pads of the IC-chips while the chips still form an entity of the "IC-wafer".

The growth of the solder-bumps is usually done by means of a galvanic process and the top layer of such bumps consists mostly of gold. Thereafter the wafer is cut to IC-chips and these chips are fixed and electrically connected to the conducting patterns of a substrate, according to one method by means of a soldering alloy. According to another method an electrically conducting glue is used.

The greatest problem in the application of these methods is that the conducting interconnections break with the passage of time owing to aging phenomena and shear stresses, which are a consequence of the difference of the thermal expansion coefficients of the chips on the one side and the substrates on the other side. (See the literature).

When using conducting glue there is still another problem, namely that the conducting particles in the glue cannot be made in a very reproducible way and therefore variations of the conduction characteristics occur, which lead to disturbances in manufacture. Moreover, the conductivity of such glues is always inferior to alloys.

Because of the economic advantage of the flip-chip method for making interconnections, it has exhaustively been searched for soldering alloys, which exhibit less aging and can absorb more shear stress. Recently, in particular, there is search for a very reliable interconnection method of IC-chips to so-called flat panel displays with a matrix arrangement of the picture points and where each picture point is driven individually.

For this purpose driver-ICs are used, which have 300 or more interconnection points per IC-chip and rupture of a single interconnection causes already reject of the complete product. In these applications the conducting patterns are optically transparent oxidic conductors with or without a cover of a thin metallic layer.

Indium is known as ductile metal with a low melting point and forms when alloyed with tin, bismuth, lead, gallium, and other metals low melting point compositions, which are used as soldering materials

In textbooks and reference books on metals and metallurgy and in phase diagram studies many of such alloys are described. Low melting point alloys consisting of indium, mercury, gallium, and other metals are also mentioned in patents, as e.g. US-P 4 966 142, US-P 5 131 582, and mixtures of indium and gallium are soldering alloys in Czechoslowakian Patent Nr. 271586. However, these alloys are nowhere used for flip-chip applications and the interconnection of bumped IC-chips to substrates, and in particular not for fastening and electrically interconnecting driver-ICs to optically transparent electrically conducting patterns on substrates.

The use of indium and indium alloys without gallium for the direct fastening of bumped ICs on conducting patterns has been investigated. There exists an exhaustive literature about this field, see e.g.:

IEEE Transactions on Components, Hybrids, and Manufacturing Technology: Vol. CHMT-10, No.2 June 1987, pp. 263-266, Vol. CHMT-13, No.l March 1990, pp. 188-193, Vol. CHMT-13, No.4 Dec. 1990, pp. 647-655.

Also the use of low melting point indium alloys for the fastening of bumped chips on liquid crystal displays has been investigated, see e.g. Proc. ISHM'90, pp. 263-268, and Int. Electronic Manufacturing Technology, IEMT, Symp.1989, pp. 57-60 and pp. 114-118.

From the ductile indium less breakage of contacts is expected than from other soldering compositions.

Concerning the use of conducting glues for flip-chip applications, see e.g.: P. Streit, Integration of driver ICs onto liquid crystal displays, SID Internat. Symposium, Philadelphia, May 1983.

PURPOSE/NOVELTY/ ADVANTAGES/and DESCRIPTION of the INVENTION: The purpose of this invention consists in obtaining very reliable electrical interconnections of an IC-chip with the conducting patterns of a substrate, whereby the ICs are provided with so-called "bumps", and whereby sufficient mechanical bonds are created, which can durably withstand the difference in the thermal expansions of chip and substrate. In this way an excellent long term quality of the electrical and the mechanical bond is guaranteed.

The novelty of the invention consists in a further increase of the ductility of indium by adding a small amount of gallium.

For obtaining higher melting points of such alloys, so that also ICs with higher dissipative power can be treated with this method (up to approximately 200 degrees C), the melting point of the alloys can be adjusted by small additions of copper or gold. (The advantage of copper is hereby that copper can be deposited by means of a galvanic process simultaneously together with indium and gallium.) A surprising advantage of the use of indium/gallium alloys for mounting of ICs on conducting metaloxides, as indiumoxide and tinoxide and mixtures of indium/ tin oxide (TTO), as are used in various flat panel displays, consists in the excellent wetting of these optically transparent conducting patterns by the molten indium/gallium alloys. It is better than indium and other indium-containing soldering compositions and can be used without a flux. The application of the invention is done by the deposition of a thin layer of the indium/gallium alloy on the most upper (the top) layer of the bumps. This is usually a galvanically deposited layer of gold, after the bumps have been grown on the ICs by a galvanic process. The indium/gallium soldering material can be deposited by various methods, namely galvanically or by dipping of the bumps in molten soldering material.

It is also possible, instead of the bumps, to cover the conducting patterns, on which the bumped IC is to be mounted, with a thin layer of soldering material (preferentially only those places are coated on which the ICs are mounted).

Mounting of the bumped IC on the conducting patterns of the substrate occurs in such a way that the substrate and if possible the IC-chip too is heated to near the melting temperature of the used alloy. Thereafter the bumped IC is aligned with the corresponding conducting patterns and is put on the substrate with a soft pressure. Now, the substrate and the IC-chip is quickly and for a short time heated to a temperature which is above the melting temperature of the soldering alloy. Thereafter the substrate and chip are cooled as quickly as possible and without any movement. The IC-chip can now be covered with a layer of synthetic material, e.g. a not completely hardening epoxy composition, for protection against influences from the outside.

This method works best, if before heating above the melting temperature, there is a small relative movement between IC-chip and the substrate, by which movement some rubbing-in of the soldering material takes place on those locations where the IC-chip is to be mounted. This is of particular importance if no solder flux is used, which is preferred practice, and works well in those cases in which the conducting patterns of the substrate are not subject to corrosion and are made by noble metals or from oxidic conductors, as e.g. ITO.

Another advantage of the use of indium/gallium alloys as a soldering material is the virtually non-aging of these soldering compounds and the capability of compensating large shear stresses, which are created by the difference of the thermal expansion of chip and substrate, also after repeated temperature cycling. Especially all tin containing alloys suffer in the passage of time from material fatigue phenomena. The addition of gallium does not do so. The advantage of gallium/indium alloys is their unique wetting property of glass and other oxidic compounds and this is important for the mounting of IC-chips on optically transparent conducting patterns. The adhesion on gold is also very good and so a thin layer of gold or of another noble metal on the optically transparent conducting patterns can still improve the quality of the electrical interconnection. This is however not imperative.

A characteristic of the invention consists also in the use of an alloy of indium and gallium with a small amount of copper and/or gold for adjustment of the melting point and for the electrical interconnection and simultaneously the mechanical mounting of bumped IC-chips on conducting patterns and, in particular, on optically transparent electrically conducting patterns of substrates, which do have another thermal expansion coefficient than the base material of the ICs.

Examples of the practical execution of the invention: Example 1:

A so-called driver IC with approximately 300 bumps and a gold top-coating, whereby the bumps are separated by a passivation layer, is put into contact with a molten mixture of 95 atomic percent indium and 5 atomic percent of gallium. The melting point of this alloy is approximately 135 deg.C. In this way a thin layer of In/Ga is formed on the golden top-layer of the bumps. After this, the so treated chip is aligned with the conductor patterns of a liquid crystal display. Normally, the driver ICs of displays are mounted towards the edges of the display.

The display has, along the edges where the ICs are to be mounted, a temperature which is approximately between 10 and 40 deg.C below the melting temperature of the soldering alloy. The chip is put on the substrate with a mild pressure. Now, preferentially, a relative motion between chip and substrate will be produced with a vibrator (e.g. a piezoelectric element) with an amplitude of 10 to 2ft micrometer. After this, the edge of the substrate is heated for a short time above the melting temperature of the soldering alloy by switching in an infrared source, thus a molten soldering material contact is made between IC-bumps and conducting patterns.The IC is now released from the holder mechanism of the alignment device. After cooling the solder connection is ready. Cooling from the liquidus-phase of the alloy is most advantageously performed in absolute mechanical immobility and as quick as possible. The indium/gallium alloy is prepared by at first melting of indium and then adding gallium. In the case, that copper or gold is desired in the alloy, the indium/gallium mixture is heated to about 900 deg.C. Copper or gold is added in fine grain form. The total is kept at temperature until copper and/or gold is completely dissolved. It is recommended, that the alloy is prepared in an inert atmosphere or in vacuum. Example 2:

While in example 1 the soldering alloy is deposited by dipping, which does not produce a good reproduction of the thickness of the soldering alloy layer, in this example a very reproducible way is used for the deposition of the soldering alloy on the bumps of the ICs. After the bumps have been grown by a galvanic method with e.g. a top-layer of gold or copper, the wafer is rinsed in water and is immersed in an indium/gallium galvanic bath. A very reliable galvanic bath for the deposition of indium/gallium (and copper) in one process step on the bumps of ICs is a variation of the galvanic bath, which is used in the production of indium by galvany. (Described in: A.F.Taggart in Handbook of Mineral Dressing, 5th print, 1953, p.2-133, John Wiley & Sons, Inc. New York. In this recipe 200 g In2O3 is dissolved in 600 ml water and 120 ml H2SO4. Now a buffer material is added, namely 250 g crystalline sodium citrate, and the whole is diluted to 1000 ml.) To this solution gallium sulfate ( and if desired coppersulfate) is added, so that the wanted composition of the alloy and melting point is reached. For a better control of the process sometimes a lower concentration of the galvanic bath is desirable.

Electrolysis occurs with a cathode current of approximately 2A/dm2 or lower. The thickness of the layer of the soldering alloy on the bumps depends on the distance of the bumps. The smaller this distance, the thinner the layer. With bumps of approximately 100 * 100 micrometer at approximately this same distance from each other the layer thickness may grow to approximately 30 micrometer, however preferentially only to a thickness of 15 to 20 micrometer. In general, it will be chosen for an as thick as possible solder layer, because in this case the shear stress will be distributed over a larger distance.

In the described galvanic process a platinum plate can be used as anode. The process is done at room temperature. If precaution is taken against oxidation of the bump base material, which is usually copper or nickel, it is not necessary to deposit a gold or other noble metal top-layer on the bumps and the soldering alloy can directly be deposited on the bump base material. This is the case, if e.g. the various galvanic steps are executed in 5 continuous time sequences.

After the deposition of the soldering alloy on the bumps, the wafers are singulated to chips and can be mounted on the conducting patterns of a substrate in the same way as described in example 1.

According to the limits, which are given in this patent, soldering alloys 10 with melting points of approximately 105 to 200 deg.C can be made. With the lower melting point alloys IC-chips can also be mounted on conducting patterns of substrates consisting of synthetic materials with low softening and melting points, as. e.g. acrylic sheets.

!5

For the expert it will be evident that this sort of soldering alloys can also be used for other applications than those that have been mentioned.

It will also be clear for the expert how to change the composition of the alloys with respect to melting point for specific applications. Moreover, for an expert, it 0 will be clear that small amounts of conducting pattern metals can be dissolved in the molten soldering alloy, and thus the adhesion can further be improved.

Claims

CLAIMS:

1. A method for simultaneous electrically connecting and mechanically mounting of integrated circuit chips, which are provided with solder bumps, on electrically conducting patterns of a substrate, comprising a soldering material as electrical interconnection conductor and mechanical adhesion medium, which consists of a = 85 to 99,5 atomic percent INDIUM, b = 0.5 to 11 atomic percent GALLIUM, c = 0 to 4 atomic percent COPPER, and d = 0 to 2 atomic percent GOLD, whereby a + b + c + d = 100.

2. A method according to claim 1, comprisinga soldering material consisting of a = 90 to 97 atomic % INDIUM, b = 3 to 8 atomic % GALLIUM, and c = 0 to 2 atomic % COPPER, whereby a + b + c = 100.

3. Method according to claim 1 or 1 and 2, comprisinga galvanic process for the deposition of the soldering material on the bumps of the IC-chips.

4. Method according to one or more of the claims 1 to 3, comprising the use of one buffered galvanic sulfate bath for the deposition of the components indium, gallium, and copper of the soldering material on the bumps of the ICs of a wafer.

5. Method according to one or more of the claims 1 to 4, comprising thin metallic layers which form the electrically conducting patterns of the substrate.

6. Method according to one or more of the claims 1 to 4, comprising electrically conducting patterns on the substrate which consist of optically transparent metal oxides.

7. Method according to one or more of the claims 1 to 4 and 6, comprising electrically conductive patterns on the substrate which consist of a mixture of indium-tin-oxide.

8. Method according to one or more of the claims 1 to 4, 6, and 7, comprising electrically conducting patterns on the substrate which consist of a mixture of indium-tin-oxide with thereon a thin layer of metal.

9. Method according to one or more of the claims 1 to 4 and 6 to 8, comprising electrically conducting patterns on the substrate which consist of a mixture of indium-tin-oxide with thereon a thin layer of gold.

10. Method according to one or more of the claims 1 to 4 and 6 to 9, comprising electrically conducting patterns on the substrate which consist of a mixture of indium-tin-oxide with thereon a layer of a metal on only those locations where there are contacts for bumps of an IC.

11. Method according to one or more of the claims 1 to 10, comprising the deposition of the soldering material on the conducting patterns of the substrate.

12. Method according to one or more of the claims 1 to 11, comprising other thermal expansion coefficients of the substrate on the one side and the basic material of the bumped IC-chip on the other side.

13. Method according to one or more of the claims 1 to 12, comprising a substrate of glass on which the conducting patterns are provided.

14. Method according to one or more of the claims 1 to 12, comprising a substrate consisting of a ceramic material on which the conducting patterns for the interconnection of IC-chips are provided.

15. Method according to one or more of the claims 1 to 12 and 14, comprising a substrate consisting of a ceramic material with a high content of alumina on which the conducting patterns for the interconnection of bumped IC-chips are provided.

16. Method according to one or more of the claims 1 to 12, comprising a substrate consisting of a composite material made of a synthetic material matrix, produced on the basis of organic chemical synthesis and a filling of inorganic materials on which the conducting patterns for the interconnection of bumped IC-chips are provided.

17. Method according to one or more of the claims 1 to 12, comprising a substrate consisting of a flexible material which is produced on the basis of organic chemical synthesis on which the conducting patterns for the interconnection of bumped IC-chips are provided.

18. Method according to one or more of the claims 1 to 12 , comprising a substrate consisting of a non-flexible material, which is produced on the basis of organic chemical synthesis, on which the conducting patterns for the interconnection of bumped IC-chips are provided.